| File: | src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Support/Alignment.h |
| Warning: | line 85, column 47 The result of the left shift is undefined due to shifting by '255', which is greater or equal to the width of type 'uint64_t' |
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| 1 | //===-- X86FastISel.cpp - X86 FastISel implementation ---------------------===// | ||||||||
| 2 | // | ||||||||
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | ||||||||
| 4 | // See https://llvm.org/LICENSE.txt for license information. | ||||||||
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||||||||
| 6 | // | ||||||||
| 7 | //===----------------------------------------------------------------------===// | ||||||||
| 8 | // | ||||||||
| 9 | // This file defines the X86-specific support for the FastISel class. Much | ||||||||
| 10 | // of the target-specific code is generated by tablegen in the file | ||||||||
| 11 | // X86GenFastISel.inc, which is #included here. | ||||||||
| 12 | // | ||||||||
| 13 | //===----------------------------------------------------------------------===// | ||||||||
| 14 | |||||||||
| 15 | #include "X86.h" | ||||||||
| 16 | #include "X86CallingConv.h" | ||||||||
| 17 | #include "X86InstrBuilder.h" | ||||||||
| 18 | #include "X86InstrInfo.h" | ||||||||
| 19 | #include "X86MachineFunctionInfo.h" | ||||||||
| 20 | #include "X86RegisterInfo.h" | ||||||||
| 21 | #include "X86Subtarget.h" | ||||||||
| 22 | #include "X86TargetMachine.h" | ||||||||
| 23 | #include "llvm/Analysis/BranchProbabilityInfo.h" | ||||||||
| 24 | #include "llvm/CodeGen/FastISel.h" | ||||||||
| 25 | #include "llvm/CodeGen/FunctionLoweringInfo.h" | ||||||||
| 26 | #include "llvm/CodeGen/MachineConstantPool.h" | ||||||||
| 27 | #include "llvm/CodeGen/MachineFrameInfo.h" | ||||||||
| 28 | #include "llvm/CodeGen/MachineRegisterInfo.h" | ||||||||
| 29 | #include "llvm/IR/CallingConv.h" | ||||||||
| 30 | #include "llvm/IR/DebugInfo.h" | ||||||||
| 31 | #include "llvm/IR/DerivedTypes.h" | ||||||||
| 32 | #include "llvm/IR/GetElementPtrTypeIterator.h" | ||||||||
| 33 | #include "llvm/IR/GlobalAlias.h" | ||||||||
| 34 | #include "llvm/IR/GlobalVariable.h" | ||||||||
| 35 | #include "llvm/IR/Instructions.h" | ||||||||
| 36 | #include "llvm/IR/IntrinsicInst.h" | ||||||||
| 37 | #include "llvm/IR/IntrinsicsX86.h" | ||||||||
| 38 | #include "llvm/IR/Operator.h" | ||||||||
| 39 | #include "llvm/MC/MCAsmInfo.h" | ||||||||
| 40 | #include "llvm/MC/MCSymbol.h" | ||||||||
| 41 | #include "llvm/Support/ErrorHandling.h" | ||||||||
| 42 | #include "llvm/Target/TargetOptions.h" | ||||||||
| 43 | using namespace llvm; | ||||||||
| 44 | |||||||||
| 45 | namespace { | ||||||||
| 46 | |||||||||
| 47 | class X86FastISel final : public FastISel { | ||||||||
| 48 | /// Subtarget - Keep a pointer to the X86Subtarget around so that we can | ||||||||
| 49 | /// make the right decision when generating code for different targets. | ||||||||
| 50 | const X86Subtarget *Subtarget; | ||||||||
| 51 | |||||||||
| 52 | /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 | ||||||||
| 53 | /// floating point ops. | ||||||||
| 54 | /// When SSE is available, use it for f32 operations. | ||||||||
| 55 | /// When SSE2 is available, use it for f64 operations. | ||||||||
| 56 | bool X86ScalarSSEf64; | ||||||||
| 57 | bool X86ScalarSSEf32; | ||||||||
| 58 | |||||||||
| 59 | public: | ||||||||
| 60 | explicit X86FastISel(FunctionLoweringInfo &funcInfo, | ||||||||
| 61 | const TargetLibraryInfo *libInfo) | ||||||||
| 62 | : FastISel(funcInfo, libInfo) { | ||||||||
| 63 | Subtarget = &funcInfo.MF->getSubtarget<X86Subtarget>(); | ||||||||
| 64 | X86ScalarSSEf64 = Subtarget->hasSSE2(); | ||||||||
| 65 | X86ScalarSSEf32 = Subtarget->hasSSE1(); | ||||||||
| 66 | } | ||||||||
| 67 | |||||||||
| 68 | bool fastSelectInstruction(const Instruction *I) override; | ||||||||
| 69 | |||||||||
| 70 | /// The specified machine instr operand is a vreg, and that | ||||||||
| 71 | /// vreg is being provided by the specified load instruction. If possible, | ||||||||
| 72 | /// try to fold the load as an operand to the instruction, returning true if | ||||||||
| 73 | /// possible. | ||||||||
| 74 | bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, | ||||||||
| 75 | const LoadInst *LI) override; | ||||||||
| 76 | |||||||||
| 77 | bool fastLowerArguments() override; | ||||||||
| 78 | bool fastLowerCall(CallLoweringInfo &CLI) override; | ||||||||
| 79 | bool fastLowerIntrinsicCall(const IntrinsicInst *II) override; | ||||||||
| 80 | |||||||||
| 81 | #include "X86GenFastISel.inc" | ||||||||
| 82 | |||||||||
| 83 | private: | ||||||||
| 84 | bool X86FastEmitCompare(const Value *LHS, const Value *RHS, EVT VT, | ||||||||
| 85 | const DebugLoc &DL); | ||||||||
| 86 | |||||||||
| 87 | bool X86FastEmitLoad(MVT VT, X86AddressMode &AM, MachineMemOperand *MMO, | ||||||||
| 88 | unsigned &ResultReg, unsigned Alignment = 1); | ||||||||
| 89 | |||||||||
| 90 | bool X86FastEmitStore(EVT VT, const Value *Val, X86AddressMode &AM, | ||||||||
| 91 | MachineMemOperand *MMO = nullptr, bool Aligned = false); | ||||||||
| 92 | bool X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM, | ||||||||
| 93 | MachineMemOperand *MMO = nullptr, bool Aligned = false); | ||||||||
| 94 | |||||||||
| 95 | bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, | ||||||||
| 96 | unsigned &ResultReg); | ||||||||
| 97 | |||||||||
| 98 | bool X86SelectAddress(const Value *V, X86AddressMode &AM); | ||||||||
| 99 | bool X86SelectCallAddress(const Value *V, X86AddressMode &AM); | ||||||||
| 100 | |||||||||
| 101 | bool X86SelectLoad(const Instruction *I); | ||||||||
| 102 | |||||||||
| 103 | bool X86SelectStore(const Instruction *I); | ||||||||
| 104 | |||||||||
| 105 | bool X86SelectRet(const Instruction *I); | ||||||||
| 106 | |||||||||
| 107 | bool X86SelectCmp(const Instruction *I); | ||||||||
| 108 | |||||||||
| 109 | bool X86SelectZExt(const Instruction *I); | ||||||||
| 110 | |||||||||
| 111 | bool X86SelectSExt(const Instruction *I); | ||||||||
| 112 | |||||||||
| 113 | bool X86SelectBranch(const Instruction *I); | ||||||||
| 114 | |||||||||
| 115 | bool X86SelectShift(const Instruction *I); | ||||||||
| 116 | |||||||||
| 117 | bool X86SelectDivRem(const Instruction *I); | ||||||||
| 118 | |||||||||
| 119 | bool X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I); | ||||||||
| 120 | |||||||||
| 121 | bool X86FastEmitSSESelect(MVT RetVT, const Instruction *I); | ||||||||
| 122 | |||||||||
| 123 | bool X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I); | ||||||||
| 124 | |||||||||
| 125 | bool X86SelectSelect(const Instruction *I); | ||||||||
| 126 | |||||||||
| 127 | bool X86SelectTrunc(const Instruction *I); | ||||||||
| 128 | |||||||||
| 129 | bool X86SelectFPExtOrFPTrunc(const Instruction *I, unsigned Opc, | ||||||||
| 130 | const TargetRegisterClass *RC); | ||||||||
| 131 | |||||||||
| 132 | bool X86SelectFPExt(const Instruction *I); | ||||||||
| 133 | bool X86SelectFPTrunc(const Instruction *I); | ||||||||
| 134 | bool X86SelectSIToFP(const Instruction *I); | ||||||||
| 135 | bool X86SelectUIToFP(const Instruction *I); | ||||||||
| 136 | bool X86SelectIntToFP(const Instruction *I, bool IsSigned); | ||||||||
| 137 | |||||||||
| 138 | const X86InstrInfo *getInstrInfo() const { | ||||||||
| 139 | return Subtarget->getInstrInfo(); | ||||||||
| 140 | } | ||||||||
| 141 | const X86TargetMachine *getTargetMachine() const { | ||||||||
| 142 | return static_cast<const X86TargetMachine *>(&TM); | ||||||||
| 143 | } | ||||||||
| 144 | |||||||||
| 145 | bool handleConstantAddresses(const Value *V, X86AddressMode &AM); | ||||||||
| 146 | |||||||||
| 147 | unsigned X86MaterializeInt(const ConstantInt *CI, MVT VT); | ||||||||
| 148 | unsigned X86MaterializeFP(const ConstantFP *CFP, MVT VT); | ||||||||
| 149 | unsigned X86MaterializeGV(const GlobalValue *GV, MVT VT); | ||||||||
| 150 | unsigned fastMaterializeConstant(const Constant *C) override; | ||||||||
| 151 | |||||||||
| 152 | unsigned fastMaterializeAlloca(const AllocaInst *C) override; | ||||||||
| 153 | |||||||||
| 154 | unsigned fastMaterializeFloatZero(const ConstantFP *CF) override; | ||||||||
| 155 | |||||||||
| 156 | /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is | ||||||||
| 157 | /// computed in an SSE register, not on the X87 floating point stack. | ||||||||
| 158 | bool isScalarFPTypeInSSEReg(EVT VT) const { | ||||||||
| 159 | return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2 | ||||||||
| 160 | (VT == MVT::f32 && X86ScalarSSEf32); // f32 is when SSE1 | ||||||||
| 161 | } | ||||||||
| 162 | |||||||||
| 163 | bool isTypeLegal(Type *Ty, MVT &VT, bool AllowI1 = false); | ||||||||
| 164 | |||||||||
| 165 | bool IsMemcpySmall(uint64_t Len); | ||||||||
| 166 | |||||||||
| 167 | bool TryEmitSmallMemcpy(X86AddressMode DestAM, | ||||||||
| 168 | X86AddressMode SrcAM, uint64_t Len); | ||||||||
| 169 | |||||||||
| 170 | bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I, | ||||||||
| 171 | const Value *Cond); | ||||||||
| 172 | |||||||||
| 173 | const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB, | ||||||||
| 174 | X86AddressMode &AM); | ||||||||
| 175 | |||||||||
| 176 | unsigned fastEmitInst_rrrr(unsigned MachineInstOpcode, | ||||||||
| 177 | const TargetRegisterClass *RC, unsigned Op0, | ||||||||
| 178 | unsigned Op1, unsigned Op2, unsigned Op3); | ||||||||
| 179 | }; | ||||||||
| 180 | |||||||||
| 181 | } // end anonymous namespace. | ||||||||
| 182 | |||||||||
| 183 | static std::pair<unsigned, bool> | ||||||||
| 184 | getX86SSEConditionCode(CmpInst::Predicate Predicate) { | ||||||||
| 185 | unsigned CC; | ||||||||
| 186 | bool NeedSwap = false; | ||||||||
| 187 | |||||||||
| 188 | // SSE Condition code mapping: | ||||||||
| 189 | // 0 - EQ | ||||||||
| 190 | // 1 - LT | ||||||||
| 191 | // 2 - LE | ||||||||
| 192 | // 3 - UNORD | ||||||||
| 193 | // 4 - NEQ | ||||||||
| 194 | // 5 - NLT | ||||||||
| 195 | // 6 - NLE | ||||||||
| 196 | // 7 - ORD | ||||||||
| 197 | switch (Predicate) { | ||||||||
| 198 | default: llvm_unreachable("Unexpected predicate")__builtin_unreachable(); | ||||||||
| 199 | case CmpInst::FCMP_OEQ: CC = 0; break; | ||||||||
| 200 | case CmpInst::FCMP_OGT: NeedSwap = true; LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||
| 201 | case CmpInst::FCMP_OLT: CC = 1; break; | ||||||||
| 202 | case CmpInst::FCMP_OGE: NeedSwap = true; LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||
| 203 | case CmpInst::FCMP_OLE: CC = 2; break; | ||||||||
| 204 | case CmpInst::FCMP_UNO: CC = 3; break; | ||||||||
| 205 | case CmpInst::FCMP_UNE: CC = 4; break; | ||||||||
| 206 | case CmpInst::FCMP_ULE: NeedSwap = true; LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||
| 207 | case CmpInst::FCMP_UGE: CC = 5; break; | ||||||||
| 208 | case CmpInst::FCMP_ULT: NeedSwap = true; LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||
| 209 | case CmpInst::FCMP_UGT: CC = 6; break; | ||||||||
| 210 | case CmpInst::FCMP_ORD: CC = 7; break; | ||||||||
| 211 | case CmpInst::FCMP_UEQ: CC = 8; break; | ||||||||
| 212 | case CmpInst::FCMP_ONE: CC = 12; break; | ||||||||
| 213 | } | ||||||||
| 214 | |||||||||
| 215 | return std::make_pair(CC, NeedSwap); | ||||||||
| 216 | } | ||||||||
| 217 | |||||||||
| 218 | /// Adds a complex addressing mode to the given machine instr builder. | ||||||||
| 219 | /// Note, this will constrain the index register. If its not possible to | ||||||||
| 220 | /// constrain the given index register, then a new one will be created. The | ||||||||
| 221 | /// IndexReg field of the addressing mode will be updated to match in this case. | ||||||||
| 222 | const MachineInstrBuilder & | ||||||||
| 223 | X86FastISel::addFullAddress(const MachineInstrBuilder &MIB, | ||||||||
| 224 | X86AddressMode &AM) { | ||||||||
| 225 | // First constrain the index register. It needs to be a GR64_NOSP. | ||||||||
| 226 | AM.IndexReg = constrainOperandRegClass(MIB->getDesc(), AM.IndexReg, | ||||||||
| 227 | MIB->getNumOperands() + | ||||||||
| 228 | X86::AddrIndexReg); | ||||||||
| 229 | return ::addFullAddress(MIB, AM); | ||||||||
| 230 | } | ||||||||
| 231 | |||||||||
| 232 | /// Check if it is possible to fold the condition from the XALU intrinsic | ||||||||
| 233 | /// into the user. The condition code will only be updated on success. | ||||||||
| 234 | bool X86FastISel::foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I, | ||||||||
| 235 | const Value *Cond) { | ||||||||
| 236 | if (!isa<ExtractValueInst>(Cond)) | ||||||||
| 237 | return false; | ||||||||
| 238 | |||||||||
| 239 | const auto *EV = cast<ExtractValueInst>(Cond); | ||||||||
| 240 | if (!isa<IntrinsicInst>(EV->getAggregateOperand())) | ||||||||
| 241 | return false; | ||||||||
| 242 | |||||||||
| 243 | const auto *II = cast<IntrinsicInst>(EV->getAggregateOperand()); | ||||||||
| 244 | MVT RetVT; | ||||||||
| 245 | const Function *Callee = II->getCalledFunction(); | ||||||||
| 246 | Type *RetTy = | ||||||||
| 247 | cast<StructType>(Callee->getReturnType())->getTypeAtIndex(0U); | ||||||||
| 248 | if (!isTypeLegal(RetTy, RetVT)) | ||||||||
| 249 | return false; | ||||||||
| 250 | |||||||||
| 251 | if (RetVT != MVT::i32 && RetVT != MVT::i64) | ||||||||
| 252 | return false; | ||||||||
| 253 | |||||||||
| 254 | X86::CondCode TmpCC; | ||||||||
| 255 | switch (II->getIntrinsicID()) { | ||||||||
| 256 | default: return false; | ||||||||
| 257 | case Intrinsic::sadd_with_overflow: | ||||||||
| 258 | case Intrinsic::ssub_with_overflow: | ||||||||
| 259 | case Intrinsic::smul_with_overflow: | ||||||||
| 260 | case Intrinsic::umul_with_overflow: TmpCC = X86::COND_O; break; | ||||||||
| 261 | case Intrinsic::uadd_with_overflow: | ||||||||
| 262 | case Intrinsic::usub_with_overflow: TmpCC = X86::COND_B; break; | ||||||||
| 263 | } | ||||||||
| 264 | |||||||||
| 265 | // Check if both instructions are in the same basic block. | ||||||||
| 266 | if (II->getParent() != I->getParent()) | ||||||||
| 267 | return false; | ||||||||
| 268 | |||||||||
| 269 | // Make sure nothing is in the way | ||||||||
| 270 | BasicBlock::const_iterator Start(I); | ||||||||
| 271 | BasicBlock::const_iterator End(II); | ||||||||
| 272 | for (auto Itr = std::prev(Start); Itr != End; --Itr) { | ||||||||
| 273 | // We only expect extractvalue instructions between the intrinsic and the | ||||||||
| 274 | // instruction to be selected. | ||||||||
| 275 | if (!isa<ExtractValueInst>(Itr)) | ||||||||
| 276 | return false; | ||||||||
| 277 | |||||||||
| 278 | // Check that the extractvalue operand comes from the intrinsic. | ||||||||
| 279 | const auto *EVI = cast<ExtractValueInst>(Itr); | ||||||||
| 280 | if (EVI->getAggregateOperand() != II) | ||||||||
| 281 | return false; | ||||||||
| 282 | } | ||||||||
| 283 | |||||||||
| 284 | // Make sure no potentially eflags clobbering phi moves can be inserted in | ||||||||
| 285 | // between. | ||||||||
| 286 | auto HasPhis = [](const BasicBlock *Succ) { | ||||||||
| 287 | return !llvm::empty(Succ->phis()); | ||||||||
| 288 | }; | ||||||||
| 289 | if (I->isTerminator() && llvm::any_of(successors(I), HasPhis)) | ||||||||
| 290 | return false; | ||||||||
| 291 | |||||||||
| 292 | CC = TmpCC; | ||||||||
| 293 | return true; | ||||||||
| 294 | } | ||||||||
| 295 | |||||||||
| 296 | bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { | ||||||||
| 297 | EVT evt = TLI.getValueType(DL, Ty, /*AllowUnknown=*/true); | ||||||||
| 298 | if (evt == MVT::Other || !evt.isSimple()) | ||||||||
| 299 | // Unhandled type. Halt "fast" selection and bail. | ||||||||
| 300 | return false; | ||||||||
| 301 | |||||||||
| 302 | VT = evt.getSimpleVT(); | ||||||||
| 303 | // For now, require SSE/SSE2 for performing floating-point operations, | ||||||||
| 304 | // since x87 requires additional work. | ||||||||
| 305 | if (VT == MVT::f64 && !X86ScalarSSEf64) | ||||||||
| 306 | return false; | ||||||||
| 307 | if (VT == MVT::f32 && !X86ScalarSSEf32) | ||||||||
| 308 | return false; | ||||||||
| 309 | // Similarly, no f80 support yet. | ||||||||
| 310 | if (VT == MVT::f80) | ||||||||
| 311 | return false; | ||||||||
| 312 | // We only handle legal types. For example, on x86-32 the instruction | ||||||||
| 313 | // selector contains all of the 64-bit instructions from x86-64, | ||||||||
| 314 | // under the assumption that i64 won't be used if the target doesn't | ||||||||
| 315 | // support it. | ||||||||
| 316 | return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); | ||||||||
| 317 | } | ||||||||
| 318 | |||||||||
| 319 | /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT. | ||||||||
| 320 | /// The address is either pre-computed, i.e. Ptr, or a GlobalAddress, i.e. GV. | ||||||||
| 321 | /// Return true and the result register by reference if it is possible. | ||||||||
| 322 | bool X86FastISel::X86FastEmitLoad(MVT VT, X86AddressMode &AM, | ||||||||
| 323 | MachineMemOperand *MMO, unsigned &ResultReg, | ||||||||
| 324 | unsigned Alignment) { | ||||||||
| 325 | bool HasSSE41 = Subtarget->hasSSE41(); | ||||||||
| 326 | bool HasAVX = Subtarget->hasAVX(); | ||||||||
| 327 | bool HasAVX2 = Subtarget->hasAVX2(); | ||||||||
| 328 | bool HasAVX512 = Subtarget->hasAVX512(); | ||||||||
| 329 | bool HasVLX = Subtarget->hasVLX(); | ||||||||
| 330 | bool IsNonTemporal = MMO && MMO->isNonTemporal(); | ||||||||
| 331 | |||||||||
| 332 | // Treat i1 loads the same as i8 loads. Masking will be done when storing. | ||||||||
| 333 | if (VT == MVT::i1) | ||||||||
| 334 | VT = MVT::i8; | ||||||||
| 335 | |||||||||
| 336 | // Get opcode and regclass of the output for the given load instruction. | ||||||||
| 337 | unsigned Opc = 0; | ||||||||
| 338 | switch (VT.SimpleTy) { | ||||||||
| 339 | default: return false; | ||||||||
| 340 | case MVT::i8: | ||||||||
| 341 | Opc = X86::MOV8rm; | ||||||||
| 342 | break; | ||||||||
| 343 | case MVT::i16: | ||||||||
| 344 | Opc = X86::MOV16rm; | ||||||||
| 345 | break; | ||||||||
| 346 | case MVT::i32: | ||||||||
| 347 | Opc = X86::MOV32rm; | ||||||||
| 348 | break; | ||||||||
| 349 | case MVT::i64: | ||||||||
| 350 | // Must be in x86-64 mode. | ||||||||
| 351 | Opc = X86::MOV64rm; | ||||||||
| 352 | break; | ||||||||
| 353 | case MVT::f32: | ||||||||
| 354 | if (X86ScalarSSEf32) | ||||||||
| 355 | Opc = HasAVX512 ? X86::VMOVSSZrm_alt : | ||||||||
| 356 | HasAVX ? X86::VMOVSSrm_alt : | ||||||||
| 357 | X86::MOVSSrm_alt; | ||||||||
| 358 | else | ||||||||
| 359 | Opc = X86::LD_Fp32m; | ||||||||
| 360 | break; | ||||||||
| 361 | case MVT::f64: | ||||||||
| 362 | if (X86ScalarSSEf64) | ||||||||
| 363 | Opc = HasAVX512 ? X86::VMOVSDZrm_alt : | ||||||||
| 364 | HasAVX ? X86::VMOVSDrm_alt : | ||||||||
| 365 | X86::MOVSDrm_alt; | ||||||||
| 366 | else | ||||||||
| 367 | Opc = X86::LD_Fp64m; | ||||||||
| 368 | break; | ||||||||
| 369 | case MVT::f80: | ||||||||
| 370 | // No f80 support yet. | ||||||||
| 371 | return false; | ||||||||
| 372 | case MVT::v4f32: | ||||||||
| 373 | if (IsNonTemporal && Alignment >= 16 && HasSSE41) | ||||||||
| 374 | Opc = HasVLX ? X86::VMOVNTDQAZ128rm : | ||||||||
| 375 | HasAVX ? X86::VMOVNTDQArm : X86::MOVNTDQArm; | ||||||||
| 376 | else if (Alignment >= 16) | ||||||||
| 377 | Opc = HasVLX ? X86::VMOVAPSZ128rm : | ||||||||
| 378 | HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm; | ||||||||
| 379 | else | ||||||||
| 380 | Opc = HasVLX ? X86::VMOVUPSZ128rm : | ||||||||
| 381 | HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm; | ||||||||
| 382 | break; | ||||||||
| 383 | case MVT::v2f64: | ||||||||
| 384 | if (IsNonTemporal && Alignment >= 16 && HasSSE41) | ||||||||
| 385 | Opc = HasVLX ? X86::VMOVNTDQAZ128rm : | ||||||||
| 386 | HasAVX ? X86::VMOVNTDQArm : X86::MOVNTDQArm; | ||||||||
| 387 | else if (Alignment >= 16) | ||||||||
| 388 | Opc = HasVLX ? X86::VMOVAPDZ128rm : | ||||||||
| 389 | HasAVX ? X86::VMOVAPDrm : X86::MOVAPDrm; | ||||||||
| 390 | else | ||||||||
| 391 | Opc = HasVLX ? X86::VMOVUPDZ128rm : | ||||||||
| 392 | HasAVX ? X86::VMOVUPDrm : X86::MOVUPDrm; | ||||||||
| 393 | break; | ||||||||
| 394 | case MVT::v4i32: | ||||||||
| 395 | case MVT::v2i64: | ||||||||
| 396 | case MVT::v8i16: | ||||||||
| 397 | case MVT::v16i8: | ||||||||
| 398 | if (IsNonTemporal && Alignment >= 16 && HasSSE41) | ||||||||
| 399 | Opc = HasVLX ? X86::VMOVNTDQAZ128rm : | ||||||||
| 400 | HasAVX ? X86::VMOVNTDQArm : X86::MOVNTDQArm; | ||||||||
| 401 | else if (Alignment >= 16) | ||||||||
| 402 | Opc = HasVLX ? X86::VMOVDQA64Z128rm : | ||||||||
| 403 | HasAVX ? X86::VMOVDQArm : X86::MOVDQArm; | ||||||||
| 404 | else | ||||||||
| 405 | Opc = HasVLX ? X86::VMOVDQU64Z128rm : | ||||||||
| 406 | HasAVX ? X86::VMOVDQUrm : X86::MOVDQUrm; | ||||||||
| 407 | break; | ||||||||
| 408 | case MVT::v8f32: | ||||||||
| 409 | assert(HasAVX)((void)0); | ||||||||
| 410 | if (IsNonTemporal && Alignment >= 32 && HasAVX2) | ||||||||
| 411 | Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm; | ||||||||
| 412 | else if (IsNonTemporal && Alignment >= 16) | ||||||||
| 413 | return false; // Force split for X86::VMOVNTDQArm | ||||||||
| 414 | else if (Alignment >= 32) | ||||||||
| 415 | Opc = HasVLX ? X86::VMOVAPSZ256rm : X86::VMOVAPSYrm; | ||||||||
| 416 | else | ||||||||
| 417 | Opc = HasVLX ? X86::VMOVUPSZ256rm : X86::VMOVUPSYrm; | ||||||||
| 418 | break; | ||||||||
| 419 | case MVT::v4f64: | ||||||||
| 420 | assert(HasAVX)((void)0); | ||||||||
| 421 | if (IsNonTemporal && Alignment >= 32 && HasAVX2) | ||||||||
| 422 | Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm; | ||||||||
| 423 | else if (IsNonTemporal && Alignment >= 16) | ||||||||
| 424 | return false; // Force split for X86::VMOVNTDQArm | ||||||||
| 425 | else if (Alignment >= 32) | ||||||||
| 426 | Opc = HasVLX ? X86::VMOVAPDZ256rm : X86::VMOVAPDYrm; | ||||||||
| 427 | else | ||||||||
| 428 | Opc = HasVLX ? X86::VMOVUPDZ256rm : X86::VMOVUPDYrm; | ||||||||
| 429 | break; | ||||||||
| 430 | case MVT::v8i32: | ||||||||
| 431 | case MVT::v4i64: | ||||||||
| 432 | case MVT::v16i16: | ||||||||
| 433 | case MVT::v32i8: | ||||||||
| 434 | assert(HasAVX)((void)0); | ||||||||
| 435 | if (IsNonTemporal && Alignment >= 32 && HasAVX2) | ||||||||
| 436 | Opc = HasVLX ? X86::VMOVNTDQAZ256rm : X86::VMOVNTDQAYrm; | ||||||||
| 437 | else if (IsNonTemporal && Alignment >= 16) | ||||||||
| 438 | return false; // Force split for X86::VMOVNTDQArm | ||||||||
| 439 | else if (Alignment >= 32) | ||||||||
| 440 | Opc = HasVLX ? X86::VMOVDQA64Z256rm : X86::VMOVDQAYrm; | ||||||||
| 441 | else | ||||||||
| 442 | Opc = HasVLX ? X86::VMOVDQU64Z256rm : X86::VMOVDQUYrm; | ||||||||
| 443 | break; | ||||||||
| 444 | case MVT::v16f32: | ||||||||
| 445 | assert(HasAVX512)((void)0); | ||||||||
| 446 | if (IsNonTemporal && Alignment >= 64) | ||||||||
| 447 | Opc = X86::VMOVNTDQAZrm; | ||||||||
| 448 | else | ||||||||
| 449 | Opc = (Alignment >= 64) ? X86::VMOVAPSZrm : X86::VMOVUPSZrm; | ||||||||
| 450 | break; | ||||||||
| 451 | case MVT::v8f64: | ||||||||
| 452 | assert(HasAVX512)((void)0); | ||||||||
| 453 | if (IsNonTemporal && Alignment >= 64) | ||||||||
| 454 | Opc = X86::VMOVNTDQAZrm; | ||||||||
| 455 | else | ||||||||
| 456 | Opc = (Alignment >= 64) ? X86::VMOVAPDZrm : X86::VMOVUPDZrm; | ||||||||
| 457 | break; | ||||||||
| 458 | case MVT::v8i64: | ||||||||
| 459 | case MVT::v16i32: | ||||||||
| 460 | case MVT::v32i16: | ||||||||
| 461 | case MVT::v64i8: | ||||||||
| 462 | assert(HasAVX512)((void)0); | ||||||||
| 463 | // Note: There are a lot more choices based on type with AVX-512, but | ||||||||
| 464 | // there's really no advantage when the load isn't masked. | ||||||||
| 465 | if (IsNonTemporal && Alignment >= 64) | ||||||||
| 466 | Opc = X86::VMOVNTDQAZrm; | ||||||||
| 467 | else | ||||||||
| 468 | Opc = (Alignment >= 64) ? X86::VMOVDQA64Zrm : X86::VMOVDQU64Zrm; | ||||||||
| 469 | break; | ||||||||
| 470 | } | ||||||||
| 471 | |||||||||
| 472 | const TargetRegisterClass *RC = TLI.getRegClassFor(VT); | ||||||||
| 473 | |||||||||
| 474 | ResultReg = createResultReg(RC); | ||||||||
| 475 | MachineInstrBuilder MIB = | ||||||||
| 476 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); | ||||||||
| 477 | addFullAddress(MIB, AM); | ||||||||
| 478 | if (MMO) | ||||||||
| 479 | MIB->addMemOperand(*FuncInfo.MF, MMO); | ||||||||
| 480 | return true; | ||||||||
| 481 | } | ||||||||
| 482 | |||||||||
| 483 | /// X86FastEmitStore - Emit a machine instruction to store a value Val of | ||||||||
| 484 | /// type VT. The address is either pre-computed, consisted of a base ptr, Ptr | ||||||||
| 485 | /// and a displacement offset, or a GlobalAddress, | ||||||||
| 486 | /// i.e. V. Return true if it is possible. | ||||||||
| 487 | bool X86FastISel::X86FastEmitStore(EVT VT, unsigned ValReg, X86AddressMode &AM, | ||||||||
| 488 | MachineMemOperand *MMO, bool Aligned) { | ||||||||
| 489 | bool HasSSE1 = Subtarget->hasSSE1(); | ||||||||
| 490 | bool HasSSE2 = Subtarget->hasSSE2(); | ||||||||
| 491 | bool HasSSE4A = Subtarget->hasSSE4A(); | ||||||||
| 492 | bool HasAVX = Subtarget->hasAVX(); | ||||||||
| 493 | bool HasAVX512 = Subtarget->hasAVX512(); | ||||||||
| 494 | bool HasVLX = Subtarget->hasVLX(); | ||||||||
| 495 | bool IsNonTemporal = MMO && MMO->isNonTemporal(); | ||||||||
| 496 | |||||||||
| 497 | // Get opcode and regclass of the output for the given store instruction. | ||||||||
| 498 | unsigned Opc = 0; | ||||||||
| 499 | switch (VT.getSimpleVT().SimpleTy) { | ||||||||
| 500 | case MVT::f80: // No f80 support yet. | ||||||||
| 501 | default: return false; | ||||||||
| 502 | case MVT::i1: { | ||||||||
| 503 | // Mask out all but lowest bit. | ||||||||
| 504 | Register AndResult = createResultReg(&X86::GR8RegClass); | ||||||||
| 505 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 506 | TII.get(X86::AND8ri), AndResult) | ||||||||
| 507 | .addReg(ValReg).addImm(1); | ||||||||
| 508 | ValReg = AndResult; | ||||||||
| 509 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; // handle i1 as i8. | ||||||||
| 510 | } | ||||||||
| 511 | case MVT::i8: Opc = X86::MOV8mr; break; | ||||||||
| 512 | case MVT::i16: Opc = X86::MOV16mr; break; | ||||||||
| 513 | case MVT::i32: | ||||||||
| 514 | Opc = (IsNonTemporal && HasSSE2) ? X86::MOVNTImr : X86::MOV32mr; | ||||||||
| 515 | break; | ||||||||
| 516 | case MVT::i64: | ||||||||
| 517 | // Must be in x86-64 mode. | ||||||||
| 518 | Opc = (IsNonTemporal && HasSSE2) ? X86::MOVNTI_64mr : X86::MOV64mr; | ||||||||
| 519 | break; | ||||||||
| 520 | case MVT::f32: | ||||||||
| 521 | if (X86ScalarSSEf32) { | ||||||||
| 522 | if (IsNonTemporal && HasSSE4A) | ||||||||
| 523 | Opc = X86::MOVNTSS; | ||||||||
| 524 | else | ||||||||
| 525 | Opc = HasAVX512 ? X86::VMOVSSZmr : | ||||||||
| 526 | HasAVX ? X86::VMOVSSmr : X86::MOVSSmr; | ||||||||
| 527 | } else | ||||||||
| 528 | Opc = X86::ST_Fp32m; | ||||||||
| 529 | break; | ||||||||
| 530 | case MVT::f64: | ||||||||
| 531 | if (X86ScalarSSEf32) { | ||||||||
| 532 | if (IsNonTemporal && HasSSE4A) | ||||||||
| 533 | Opc = X86::MOVNTSD; | ||||||||
| 534 | else | ||||||||
| 535 | Opc = HasAVX512 ? X86::VMOVSDZmr : | ||||||||
| 536 | HasAVX ? X86::VMOVSDmr : X86::MOVSDmr; | ||||||||
| 537 | } else | ||||||||
| 538 | Opc = X86::ST_Fp64m; | ||||||||
| 539 | break; | ||||||||
| 540 | case MVT::x86mmx: | ||||||||
| 541 | Opc = (IsNonTemporal && HasSSE1) ? X86::MMX_MOVNTQmr : X86::MMX_MOVQ64mr; | ||||||||
| 542 | break; | ||||||||
| 543 | case MVT::v4f32: | ||||||||
| 544 | if (Aligned) { | ||||||||
| 545 | if (IsNonTemporal) | ||||||||
| 546 | Opc = HasVLX ? X86::VMOVNTPSZ128mr : | ||||||||
| 547 | HasAVX ? X86::VMOVNTPSmr : X86::MOVNTPSmr; | ||||||||
| 548 | else | ||||||||
| 549 | Opc = HasVLX ? X86::VMOVAPSZ128mr : | ||||||||
| 550 | HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr; | ||||||||
| 551 | } else | ||||||||
| 552 | Opc = HasVLX ? X86::VMOVUPSZ128mr : | ||||||||
| 553 | HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr; | ||||||||
| 554 | break; | ||||||||
| 555 | case MVT::v2f64: | ||||||||
| 556 | if (Aligned) { | ||||||||
| 557 | if (IsNonTemporal) | ||||||||
| 558 | Opc = HasVLX ? X86::VMOVNTPDZ128mr : | ||||||||
| 559 | HasAVX ? X86::VMOVNTPDmr : X86::MOVNTPDmr; | ||||||||
| 560 | else | ||||||||
| 561 | Opc = HasVLX ? X86::VMOVAPDZ128mr : | ||||||||
| 562 | HasAVX ? X86::VMOVAPDmr : X86::MOVAPDmr; | ||||||||
| 563 | } else | ||||||||
| 564 | Opc = HasVLX ? X86::VMOVUPDZ128mr : | ||||||||
| 565 | HasAVX ? X86::VMOVUPDmr : X86::MOVUPDmr; | ||||||||
| 566 | break; | ||||||||
| 567 | case MVT::v4i32: | ||||||||
| 568 | case MVT::v2i64: | ||||||||
| 569 | case MVT::v8i16: | ||||||||
| 570 | case MVT::v16i8: | ||||||||
| 571 | if (Aligned) { | ||||||||
| 572 | if (IsNonTemporal) | ||||||||
| 573 | Opc = HasVLX ? X86::VMOVNTDQZ128mr : | ||||||||
| 574 | HasAVX ? X86::VMOVNTDQmr : X86::MOVNTDQmr; | ||||||||
| 575 | else | ||||||||
| 576 | Opc = HasVLX ? X86::VMOVDQA64Z128mr : | ||||||||
| 577 | HasAVX ? X86::VMOVDQAmr : X86::MOVDQAmr; | ||||||||
| 578 | } else | ||||||||
| 579 | Opc = HasVLX ? X86::VMOVDQU64Z128mr : | ||||||||
| 580 | HasAVX ? X86::VMOVDQUmr : X86::MOVDQUmr; | ||||||||
| 581 | break; | ||||||||
| 582 | case MVT::v8f32: | ||||||||
| 583 | assert(HasAVX)((void)0); | ||||||||
| 584 | if (Aligned) { | ||||||||
| 585 | if (IsNonTemporal) | ||||||||
| 586 | Opc = HasVLX ? X86::VMOVNTPSZ256mr : X86::VMOVNTPSYmr; | ||||||||
| 587 | else | ||||||||
| 588 | Opc = HasVLX ? X86::VMOVAPSZ256mr : X86::VMOVAPSYmr; | ||||||||
| 589 | } else | ||||||||
| 590 | Opc = HasVLX ? X86::VMOVUPSZ256mr : X86::VMOVUPSYmr; | ||||||||
| 591 | break; | ||||||||
| 592 | case MVT::v4f64: | ||||||||
| 593 | assert(HasAVX)((void)0); | ||||||||
| 594 | if (Aligned) { | ||||||||
| 595 | if (IsNonTemporal) | ||||||||
| 596 | Opc = HasVLX ? X86::VMOVNTPDZ256mr : X86::VMOVNTPDYmr; | ||||||||
| 597 | else | ||||||||
| 598 | Opc = HasVLX ? X86::VMOVAPDZ256mr : X86::VMOVAPDYmr; | ||||||||
| 599 | } else | ||||||||
| 600 | Opc = HasVLX ? X86::VMOVUPDZ256mr : X86::VMOVUPDYmr; | ||||||||
| 601 | break; | ||||||||
| 602 | case MVT::v8i32: | ||||||||
| 603 | case MVT::v4i64: | ||||||||
| 604 | case MVT::v16i16: | ||||||||
| 605 | case MVT::v32i8: | ||||||||
| 606 | assert(HasAVX)((void)0); | ||||||||
| 607 | if (Aligned) { | ||||||||
| 608 | if (IsNonTemporal) | ||||||||
| 609 | Opc = HasVLX ? X86::VMOVNTDQZ256mr : X86::VMOVNTDQYmr; | ||||||||
| 610 | else | ||||||||
| 611 | Opc = HasVLX ? X86::VMOVDQA64Z256mr : X86::VMOVDQAYmr; | ||||||||
| 612 | } else | ||||||||
| 613 | Opc = HasVLX ? X86::VMOVDQU64Z256mr : X86::VMOVDQUYmr; | ||||||||
| 614 | break; | ||||||||
| 615 | case MVT::v16f32: | ||||||||
| 616 | assert(HasAVX512)((void)0); | ||||||||
| 617 | if (Aligned) | ||||||||
| 618 | Opc = IsNonTemporal ? X86::VMOVNTPSZmr : X86::VMOVAPSZmr; | ||||||||
| 619 | else | ||||||||
| 620 | Opc = X86::VMOVUPSZmr; | ||||||||
| 621 | break; | ||||||||
| 622 | case MVT::v8f64: | ||||||||
| 623 | assert(HasAVX512)((void)0); | ||||||||
| 624 | if (Aligned) { | ||||||||
| 625 | Opc = IsNonTemporal ? X86::VMOVNTPDZmr : X86::VMOVAPDZmr; | ||||||||
| 626 | } else | ||||||||
| 627 | Opc = X86::VMOVUPDZmr; | ||||||||
| 628 | break; | ||||||||
| 629 | case MVT::v8i64: | ||||||||
| 630 | case MVT::v16i32: | ||||||||
| 631 | case MVT::v32i16: | ||||||||
| 632 | case MVT::v64i8: | ||||||||
| 633 | assert(HasAVX512)((void)0); | ||||||||
| 634 | // Note: There are a lot more choices based on type with AVX-512, but | ||||||||
| 635 | // there's really no advantage when the store isn't masked. | ||||||||
| 636 | if (Aligned) | ||||||||
| 637 | Opc = IsNonTemporal ? X86::VMOVNTDQZmr : X86::VMOVDQA64Zmr; | ||||||||
| 638 | else | ||||||||
| 639 | Opc = X86::VMOVDQU64Zmr; | ||||||||
| 640 | break; | ||||||||
| 641 | } | ||||||||
| 642 | |||||||||
| 643 | const MCInstrDesc &Desc = TII.get(Opc); | ||||||||
| 644 | // Some of the instructions in the previous switch use FR128 instead | ||||||||
| 645 | // of FR32 for ValReg. Make sure the register we feed the instruction | ||||||||
| 646 | // matches its register class constraints. | ||||||||
| 647 | // Note: This is fine to do a copy from FR32 to FR128, this is the | ||||||||
| 648 | // same registers behind the scene and actually why it did not trigger | ||||||||
| 649 | // any bugs before. | ||||||||
| 650 | ValReg = constrainOperandRegClass(Desc, ValReg, Desc.getNumOperands() - 1); | ||||||||
| 651 | MachineInstrBuilder MIB = | ||||||||
| 652 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, Desc); | ||||||||
| 653 | addFullAddress(MIB, AM).addReg(ValReg); | ||||||||
| 654 | if (MMO) | ||||||||
| 655 | MIB->addMemOperand(*FuncInfo.MF, MMO); | ||||||||
| 656 | |||||||||
| 657 | return true; | ||||||||
| 658 | } | ||||||||
| 659 | |||||||||
| 660 | bool X86FastISel::X86FastEmitStore(EVT VT, const Value *Val, | ||||||||
| 661 | X86AddressMode &AM, | ||||||||
| 662 | MachineMemOperand *MMO, bool Aligned) { | ||||||||
| 663 | // Handle 'null' like i32/i64 0. | ||||||||
| 664 | if (isa<ConstantPointerNull>(Val)) | ||||||||
| 665 | Val = Constant::getNullValue(DL.getIntPtrType(Val->getContext())); | ||||||||
| 666 | |||||||||
| 667 | // If this is a store of a simple constant, fold the constant into the store. | ||||||||
| 668 | if (const ConstantInt *CI = dyn_cast<ConstantInt>(Val)) { | ||||||||
| 669 | unsigned Opc = 0; | ||||||||
| 670 | bool Signed = true; | ||||||||
| 671 | switch (VT.getSimpleVT().SimpleTy) { | ||||||||
| 672 | default: break; | ||||||||
| 673 | case MVT::i1: | ||||||||
| 674 | Signed = false; | ||||||||
| 675 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; // Handle as i8. | ||||||||
| 676 | case MVT::i8: Opc = X86::MOV8mi; break; | ||||||||
| 677 | case MVT::i16: Opc = X86::MOV16mi; break; | ||||||||
| 678 | case MVT::i32: Opc = X86::MOV32mi; break; | ||||||||
| 679 | case MVT::i64: | ||||||||
| 680 | // Must be a 32-bit sign extended value. | ||||||||
| 681 | if (isInt<32>(CI->getSExtValue())) | ||||||||
| 682 | Opc = X86::MOV64mi32; | ||||||||
| 683 | break; | ||||||||
| 684 | } | ||||||||
| 685 | |||||||||
| 686 | if (Opc) { | ||||||||
| 687 | MachineInstrBuilder MIB = | ||||||||
| 688 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc)); | ||||||||
| 689 | addFullAddress(MIB, AM).addImm(Signed ? (uint64_t) CI->getSExtValue() | ||||||||
| 690 | : CI->getZExtValue()); | ||||||||
| 691 | if (MMO) | ||||||||
| 692 | MIB->addMemOperand(*FuncInfo.MF, MMO); | ||||||||
| 693 | return true; | ||||||||
| 694 | } | ||||||||
| 695 | } | ||||||||
| 696 | |||||||||
| 697 | Register ValReg = getRegForValue(Val); | ||||||||
| 698 | if (ValReg == 0) | ||||||||
| 699 | return false; | ||||||||
| 700 | |||||||||
| 701 | return X86FastEmitStore(VT, ValReg, AM, MMO, Aligned); | ||||||||
| 702 | } | ||||||||
| 703 | |||||||||
| 704 | /// X86FastEmitExtend - Emit a machine instruction to extend a value Src of | ||||||||
| 705 | /// type SrcVT to type DstVT using the specified extension opcode Opc (e.g. | ||||||||
| 706 | /// ISD::SIGN_EXTEND). | ||||||||
| 707 | bool X86FastISel::X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, | ||||||||
| 708 | unsigned Src, EVT SrcVT, | ||||||||
| 709 | unsigned &ResultReg) { | ||||||||
| 710 | unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); | ||||||||
| 711 | if (RR == 0) | ||||||||
| 712 | return false; | ||||||||
| 713 | |||||||||
| 714 | ResultReg = RR; | ||||||||
| 715 | return true; | ||||||||
| 716 | } | ||||||||
| 717 | |||||||||
| 718 | bool X86FastISel::handleConstantAddresses(const Value *V, X86AddressMode &AM) { | ||||||||
| 719 | // Handle constant address. | ||||||||
| 720 | if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) { | ||||||||
| 721 | // Can't handle alternate code models yet. | ||||||||
| 722 | if (TM.getCodeModel() != CodeModel::Small) | ||||||||
| 723 | return false; | ||||||||
| 724 | |||||||||
| 725 | // Can't handle TLS yet. | ||||||||
| 726 | if (GV->isThreadLocal()) | ||||||||
| 727 | return false; | ||||||||
| 728 | |||||||||
| 729 | // Can't handle !absolute_symbol references yet. | ||||||||
| 730 | if (GV->isAbsoluteSymbolRef()) | ||||||||
| 731 | return false; | ||||||||
| 732 | |||||||||
| 733 | // RIP-relative addresses can't have additional register operands, so if | ||||||||
| 734 | // we've already folded stuff into the addressing mode, just force the | ||||||||
| 735 | // global value into its own register, which we can use as the basereg. | ||||||||
| 736 | if (!Subtarget->isPICStyleRIPRel() || | ||||||||
| 737 | (AM.Base.Reg == 0 && AM.IndexReg == 0)) { | ||||||||
| 738 | // Okay, we've committed to selecting this global. Set up the address. | ||||||||
| 739 | AM.GV = GV; | ||||||||
| 740 | |||||||||
| 741 | // Allow the subtarget to classify the global. | ||||||||
| 742 | unsigned char GVFlags = Subtarget->classifyGlobalReference(GV); | ||||||||
| 743 | |||||||||
| 744 | // If this reference is relative to the pic base, set it now. | ||||||||
| 745 | if (isGlobalRelativeToPICBase(GVFlags)) { | ||||||||
| 746 | // FIXME: How do we know Base.Reg is free?? | ||||||||
| 747 | AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF); | ||||||||
| 748 | } | ||||||||
| 749 | |||||||||
| 750 | // Unless the ABI requires an extra load, return a direct reference to | ||||||||
| 751 | // the global. | ||||||||
| 752 | if (!isGlobalStubReference(GVFlags)) { | ||||||||
| 753 | if (Subtarget->isPICStyleRIPRel()) { | ||||||||
| 754 | // Use rip-relative addressing if we can. Above we verified that the | ||||||||
| 755 | // base and index registers are unused. | ||||||||
| 756 | assert(AM.Base.Reg == 0 && AM.IndexReg == 0)((void)0); | ||||||||
| 757 | AM.Base.Reg = X86::RIP; | ||||||||
| 758 | } | ||||||||
| 759 | AM.GVOpFlags = GVFlags; | ||||||||
| 760 | return true; | ||||||||
| 761 | } | ||||||||
| 762 | |||||||||
| 763 | // Ok, we need to do a load from a stub. If we've already loaded from | ||||||||
| 764 | // this stub, reuse the loaded pointer, otherwise emit the load now. | ||||||||
| 765 | DenseMap<const Value *, Register>::iterator I = LocalValueMap.find(V); | ||||||||
| 766 | Register LoadReg; | ||||||||
| 767 | if (I != LocalValueMap.end() && I->second) { | ||||||||
| 768 | LoadReg = I->second; | ||||||||
| 769 | } else { | ||||||||
| 770 | // Issue load from stub. | ||||||||
| 771 | unsigned Opc = 0; | ||||||||
| 772 | const TargetRegisterClass *RC = nullptr; | ||||||||
| 773 | X86AddressMode StubAM; | ||||||||
| 774 | StubAM.Base.Reg = AM.Base.Reg; | ||||||||
| 775 | StubAM.GV = GV; | ||||||||
| 776 | StubAM.GVOpFlags = GVFlags; | ||||||||
| 777 | |||||||||
| 778 | // Prepare for inserting code in the local-value area. | ||||||||
| 779 | SavePoint SaveInsertPt = enterLocalValueArea(); | ||||||||
| 780 | |||||||||
| 781 | if (TLI.getPointerTy(DL) == MVT::i64) { | ||||||||
| 782 | Opc = X86::MOV64rm; | ||||||||
| 783 | RC = &X86::GR64RegClass; | ||||||||
| 784 | } else { | ||||||||
| 785 | Opc = X86::MOV32rm; | ||||||||
| 786 | RC = &X86::GR32RegClass; | ||||||||
| 787 | } | ||||||||
| 788 | |||||||||
| 789 | if (Subtarget->isPICStyleRIPRel() || GVFlags == X86II::MO_GOTPCREL) | ||||||||
| 790 | StubAM.Base.Reg = X86::RIP; | ||||||||
| 791 | |||||||||
| 792 | LoadReg = createResultReg(RC); | ||||||||
| 793 | MachineInstrBuilder LoadMI = | ||||||||
| 794 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), LoadReg); | ||||||||
| 795 | addFullAddress(LoadMI, StubAM); | ||||||||
| 796 | |||||||||
| 797 | // Ok, back to normal mode. | ||||||||
| 798 | leaveLocalValueArea(SaveInsertPt); | ||||||||
| 799 | |||||||||
| 800 | // Prevent loading GV stub multiple times in same MBB. | ||||||||
| 801 | LocalValueMap[V] = LoadReg; | ||||||||
| 802 | } | ||||||||
| 803 | |||||||||
| 804 | // Now construct the final address. Note that the Disp, Scale, | ||||||||
| 805 | // and Index values may already be set here. | ||||||||
| 806 | AM.Base.Reg = LoadReg; | ||||||||
| 807 | AM.GV = nullptr; | ||||||||
| 808 | return true; | ||||||||
| 809 | } | ||||||||
| 810 | } | ||||||||
| 811 | |||||||||
| 812 | // If all else fails, try to materialize the value in a register. | ||||||||
| 813 | if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { | ||||||||
| 814 | if (AM.Base.Reg == 0) { | ||||||||
| 815 | AM.Base.Reg = getRegForValue(V); | ||||||||
| 816 | return AM.Base.Reg != 0; | ||||||||
| 817 | } | ||||||||
| 818 | if (AM.IndexReg == 0) { | ||||||||
| 819 | assert(AM.Scale == 1 && "Scale with no index!")((void)0); | ||||||||
| 820 | AM.IndexReg = getRegForValue(V); | ||||||||
| 821 | return AM.IndexReg != 0; | ||||||||
| 822 | } | ||||||||
| 823 | } | ||||||||
| 824 | |||||||||
| 825 | return false; | ||||||||
| 826 | } | ||||||||
| 827 | |||||||||
| 828 | /// X86SelectAddress - Attempt to fill in an address from the given value. | ||||||||
| 829 | /// | ||||||||
| 830 | bool X86FastISel::X86SelectAddress(const Value *V, X86AddressMode &AM) { | ||||||||
| 831 | SmallVector<const Value *, 32> GEPs; | ||||||||
| 832 | redo_gep: | ||||||||
| 833 | const User *U = nullptr; | ||||||||
| 834 | unsigned Opcode = Instruction::UserOp1; | ||||||||
| 835 | if (const Instruction *I = dyn_cast<Instruction>(V)) { | ||||||||
| 836 | // Don't walk into other basic blocks; it's possible we haven't | ||||||||
| 837 | // visited them yet, so the instructions may not yet be assigned | ||||||||
| 838 | // virtual registers. | ||||||||
| 839 | if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(V)) || | ||||||||
| 840 | FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { | ||||||||
| 841 | Opcode = I->getOpcode(); | ||||||||
| 842 | U = I; | ||||||||
| 843 | } | ||||||||
| 844 | } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { | ||||||||
| 845 | Opcode = C->getOpcode(); | ||||||||
| 846 | U = C; | ||||||||
| 847 | } | ||||||||
| 848 | |||||||||
| 849 | if (PointerType *Ty = dyn_cast<PointerType>(V->getType())) | ||||||||
| 850 | if (Ty->getAddressSpace() > 255) | ||||||||
| 851 | // Fast instruction selection doesn't support the special | ||||||||
| 852 | // address spaces. | ||||||||
| 853 | return false; | ||||||||
| 854 | |||||||||
| 855 | switch (Opcode) { | ||||||||
| 856 | default: break; | ||||||||
| 857 | case Instruction::BitCast: | ||||||||
| 858 | // Look past bitcasts. | ||||||||
| 859 | return X86SelectAddress(U->getOperand(0), AM); | ||||||||
| 860 | |||||||||
| 861 | case Instruction::IntToPtr: | ||||||||
| 862 | // Look past no-op inttoptrs. | ||||||||
| 863 | if (TLI.getValueType(DL, U->getOperand(0)->getType()) == | ||||||||
| 864 | TLI.getPointerTy(DL)) | ||||||||
| 865 | return X86SelectAddress(U->getOperand(0), AM); | ||||||||
| 866 | break; | ||||||||
| 867 | |||||||||
| 868 | case Instruction::PtrToInt: | ||||||||
| 869 | // Look past no-op ptrtoints. | ||||||||
| 870 | if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL)) | ||||||||
| 871 | return X86SelectAddress(U->getOperand(0), AM); | ||||||||
| 872 | break; | ||||||||
| 873 | |||||||||
| 874 | case Instruction::Alloca: { | ||||||||
| 875 | // Do static allocas. | ||||||||
| 876 | const AllocaInst *A = cast<AllocaInst>(V); | ||||||||
| 877 | DenseMap<const AllocaInst *, int>::iterator SI = | ||||||||
| 878 | FuncInfo.StaticAllocaMap.find(A); | ||||||||
| 879 | if (SI != FuncInfo.StaticAllocaMap.end()) { | ||||||||
| 880 | AM.BaseType = X86AddressMode::FrameIndexBase; | ||||||||
| 881 | AM.Base.FrameIndex = SI->second; | ||||||||
| 882 | return true; | ||||||||
| 883 | } | ||||||||
| 884 | break; | ||||||||
| 885 | } | ||||||||
| 886 | |||||||||
| 887 | case Instruction::Add: { | ||||||||
| 888 | // Adds of constants are common and easy enough. | ||||||||
| 889 | if (const ConstantInt *CI = dyn_cast<ConstantInt>(U->getOperand(1))) { | ||||||||
| 890 | uint64_t Disp = (int32_t)AM.Disp + (uint64_t)CI->getSExtValue(); | ||||||||
| 891 | // They have to fit in the 32-bit signed displacement field though. | ||||||||
| 892 | if (isInt<32>(Disp)) { | ||||||||
| 893 | AM.Disp = (uint32_t)Disp; | ||||||||
| 894 | return X86SelectAddress(U->getOperand(0), AM); | ||||||||
| 895 | } | ||||||||
| 896 | } | ||||||||
| 897 | break; | ||||||||
| 898 | } | ||||||||
| 899 | |||||||||
| 900 | case Instruction::GetElementPtr: { | ||||||||
| 901 | X86AddressMode SavedAM = AM; | ||||||||
| 902 | |||||||||
| 903 | // Pattern-match simple GEPs. | ||||||||
| 904 | uint64_t Disp = (int32_t)AM.Disp; | ||||||||
| 905 | unsigned IndexReg = AM.IndexReg; | ||||||||
| 906 | unsigned Scale = AM.Scale; | ||||||||
| 907 | gep_type_iterator GTI = gep_type_begin(U); | ||||||||
| 908 | // Iterate through the indices, folding what we can. Constants can be | ||||||||
| 909 | // folded, and one dynamic index can be handled, if the scale is supported. | ||||||||
| 910 | for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); | ||||||||
| 911 | i != e; ++i, ++GTI) { | ||||||||
| 912 | const Value *Op = *i; | ||||||||
| 913 | if (StructType *STy = GTI.getStructTypeOrNull()) { | ||||||||
| 914 | const StructLayout *SL = DL.getStructLayout(STy); | ||||||||
| 915 | Disp += SL->getElementOffset(cast<ConstantInt>(Op)->getZExtValue()); | ||||||||
| 916 | continue; | ||||||||
| 917 | } | ||||||||
| 918 | |||||||||
| 919 | // A array/variable index is always of the form i*S where S is the | ||||||||
| 920 | // constant scale size. See if we can push the scale into immediates. | ||||||||
| 921 | uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType()); | ||||||||
| 922 | for (;;) { | ||||||||
| 923 | if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { | ||||||||
| 924 | // Constant-offset addressing. | ||||||||
| 925 | Disp += CI->getSExtValue() * S; | ||||||||
| 926 | break; | ||||||||
| 927 | } | ||||||||
| 928 | if (canFoldAddIntoGEP(U, Op)) { | ||||||||
| 929 | // A compatible add with a constant operand. Fold the constant. | ||||||||
| 930 | ConstantInt *CI = | ||||||||
| 931 | cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1)); | ||||||||
| 932 | Disp += CI->getSExtValue() * S; | ||||||||
| 933 | // Iterate on the other operand. | ||||||||
| 934 | Op = cast<AddOperator>(Op)->getOperand(0); | ||||||||
| 935 | continue; | ||||||||
| 936 | } | ||||||||
| 937 | if (IndexReg == 0 && | ||||||||
| 938 | (!AM.GV || !Subtarget->isPICStyleRIPRel()) && | ||||||||
| 939 | (S == 1 || S == 2 || S == 4 || S == 8)) { | ||||||||
| 940 | // Scaled-index addressing. | ||||||||
| 941 | Scale = S; | ||||||||
| 942 | IndexReg = getRegForGEPIndex(Op); | ||||||||
| 943 | if (IndexReg == 0) | ||||||||
| 944 | return false; | ||||||||
| 945 | break; | ||||||||
| 946 | } | ||||||||
| 947 | // Unsupported. | ||||||||
| 948 | goto unsupported_gep; | ||||||||
| 949 | } | ||||||||
| 950 | } | ||||||||
| 951 | |||||||||
| 952 | // Check for displacement overflow. | ||||||||
| 953 | if (!isInt<32>(Disp)) | ||||||||
| 954 | break; | ||||||||
| 955 | |||||||||
| 956 | AM.IndexReg = IndexReg; | ||||||||
| 957 | AM.Scale = Scale; | ||||||||
| 958 | AM.Disp = (uint32_t)Disp; | ||||||||
| 959 | GEPs.push_back(V); | ||||||||
| 960 | |||||||||
| 961 | if (const GetElementPtrInst *GEP = | ||||||||
| 962 | dyn_cast<GetElementPtrInst>(U->getOperand(0))) { | ||||||||
| 963 | // Ok, the GEP indices were covered by constant-offset and scaled-index | ||||||||
| 964 | // addressing. Update the address state and move on to examining the base. | ||||||||
| 965 | V = GEP; | ||||||||
| 966 | goto redo_gep; | ||||||||
| 967 | } else if (X86SelectAddress(U->getOperand(0), AM)) { | ||||||||
| 968 | return true; | ||||||||
| 969 | } | ||||||||
| 970 | |||||||||
| 971 | // If we couldn't merge the gep value into this addr mode, revert back to | ||||||||
| 972 | // our address and just match the value instead of completely failing. | ||||||||
| 973 | AM = SavedAM; | ||||||||
| 974 | |||||||||
| 975 | for (const Value *I : reverse(GEPs)) | ||||||||
| 976 | if (handleConstantAddresses(I, AM)) | ||||||||
| 977 | return true; | ||||||||
| 978 | |||||||||
| 979 | return false; | ||||||||
| 980 | unsupported_gep: | ||||||||
| 981 | // Ok, the GEP indices weren't all covered. | ||||||||
| 982 | break; | ||||||||
| 983 | } | ||||||||
| 984 | } | ||||||||
| 985 | |||||||||
| 986 | return handleConstantAddresses(V, AM); | ||||||||
| 987 | } | ||||||||
| 988 | |||||||||
| 989 | /// X86SelectCallAddress - Attempt to fill in an address from the given value. | ||||||||
| 990 | /// | ||||||||
| 991 | bool X86FastISel::X86SelectCallAddress(const Value *V, X86AddressMode &AM) { | ||||||||
| 992 | const User *U = nullptr; | ||||||||
| 993 | unsigned Opcode = Instruction::UserOp1; | ||||||||
| 994 | const Instruction *I = dyn_cast<Instruction>(V); | ||||||||
| 995 | // Record if the value is defined in the same basic block. | ||||||||
| 996 | // | ||||||||
| 997 | // This information is crucial to know whether or not folding an | ||||||||
| 998 | // operand is valid. | ||||||||
| 999 | // Indeed, FastISel generates or reuses a virtual register for all | ||||||||
| 1000 | // operands of all instructions it selects. Obviously, the definition and | ||||||||
| 1001 | // its uses must use the same virtual register otherwise the produced | ||||||||
| 1002 | // code is incorrect. | ||||||||
| 1003 | // Before instruction selection, FunctionLoweringInfo::set sets the virtual | ||||||||
| 1004 | // registers for values that are alive across basic blocks. This ensures | ||||||||
| 1005 | // that the values are consistently set between across basic block, even | ||||||||
| 1006 | // if different instruction selection mechanisms are used (e.g., a mix of | ||||||||
| 1007 | // SDISel and FastISel). | ||||||||
| 1008 | // For values local to a basic block, the instruction selection process | ||||||||
| 1009 | // generates these virtual registers with whatever method is appropriate | ||||||||
| 1010 | // for its needs. In particular, FastISel and SDISel do not share the way | ||||||||
| 1011 | // local virtual registers are set. | ||||||||
| 1012 | // Therefore, this is impossible (or at least unsafe) to share values | ||||||||
| 1013 | // between basic blocks unless they use the same instruction selection | ||||||||
| 1014 | // method, which is not guarantee for X86. | ||||||||
| 1015 | // Moreover, things like hasOneUse could not be used accurately, if we | ||||||||
| 1016 | // allow to reference values across basic blocks whereas they are not | ||||||||
| 1017 | // alive across basic blocks initially. | ||||||||
| 1018 | bool InMBB = true; | ||||||||
| 1019 | if (I) { | ||||||||
| 1020 | Opcode = I->getOpcode(); | ||||||||
| 1021 | U = I; | ||||||||
| 1022 | InMBB = I->getParent() == FuncInfo.MBB->getBasicBlock(); | ||||||||
| 1023 | } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(V)) { | ||||||||
| 1024 | Opcode = C->getOpcode(); | ||||||||
| 1025 | U = C; | ||||||||
| 1026 | } | ||||||||
| 1027 | |||||||||
| 1028 | switch (Opcode) { | ||||||||
| 1029 | default: break; | ||||||||
| 1030 | case Instruction::BitCast: | ||||||||
| 1031 | // Look past bitcasts if its operand is in the same BB. | ||||||||
| 1032 | if (InMBB) | ||||||||
| 1033 | return X86SelectCallAddress(U->getOperand(0), AM); | ||||||||
| 1034 | break; | ||||||||
| 1035 | |||||||||
| 1036 | case Instruction::IntToPtr: | ||||||||
| 1037 | // Look past no-op inttoptrs if its operand is in the same BB. | ||||||||
| 1038 | if (InMBB && | ||||||||
| 1039 | TLI.getValueType(DL, U->getOperand(0)->getType()) == | ||||||||
| 1040 | TLI.getPointerTy(DL)) | ||||||||
| 1041 | return X86SelectCallAddress(U->getOperand(0), AM); | ||||||||
| 1042 | break; | ||||||||
| 1043 | |||||||||
| 1044 | case Instruction::PtrToInt: | ||||||||
| 1045 | // Look past no-op ptrtoints if its operand is in the same BB. | ||||||||
| 1046 | if (InMBB && TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL)) | ||||||||
| 1047 | return X86SelectCallAddress(U->getOperand(0), AM); | ||||||||
| 1048 | break; | ||||||||
| 1049 | } | ||||||||
| 1050 | |||||||||
| 1051 | // Handle constant address. | ||||||||
| 1052 | if (const GlobalValue *GV = dyn_cast<GlobalValue>(V)) { | ||||||||
| 1053 | // Can't handle alternate code models yet. | ||||||||
| 1054 | if (TM.getCodeModel() != CodeModel::Small) | ||||||||
| 1055 | return false; | ||||||||
| 1056 | |||||||||
| 1057 | // RIP-relative addresses can't have additional register operands. | ||||||||
| 1058 | if (Subtarget->isPICStyleRIPRel() && | ||||||||
| 1059 | (AM.Base.Reg != 0 || AM.IndexReg != 0)) | ||||||||
| 1060 | return false; | ||||||||
| 1061 | |||||||||
| 1062 | // Can't handle TLS. | ||||||||
| 1063 | if (const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV)) | ||||||||
| 1064 | if (GVar->isThreadLocal()) | ||||||||
| 1065 | return false; | ||||||||
| 1066 | |||||||||
| 1067 | // Okay, we've committed to selecting this global. Set up the basic address. | ||||||||
| 1068 | AM.GV = GV; | ||||||||
| 1069 | |||||||||
| 1070 | // Return a direct reference to the global. Fastisel can handle calls to | ||||||||
| 1071 | // functions that require loads, such as dllimport and nonlazybind | ||||||||
| 1072 | // functions. | ||||||||
| 1073 | if (Subtarget->isPICStyleRIPRel()) { | ||||||||
| 1074 | // Use rip-relative addressing if we can. Above we verified that the | ||||||||
| 1075 | // base and index registers are unused. | ||||||||
| 1076 | assert(AM.Base.Reg == 0 && AM.IndexReg == 0)((void)0); | ||||||||
| 1077 | AM.Base.Reg = X86::RIP; | ||||||||
| 1078 | } else { | ||||||||
| 1079 | AM.GVOpFlags = Subtarget->classifyLocalReference(nullptr); | ||||||||
| 1080 | } | ||||||||
| 1081 | |||||||||
| 1082 | return true; | ||||||||
| 1083 | } | ||||||||
| 1084 | |||||||||
| 1085 | // If all else fails, try to materialize the value in a register. | ||||||||
| 1086 | if (!AM.GV || !Subtarget->isPICStyleRIPRel()) { | ||||||||
| 1087 | auto GetCallRegForValue = [this](const Value *V) { | ||||||||
| 1088 | Register Reg = getRegForValue(V); | ||||||||
| 1089 | |||||||||
| 1090 | // In 64-bit mode, we need a 64-bit register even if pointers are 32 bits. | ||||||||
| 1091 | if (Reg && Subtarget->isTarget64BitILP32()) { | ||||||||
| 1092 | Register CopyReg = createResultReg(&X86::GR32RegClass); | ||||||||
| 1093 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV32rr), | ||||||||
| 1094 | CopyReg) | ||||||||
| 1095 | .addReg(Reg); | ||||||||
| 1096 | |||||||||
| 1097 | Register ExtReg = createResultReg(&X86::GR64RegClass); | ||||||||
| 1098 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1099 | TII.get(TargetOpcode::SUBREG_TO_REG), ExtReg) | ||||||||
| 1100 | .addImm(0) | ||||||||
| 1101 | .addReg(CopyReg) | ||||||||
| 1102 | .addImm(X86::sub_32bit); | ||||||||
| 1103 | Reg = ExtReg; | ||||||||
| 1104 | } | ||||||||
| 1105 | |||||||||
| 1106 | return Reg; | ||||||||
| 1107 | }; | ||||||||
| 1108 | |||||||||
| 1109 | if (AM.Base.Reg == 0) { | ||||||||
| 1110 | AM.Base.Reg = GetCallRegForValue(V); | ||||||||
| 1111 | return AM.Base.Reg != 0; | ||||||||
| 1112 | } | ||||||||
| 1113 | if (AM.IndexReg == 0) { | ||||||||
| 1114 | assert(AM.Scale == 1 && "Scale with no index!")((void)0); | ||||||||
| 1115 | AM.IndexReg = GetCallRegForValue(V); | ||||||||
| 1116 | return AM.IndexReg != 0; | ||||||||
| 1117 | } | ||||||||
| 1118 | } | ||||||||
| 1119 | |||||||||
| 1120 | return false; | ||||||||
| 1121 | } | ||||||||
| 1122 | |||||||||
| 1123 | |||||||||
| 1124 | /// X86SelectStore - Select and emit code to implement store instructions. | ||||||||
| 1125 | bool X86FastISel::X86SelectStore(const Instruction *I) { | ||||||||
| 1126 | // Atomic stores need special handling. | ||||||||
| 1127 | const StoreInst *S = cast<StoreInst>(I); | ||||||||
| 1128 | |||||||||
| 1129 | if (S->isAtomic()) | ||||||||
| 1130 | return false; | ||||||||
| 1131 | |||||||||
| 1132 | const Value *PtrV = I->getOperand(1); | ||||||||
| 1133 | if (TLI.supportSwiftError()) { | ||||||||
| 1134 | // Swifterror values can come from either a function parameter with | ||||||||
| 1135 | // swifterror attribute or an alloca with swifterror attribute. | ||||||||
| 1136 | if (const Argument *Arg = dyn_cast<Argument>(PtrV)) { | ||||||||
| 1137 | if (Arg->hasSwiftErrorAttr()) | ||||||||
| 1138 | return false; | ||||||||
| 1139 | } | ||||||||
| 1140 | |||||||||
| 1141 | if (const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) { | ||||||||
| 1142 | if (Alloca->isSwiftError()) | ||||||||
| 1143 | return false; | ||||||||
| 1144 | } | ||||||||
| 1145 | } | ||||||||
| 1146 | |||||||||
| 1147 | const Value *Val = S->getValueOperand(); | ||||||||
| 1148 | const Value *Ptr = S->getPointerOperand(); | ||||||||
| 1149 | |||||||||
| 1150 | MVT VT; | ||||||||
| 1151 | if (!isTypeLegal(Val->getType(), VT, /*AllowI1=*/true)) | ||||||||
| 1152 | return false; | ||||||||
| 1153 | |||||||||
| 1154 | Align Alignment = S->getAlign(); | ||||||||
| 1155 | Align ABIAlignment = DL.getABITypeAlign(Val->getType()); | ||||||||
| 1156 | bool Aligned = Alignment >= ABIAlignment; | ||||||||
| 1157 | |||||||||
| 1158 | X86AddressMode AM; | ||||||||
| 1159 | if (!X86SelectAddress(Ptr, AM)) | ||||||||
| 1160 | return false; | ||||||||
| 1161 | |||||||||
| 1162 | return X86FastEmitStore(VT, Val, AM, createMachineMemOperandFor(I), Aligned); | ||||||||
| 1163 | } | ||||||||
| 1164 | |||||||||
| 1165 | /// X86SelectRet - Select and emit code to implement ret instructions. | ||||||||
| 1166 | bool X86FastISel::X86SelectRet(const Instruction *I) { | ||||||||
| 1167 | const ReturnInst *Ret = cast<ReturnInst>(I); | ||||||||
| 1168 | const Function &F = *I->getParent()->getParent(); | ||||||||
| 1169 | const X86MachineFunctionInfo *X86MFInfo = | ||||||||
| 1170 | FuncInfo.MF->getInfo<X86MachineFunctionInfo>(); | ||||||||
| 1171 | |||||||||
| 1172 | if (!FuncInfo.CanLowerReturn) | ||||||||
| 1173 | return false; | ||||||||
| 1174 | |||||||||
| 1175 | if (TLI.supportSwiftError() && | ||||||||
| 1176 | F.getAttributes().hasAttrSomewhere(Attribute::SwiftError)) | ||||||||
| 1177 | return false; | ||||||||
| 1178 | |||||||||
| 1179 | if (TLI.supportSplitCSR(FuncInfo.MF)) | ||||||||
| 1180 | return false; | ||||||||
| 1181 | |||||||||
| 1182 | CallingConv::ID CC = F.getCallingConv(); | ||||||||
| 1183 | if (CC != CallingConv::C && | ||||||||
| 1184 | CC != CallingConv::Fast && | ||||||||
| 1185 | CC != CallingConv::Tail && | ||||||||
| 1186 | CC != CallingConv::SwiftTail && | ||||||||
| 1187 | CC != CallingConv::X86_FastCall && | ||||||||
| 1188 | CC != CallingConv::X86_StdCall && | ||||||||
| 1189 | CC != CallingConv::X86_ThisCall && | ||||||||
| 1190 | CC != CallingConv::X86_64_SysV && | ||||||||
| 1191 | CC != CallingConv::Win64) | ||||||||
| 1192 | return false; | ||||||||
| 1193 | |||||||||
| 1194 | // Don't handle popping bytes if they don't fit the ret's immediate. | ||||||||
| 1195 | if (!isUInt<16>(X86MFInfo->getBytesToPopOnReturn())) | ||||||||
| 1196 | return false; | ||||||||
| 1197 | |||||||||
| 1198 | // fastcc with -tailcallopt is intended to provide a guaranteed | ||||||||
| 1199 | // tail call optimization. Fastisel doesn't know how to do that. | ||||||||
| 1200 | if ((CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt) || | ||||||||
| 1201 | CC == CallingConv::Tail || CC == CallingConv::SwiftTail) | ||||||||
| 1202 | return false; | ||||||||
| 1203 | |||||||||
| 1204 | // Let SDISel handle vararg functions. | ||||||||
| 1205 | if (F.isVarArg()) | ||||||||
| 1206 | return false; | ||||||||
| 1207 | |||||||||
| 1208 | // Build a list of return value registers. | ||||||||
| 1209 | SmallVector<unsigned, 4> RetRegs; | ||||||||
| 1210 | |||||||||
| 1211 | if (Ret->getNumOperands() > 0) { | ||||||||
| 1212 | SmallVector<ISD::OutputArg, 4> Outs; | ||||||||
| 1213 | GetReturnInfo(CC, F.getReturnType(), F.getAttributes(), Outs, TLI, DL); | ||||||||
| 1214 | |||||||||
| 1215 | // Analyze operands of the call, assigning locations to each operand. | ||||||||
| 1216 | SmallVector<CCValAssign, 16> ValLocs; | ||||||||
| 1217 | CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, I->getContext()); | ||||||||
| 1218 | CCInfo.AnalyzeReturn(Outs, RetCC_X86); | ||||||||
| 1219 | |||||||||
| 1220 | const Value *RV = Ret->getOperand(0); | ||||||||
| 1221 | Register Reg = getRegForValue(RV); | ||||||||
| 1222 | if (Reg == 0) | ||||||||
| 1223 | return false; | ||||||||
| 1224 | |||||||||
| 1225 | // Only handle a single return value for now. | ||||||||
| 1226 | if (ValLocs.size() != 1) | ||||||||
| 1227 | return false; | ||||||||
| 1228 | |||||||||
| 1229 | CCValAssign &VA = ValLocs[0]; | ||||||||
| 1230 | |||||||||
| 1231 | // Don't bother handling odd stuff for now. | ||||||||
| 1232 | if (VA.getLocInfo() != CCValAssign::Full) | ||||||||
| 1233 | return false; | ||||||||
| 1234 | // Only handle register returns for now. | ||||||||
| 1235 | if (!VA.isRegLoc()) | ||||||||
| 1236 | return false; | ||||||||
| 1237 | |||||||||
| 1238 | // The calling-convention tables for x87 returns don't tell | ||||||||
| 1239 | // the whole story. | ||||||||
| 1240 | if (VA.getLocReg() == X86::FP0 || VA.getLocReg() == X86::FP1) | ||||||||
| 1241 | return false; | ||||||||
| 1242 | |||||||||
| 1243 | unsigned SrcReg = Reg + VA.getValNo(); | ||||||||
| 1244 | EVT SrcVT = TLI.getValueType(DL, RV->getType()); | ||||||||
| 1245 | EVT DstVT = VA.getValVT(); | ||||||||
| 1246 | // Special handling for extended integers. | ||||||||
| 1247 | if (SrcVT != DstVT) { | ||||||||
| 1248 | if (SrcVT != MVT::i1 && SrcVT != MVT::i8 && SrcVT != MVT::i16) | ||||||||
| 1249 | return false; | ||||||||
| 1250 | |||||||||
| 1251 | if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) | ||||||||
| 1252 | return false; | ||||||||
| 1253 | |||||||||
| 1254 | assert(DstVT == MVT::i32 && "X86 should always ext to i32")((void)0); | ||||||||
| 1255 | |||||||||
| 1256 | if (SrcVT == MVT::i1) { | ||||||||
| 1257 | if (Outs[0].Flags.isSExt()) | ||||||||
| 1258 | return false; | ||||||||
| 1259 | // TODO | ||||||||
| 1260 | SrcReg = fastEmitZExtFromI1(MVT::i8, SrcReg); | ||||||||
| 1261 | SrcVT = MVT::i8; | ||||||||
| 1262 | } | ||||||||
| 1263 | unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : | ||||||||
| 1264 | ISD::SIGN_EXTEND; | ||||||||
| 1265 | // TODO | ||||||||
| 1266 | SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); | ||||||||
| 1267 | } | ||||||||
| 1268 | |||||||||
| 1269 | // Make the copy. | ||||||||
| 1270 | Register DstReg = VA.getLocReg(); | ||||||||
| 1271 | const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); | ||||||||
| 1272 | // Avoid a cross-class copy. This is very unlikely. | ||||||||
| 1273 | if (!SrcRC->contains(DstReg)) | ||||||||
| 1274 | return false; | ||||||||
| 1275 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1276 | TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg); | ||||||||
| 1277 | |||||||||
| 1278 | // Add register to return instruction. | ||||||||
| 1279 | RetRegs.push_back(VA.getLocReg()); | ||||||||
| 1280 | } | ||||||||
| 1281 | |||||||||
| 1282 | // Swift calling convention does not require we copy the sret argument | ||||||||
| 1283 | // into %rax/%eax for the return, and SRetReturnReg is not set for Swift. | ||||||||
| 1284 | |||||||||
| 1285 | // All x86 ABIs require that for returning structs by value we copy | ||||||||
| 1286 | // the sret argument into %rax/%eax (depending on ABI) for the return. | ||||||||
| 1287 | // We saved the argument into a virtual register in the entry block, | ||||||||
| 1288 | // so now we copy the value out and into %rax/%eax. | ||||||||
| 1289 | if (F.hasStructRetAttr() && CC != CallingConv::Swift && | ||||||||
| 1290 | CC != CallingConv::SwiftTail) { | ||||||||
| 1291 | Register Reg = X86MFInfo->getSRetReturnReg(); | ||||||||
| 1292 | assert(Reg &&((void)0) | ||||||||
| 1293 | "SRetReturnReg should have been set in LowerFormalArguments()!")((void)0); | ||||||||
| 1294 | unsigned RetReg = Subtarget->isTarget64BitLP64() ? X86::RAX : X86::EAX; | ||||||||
| 1295 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1296 | TII.get(TargetOpcode::COPY), RetReg).addReg(Reg); | ||||||||
| 1297 | RetRegs.push_back(RetReg); | ||||||||
| 1298 | } | ||||||||
| 1299 | |||||||||
| 1300 | // Now emit the RET. | ||||||||
| 1301 | MachineInstrBuilder MIB; | ||||||||
| 1302 | if (X86MFInfo->getBytesToPopOnReturn()) { | ||||||||
| 1303 | MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1304 | TII.get(Subtarget->is64Bit() ? X86::RETIQ : X86::RETIL)) | ||||||||
| 1305 | .addImm(X86MFInfo->getBytesToPopOnReturn()); | ||||||||
| 1306 | } else { | ||||||||
| 1307 | MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1308 | TII.get(Subtarget->is64Bit() ? X86::RETQ : X86::RETL)); | ||||||||
| 1309 | } | ||||||||
| 1310 | for (unsigned i = 0, e = RetRegs.size(); i != e; ++i) | ||||||||
| 1311 | MIB.addReg(RetRegs[i], RegState::Implicit); | ||||||||
| 1312 | return true; | ||||||||
| 1313 | } | ||||||||
| 1314 | |||||||||
| 1315 | /// X86SelectLoad - Select and emit code to implement load instructions. | ||||||||
| 1316 | /// | ||||||||
| 1317 | bool X86FastISel::X86SelectLoad(const Instruction *I) { | ||||||||
| 1318 | const LoadInst *LI = cast<LoadInst>(I); | ||||||||
| 1319 | |||||||||
| 1320 | // Atomic loads need special handling. | ||||||||
| 1321 | if (LI->isAtomic()) | ||||||||
| 1322 | return false; | ||||||||
| 1323 | |||||||||
| 1324 | const Value *SV = I->getOperand(0); | ||||||||
| 1325 | if (TLI.supportSwiftError()) { | ||||||||
| 1326 | // Swifterror values can come from either a function parameter with | ||||||||
| 1327 | // swifterror attribute or an alloca with swifterror attribute. | ||||||||
| 1328 | if (const Argument *Arg
| ||||||||
| 1329 | if (Arg->hasSwiftErrorAttr()) | ||||||||
| 1330 | return false; | ||||||||
| 1331 | } | ||||||||
| 1332 | |||||||||
| 1333 | if (const AllocaInst *Alloca
| ||||||||
| 1334 | if (Alloca->isSwiftError()) | ||||||||
| 1335 | return false; | ||||||||
| 1336 | } | ||||||||
| 1337 | } | ||||||||
| 1338 | |||||||||
| 1339 | MVT VT; | ||||||||
| 1340 | if (!isTypeLegal(LI->getType(), VT, /*AllowI1=*/true)) | ||||||||
| 1341 | return false; | ||||||||
| 1342 | |||||||||
| 1343 | const Value *Ptr = LI->getPointerOperand(); | ||||||||
| 1344 | |||||||||
| 1345 | X86AddressMode AM; | ||||||||
| 1346 | if (!X86SelectAddress(Ptr, AM)) | ||||||||
| 1347 | return false; | ||||||||
| 1348 | |||||||||
| 1349 | unsigned ResultReg = 0; | ||||||||
| 1350 | if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg, | ||||||||
| 1351 | LI->getAlign().value())) | ||||||||
| 1352 | return false; | ||||||||
| 1353 | |||||||||
| 1354 | updateValueMap(I, ResultReg); | ||||||||
| 1355 | return true; | ||||||||
| 1356 | } | ||||||||
| 1357 | |||||||||
| 1358 | static unsigned X86ChooseCmpOpcode(EVT VT, const X86Subtarget *Subtarget) { | ||||||||
| 1359 | bool HasAVX512 = Subtarget->hasAVX512(); | ||||||||
| 1360 | bool HasAVX = Subtarget->hasAVX(); | ||||||||
| 1361 | bool X86ScalarSSEf32 = Subtarget->hasSSE1(); | ||||||||
| 1362 | bool X86ScalarSSEf64 = Subtarget->hasSSE2(); | ||||||||
| 1363 | |||||||||
| 1364 | switch (VT.getSimpleVT().SimpleTy) { | ||||||||
| 1365 | default: return 0; | ||||||||
| 1366 | case MVT::i8: return X86::CMP8rr; | ||||||||
| 1367 | case MVT::i16: return X86::CMP16rr; | ||||||||
| 1368 | case MVT::i32: return X86::CMP32rr; | ||||||||
| 1369 | case MVT::i64: return X86::CMP64rr; | ||||||||
| 1370 | case MVT::f32: | ||||||||
| 1371 | return X86ScalarSSEf32 | ||||||||
| 1372 | ? (HasAVX512 ? X86::VUCOMISSZrr | ||||||||
| 1373 | : HasAVX ? X86::VUCOMISSrr : X86::UCOMISSrr) | ||||||||
| 1374 | : 0; | ||||||||
| 1375 | case MVT::f64: | ||||||||
| 1376 | return X86ScalarSSEf64 | ||||||||
| 1377 | ? (HasAVX512 ? X86::VUCOMISDZrr | ||||||||
| 1378 | : HasAVX ? X86::VUCOMISDrr : X86::UCOMISDrr) | ||||||||
| 1379 | : 0; | ||||||||
| 1380 | } | ||||||||
| 1381 | } | ||||||||
| 1382 | |||||||||
| 1383 | /// If we have a comparison with RHS as the RHS of the comparison, return an | ||||||||
| 1384 | /// opcode that works for the compare (e.g. CMP32ri) otherwise return 0. | ||||||||
| 1385 | static unsigned X86ChooseCmpImmediateOpcode(EVT VT, const ConstantInt *RHSC) { | ||||||||
| 1386 | int64_t Val = RHSC->getSExtValue(); | ||||||||
| 1387 | switch (VT.getSimpleVT().SimpleTy) { | ||||||||
| 1388 | // Otherwise, we can't fold the immediate into this comparison. | ||||||||
| 1389 | default: | ||||||||
| 1390 | return 0; | ||||||||
| 1391 | case MVT::i8: | ||||||||
| 1392 | return X86::CMP8ri; | ||||||||
| 1393 | case MVT::i16: | ||||||||
| 1394 | if (isInt<8>(Val)) | ||||||||
| 1395 | return X86::CMP16ri8; | ||||||||
| 1396 | return X86::CMP16ri; | ||||||||
| 1397 | case MVT::i32: | ||||||||
| 1398 | if (isInt<8>(Val)) | ||||||||
| 1399 | return X86::CMP32ri8; | ||||||||
| 1400 | return X86::CMP32ri; | ||||||||
| 1401 | case MVT::i64: | ||||||||
| 1402 | if (isInt<8>(Val)) | ||||||||
| 1403 | return X86::CMP64ri8; | ||||||||
| 1404 | // 64-bit comparisons are only valid if the immediate fits in a 32-bit sext | ||||||||
| 1405 | // field. | ||||||||
| 1406 | if (isInt<32>(Val)) | ||||||||
| 1407 | return X86::CMP64ri32; | ||||||||
| 1408 | return 0; | ||||||||
| 1409 | } | ||||||||
| 1410 | } | ||||||||
| 1411 | |||||||||
| 1412 | bool X86FastISel::X86FastEmitCompare(const Value *Op0, const Value *Op1, EVT VT, | ||||||||
| 1413 | const DebugLoc &CurDbgLoc) { | ||||||||
| 1414 | Register Op0Reg = getRegForValue(Op0); | ||||||||
| 1415 | if (Op0Reg == 0) return false; | ||||||||
| 1416 | |||||||||
| 1417 | // Handle 'null' like i32/i64 0. | ||||||||
| 1418 | if (isa<ConstantPointerNull>(Op1)) | ||||||||
| 1419 | Op1 = Constant::getNullValue(DL.getIntPtrType(Op0->getContext())); | ||||||||
| 1420 | |||||||||
| 1421 | // We have two options: compare with register or immediate. If the RHS of | ||||||||
| 1422 | // the compare is an immediate that we can fold into this compare, use | ||||||||
| 1423 | // CMPri, otherwise use CMPrr. | ||||||||
| 1424 | if (const ConstantInt *Op1C = dyn_cast<ConstantInt>(Op1)) { | ||||||||
| 1425 | if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) { | ||||||||
| 1426 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDbgLoc, TII.get(CompareImmOpc)) | ||||||||
| 1427 | .addReg(Op0Reg) | ||||||||
| 1428 | .addImm(Op1C->getSExtValue()); | ||||||||
| 1429 | return true; | ||||||||
| 1430 | } | ||||||||
| 1431 | } | ||||||||
| 1432 | |||||||||
| 1433 | unsigned CompareOpc = X86ChooseCmpOpcode(VT, Subtarget); | ||||||||
| 1434 | if (CompareOpc == 0) return false; | ||||||||
| 1435 | |||||||||
| 1436 | Register Op1Reg = getRegForValue(Op1); | ||||||||
| 1437 | if (Op1Reg == 0) return false; | ||||||||
| 1438 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, CurDbgLoc, TII.get(CompareOpc)) | ||||||||
| 1439 | .addReg(Op0Reg) | ||||||||
| 1440 | .addReg(Op1Reg); | ||||||||
| 1441 | |||||||||
| 1442 | return true; | ||||||||
| 1443 | } | ||||||||
| 1444 | |||||||||
| 1445 | bool X86FastISel::X86SelectCmp(const Instruction *I) { | ||||||||
| 1446 | const CmpInst *CI = cast<CmpInst>(I); | ||||||||
| 1447 | |||||||||
| 1448 | MVT VT; | ||||||||
| 1449 | if (!isTypeLegal(I->getOperand(0)->getType(), VT)) | ||||||||
| 1450 | return false; | ||||||||
| 1451 | |||||||||
| 1452 | // Below code only works for scalars. | ||||||||
| 1453 | if (VT.isVector()) | ||||||||
| 1454 | return false; | ||||||||
| 1455 | |||||||||
| 1456 | // Try to optimize or fold the cmp. | ||||||||
| 1457 | CmpInst::Predicate Predicate = optimizeCmpPredicate(CI); | ||||||||
| 1458 | unsigned ResultReg = 0; | ||||||||
| 1459 | switch (Predicate) { | ||||||||
| 1460 | default: break; | ||||||||
| 1461 | case CmpInst::FCMP_FALSE: { | ||||||||
| 1462 | ResultReg = createResultReg(&X86::GR32RegClass); | ||||||||
| 1463 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV32r0), | ||||||||
| 1464 | ResultReg); | ||||||||
| 1465 | ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultReg, X86::sub_8bit); | ||||||||
| 1466 | if (!ResultReg) | ||||||||
| 1467 | return false; | ||||||||
| 1468 | break; | ||||||||
| 1469 | } | ||||||||
| 1470 | case CmpInst::FCMP_TRUE: { | ||||||||
| 1471 | ResultReg = createResultReg(&X86::GR8RegClass); | ||||||||
| 1472 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri), | ||||||||
| 1473 | ResultReg).addImm(1); | ||||||||
| 1474 | break; | ||||||||
| 1475 | } | ||||||||
| 1476 | } | ||||||||
| 1477 | |||||||||
| 1478 | if (ResultReg) { | ||||||||
| 1479 | updateValueMap(I, ResultReg); | ||||||||
| 1480 | return true; | ||||||||
| 1481 | } | ||||||||
| 1482 | |||||||||
| 1483 | const Value *LHS = CI->getOperand(0); | ||||||||
| 1484 | const Value *RHS = CI->getOperand(1); | ||||||||
| 1485 | |||||||||
| 1486 | // The optimizer might have replaced fcmp oeq %x, %x with fcmp ord %x, 0.0. | ||||||||
| 1487 | // We don't have to materialize a zero constant for this case and can just use | ||||||||
| 1488 | // %x again on the RHS. | ||||||||
| 1489 | if (Predicate == CmpInst::FCMP_ORD || Predicate == CmpInst::FCMP_UNO) { | ||||||||
| 1490 | const auto *RHSC = dyn_cast<ConstantFP>(RHS); | ||||||||
| 1491 | if (RHSC && RHSC->isNullValue()) | ||||||||
| 1492 | RHS = LHS; | ||||||||
| 1493 | } | ||||||||
| 1494 | |||||||||
| 1495 | // FCMP_OEQ and FCMP_UNE cannot be checked with a single instruction. | ||||||||
| 1496 | static const uint16_t SETFOpcTable[2][3] = { | ||||||||
| 1497 | { X86::COND_E, X86::COND_NP, X86::AND8rr }, | ||||||||
| 1498 | { X86::COND_NE, X86::COND_P, X86::OR8rr } | ||||||||
| 1499 | }; | ||||||||
| 1500 | const uint16_t *SETFOpc = nullptr; | ||||||||
| 1501 | switch (Predicate) { | ||||||||
| 1502 | default: break; | ||||||||
| 1503 | case CmpInst::FCMP_OEQ: SETFOpc = &SETFOpcTable[0][0]; break; | ||||||||
| 1504 | case CmpInst::FCMP_UNE: SETFOpc = &SETFOpcTable[1][0]; break; | ||||||||
| 1505 | } | ||||||||
| 1506 | |||||||||
| 1507 | ResultReg = createResultReg(&X86::GR8RegClass); | ||||||||
| 1508 | if (SETFOpc) { | ||||||||
| 1509 | if (!X86FastEmitCompare(LHS, RHS, VT, I->getDebugLoc())) | ||||||||
| 1510 | return false; | ||||||||
| 1511 | |||||||||
| 1512 | Register FlagReg1 = createResultReg(&X86::GR8RegClass); | ||||||||
| 1513 | Register FlagReg2 = createResultReg(&X86::GR8RegClass); | ||||||||
| 1514 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr), | ||||||||
| 1515 | FlagReg1).addImm(SETFOpc[0]); | ||||||||
| 1516 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr), | ||||||||
| 1517 | FlagReg2).addImm(SETFOpc[1]); | ||||||||
| 1518 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[2]), | ||||||||
| 1519 | ResultReg).addReg(FlagReg1).addReg(FlagReg2); | ||||||||
| 1520 | updateValueMap(I, ResultReg); | ||||||||
| 1521 | return true; | ||||||||
| 1522 | } | ||||||||
| 1523 | |||||||||
| 1524 | X86::CondCode CC; | ||||||||
| 1525 | bool SwapArgs; | ||||||||
| 1526 | std::tie(CC, SwapArgs) = X86::getX86ConditionCode(Predicate); | ||||||||
| 1527 | assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.")((void)0); | ||||||||
| 1528 | |||||||||
| 1529 | if (SwapArgs) | ||||||||
| 1530 | std::swap(LHS, RHS); | ||||||||
| 1531 | |||||||||
| 1532 | // Emit a compare of LHS/RHS. | ||||||||
| 1533 | if (!X86FastEmitCompare(LHS, RHS, VT, I->getDebugLoc())) | ||||||||
| 1534 | return false; | ||||||||
| 1535 | |||||||||
| 1536 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr), | ||||||||
| 1537 | ResultReg).addImm(CC); | ||||||||
| 1538 | updateValueMap(I, ResultReg); | ||||||||
| 1539 | return true; | ||||||||
| 1540 | } | ||||||||
| 1541 | |||||||||
| 1542 | bool X86FastISel::X86SelectZExt(const Instruction *I) { | ||||||||
| 1543 | EVT DstVT = TLI.getValueType(DL, I->getType()); | ||||||||
| 1544 | if (!TLI.isTypeLegal(DstVT)) | ||||||||
| 1545 | return false; | ||||||||
| 1546 | |||||||||
| 1547 | Register ResultReg = getRegForValue(I->getOperand(0)); | ||||||||
| 1548 | if (ResultReg == 0) | ||||||||
| 1549 | return false; | ||||||||
| 1550 | |||||||||
| 1551 | // Handle zero-extension from i1 to i8, which is common. | ||||||||
| 1552 | MVT SrcVT = TLI.getSimpleValueType(DL, I->getOperand(0)->getType()); | ||||||||
| 1553 | if (SrcVT == MVT::i1) { | ||||||||
| 1554 | // Set the high bits to zero. | ||||||||
| 1555 | ResultReg = fastEmitZExtFromI1(MVT::i8, ResultReg); | ||||||||
| 1556 | SrcVT = MVT::i8; | ||||||||
| 1557 | |||||||||
| 1558 | if (ResultReg == 0) | ||||||||
| 1559 | return false; | ||||||||
| 1560 | } | ||||||||
| 1561 | |||||||||
| 1562 | if (DstVT == MVT::i64) { | ||||||||
| 1563 | // Handle extension to 64-bits via sub-register shenanigans. | ||||||||
| 1564 | unsigned MovInst; | ||||||||
| 1565 | |||||||||
| 1566 | switch (SrcVT.SimpleTy) { | ||||||||
| 1567 | case MVT::i8: MovInst = X86::MOVZX32rr8; break; | ||||||||
| 1568 | case MVT::i16: MovInst = X86::MOVZX32rr16; break; | ||||||||
| 1569 | case MVT::i32: MovInst = X86::MOV32rr; break; | ||||||||
| 1570 | default: llvm_unreachable("Unexpected zext to i64 source type")__builtin_unreachable(); | ||||||||
| 1571 | } | ||||||||
| 1572 | |||||||||
| 1573 | Register Result32 = createResultReg(&X86::GR32RegClass); | ||||||||
| 1574 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovInst), Result32) | ||||||||
| 1575 | .addReg(ResultReg); | ||||||||
| 1576 | |||||||||
| 1577 | ResultReg = createResultReg(&X86::GR64RegClass); | ||||||||
| 1578 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::SUBREG_TO_REG), | ||||||||
| 1579 | ResultReg) | ||||||||
| 1580 | .addImm(0).addReg(Result32).addImm(X86::sub_32bit); | ||||||||
| 1581 | } else if (DstVT == MVT::i16) { | ||||||||
| 1582 | // i8->i16 doesn't exist in the autogenerated isel table. Need to zero | ||||||||
| 1583 | // extend to 32-bits and then extract down to 16-bits. | ||||||||
| 1584 | Register Result32 = createResultReg(&X86::GR32RegClass); | ||||||||
| 1585 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOVZX32rr8), | ||||||||
| 1586 | Result32).addReg(ResultReg); | ||||||||
| 1587 | |||||||||
| 1588 | ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, X86::sub_16bit); | ||||||||
| 1589 | } else if (DstVT != MVT::i8) { | ||||||||
| 1590 | ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, | ||||||||
| 1591 | ResultReg); | ||||||||
| 1592 | if (ResultReg == 0) | ||||||||
| 1593 | return false; | ||||||||
| 1594 | } | ||||||||
| 1595 | |||||||||
| 1596 | updateValueMap(I, ResultReg); | ||||||||
| 1597 | return true; | ||||||||
| 1598 | } | ||||||||
| 1599 | |||||||||
| 1600 | bool X86FastISel::X86SelectSExt(const Instruction *I) { | ||||||||
| 1601 | EVT DstVT = TLI.getValueType(DL, I->getType()); | ||||||||
| 1602 | if (!TLI.isTypeLegal(DstVT)) | ||||||||
| 1603 | return false; | ||||||||
| 1604 | |||||||||
| 1605 | Register ResultReg = getRegForValue(I->getOperand(0)); | ||||||||
| 1606 | if (ResultReg == 0) | ||||||||
| 1607 | return false; | ||||||||
| 1608 | |||||||||
| 1609 | // Handle sign-extension from i1 to i8. | ||||||||
| 1610 | MVT SrcVT = TLI.getSimpleValueType(DL, I->getOperand(0)->getType()); | ||||||||
| 1611 | if (SrcVT == MVT::i1) { | ||||||||
| 1612 | // Set the high bits to zero. | ||||||||
| 1613 | Register ZExtReg = fastEmitZExtFromI1(MVT::i8, ResultReg); | ||||||||
| 1614 | if (ZExtReg == 0) | ||||||||
| 1615 | return false; | ||||||||
| 1616 | |||||||||
| 1617 | // Negate the result to make an 8-bit sign extended value. | ||||||||
| 1618 | ResultReg = createResultReg(&X86::GR8RegClass); | ||||||||
| 1619 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::NEG8r), | ||||||||
| 1620 | ResultReg).addReg(ZExtReg); | ||||||||
| 1621 | |||||||||
| 1622 | SrcVT = MVT::i8; | ||||||||
| 1623 | } | ||||||||
| 1624 | |||||||||
| 1625 | if (DstVT == MVT::i16) { | ||||||||
| 1626 | // i8->i16 doesn't exist in the autogenerated isel table. Need to sign | ||||||||
| 1627 | // extend to 32-bits and then extract down to 16-bits. | ||||||||
| 1628 | Register Result32 = createResultReg(&X86::GR32RegClass); | ||||||||
| 1629 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOVSX32rr8), | ||||||||
| 1630 | Result32).addReg(ResultReg); | ||||||||
| 1631 | |||||||||
| 1632 | ResultReg = fastEmitInst_extractsubreg(MVT::i16, Result32, X86::sub_16bit); | ||||||||
| 1633 | } else if (DstVT != MVT::i8) { | ||||||||
| 1634 | ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::SIGN_EXTEND, | ||||||||
| 1635 | ResultReg); | ||||||||
| 1636 | if (ResultReg == 0) | ||||||||
| 1637 | return false; | ||||||||
| 1638 | } | ||||||||
| 1639 | |||||||||
| 1640 | updateValueMap(I, ResultReg); | ||||||||
| 1641 | return true; | ||||||||
| 1642 | } | ||||||||
| 1643 | |||||||||
| 1644 | bool X86FastISel::X86SelectBranch(const Instruction *I) { | ||||||||
| 1645 | // Unconditional branches are selected by tablegen-generated code. | ||||||||
| 1646 | // Handle a conditional branch. | ||||||||
| 1647 | const BranchInst *BI = cast<BranchInst>(I); | ||||||||
| 1648 | MachineBasicBlock *TrueMBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; | ||||||||
| 1649 | MachineBasicBlock *FalseMBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; | ||||||||
| 1650 | |||||||||
| 1651 | // Fold the common case of a conditional branch with a comparison | ||||||||
| 1652 | // in the same block (values defined on other blocks may not have | ||||||||
| 1653 | // initialized registers). | ||||||||
| 1654 | X86::CondCode CC; | ||||||||
| 1655 | if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { | ||||||||
| 1656 | if (CI->hasOneUse() && CI->getParent() == I->getParent()) { | ||||||||
| 1657 | EVT VT = TLI.getValueType(DL, CI->getOperand(0)->getType()); | ||||||||
| 1658 | |||||||||
| 1659 | // Try to optimize or fold the cmp. | ||||||||
| 1660 | CmpInst::Predicate Predicate = optimizeCmpPredicate(CI); | ||||||||
| 1661 | switch (Predicate) { | ||||||||
| 1662 | default: break; | ||||||||
| 1663 | case CmpInst::FCMP_FALSE: fastEmitBranch(FalseMBB, DbgLoc); return true; | ||||||||
| 1664 | case CmpInst::FCMP_TRUE: fastEmitBranch(TrueMBB, DbgLoc); return true; | ||||||||
| 1665 | } | ||||||||
| 1666 | |||||||||
| 1667 | const Value *CmpLHS = CI->getOperand(0); | ||||||||
| 1668 | const Value *CmpRHS = CI->getOperand(1); | ||||||||
| 1669 | |||||||||
| 1670 | // The optimizer might have replaced fcmp oeq %x, %x with fcmp ord %x, | ||||||||
| 1671 | // 0.0. | ||||||||
| 1672 | // We don't have to materialize a zero constant for this case and can just | ||||||||
| 1673 | // use %x again on the RHS. | ||||||||
| 1674 | if (Predicate == CmpInst::FCMP_ORD || Predicate == CmpInst::FCMP_UNO) { | ||||||||
| 1675 | const auto *CmpRHSC = dyn_cast<ConstantFP>(CmpRHS); | ||||||||
| 1676 | if (CmpRHSC && CmpRHSC->isNullValue()) | ||||||||
| 1677 | CmpRHS = CmpLHS; | ||||||||
| 1678 | } | ||||||||
| 1679 | |||||||||
| 1680 | // Try to take advantage of fallthrough opportunities. | ||||||||
| 1681 | if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) { | ||||||||
| 1682 | std::swap(TrueMBB, FalseMBB); | ||||||||
| 1683 | Predicate = CmpInst::getInversePredicate(Predicate); | ||||||||
| 1684 | } | ||||||||
| 1685 | |||||||||
| 1686 | // FCMP_OEQ and FCMP_UNE cannot be expressed with a single flag/condition | ||||||||
| 1687 | // code check. Instead two branch instructions are required to check all | ||||||||
| 1688 | // the flags. First we change the predicate to a supported condition code, | ||||||||
| 1689 | // which will be the first branch. Later one we will emit the second | ||||||||
| 1690 | // branch. | ||||||||
| 1691 | bool NeedExtraBranch = false; | ||||||||
| 1692 | switch (Predicate) { | ||||||||
| 1693 | default: break; | ||||||||
| 1694 | case CmpInst::FCMP_OEQ: | ||||||||
| 1695 | std::swap(TrueMBB, FalseMBB); | ||||||||
| 1696 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||
| 1697 | case CmpInst::FCMP_UNE: | ||||||||
| 1698 | NeedExtraBranch = true; | ||||||||
| 1699 | Predicate = CmpInst::FCMP_ONE; | ||||||||
| 1700 | break; | ||||||||
| 1701 | } | ||||||||
| 1702 | |||||||||
| 1703 | bool SwapArgs; | ||||||||
| 1704 | std::tie(CC, SwapArgs) = X86::getX86ConditionCode(Predicate); | ||||||||
| 1705 | assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.")((void)0); | ||||||||
| 1706 | |||||||||
| 1707 | if (SwapArgs) | ||||||||
| 1708 | std::swap(CmpLHS, CmpRHS); | ||||||||
| 1709 | |||||||||
| 1710 | // Emit a compare of the LHS and RHS, setting the flags. | ||||||||
| 1711 | if (!X86FastEmitCompare(CmpLHS, CmpRHS, VT, CI->getDebugLoc())) | ||||||||
| 1712 | return false; | ||||||||
| 1713 | |||||||||
| 1714 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1)) | ||||||||
| 1715 | .addMBB(TrueMBB).addImm(CC); | ||||||||
| 1716 | |||||||||
| 1717 | // X86 requires a second branch to handle UNE (and OEQ, which is mapped | ||||||||
| 1718 | // to UNE above). | ||||||||
| 1719 | if (NeedExtraBranch) { | ||||||||
| 1720 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1)) | ||||||||
| 1721 | .addMBB(TrueMBB).addImm(X86::COND_P); | ||||||||
| 1722 | } | ||||||||
| 1723 | |||||||||
| 1724 | finishCondBranch(BI->getParent(), TrueMBB, FalseMBB); | ||||||||
| 1725 | return true; | ||||||||
| 1726 | } | ||||||||
| 1727 | } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) { | ||||||||
| 1728 | // Handle things like "%cond = trunc i32 %X to i1 / br i1 %cond", which | ||||||||
| 1729 | // typically happen for _Bool and C++ bools. | ||||||||
| 1730 | MVT SourceVT; | ||||||||
| 1731 | if (TI->hasOneUse() && TI->getParent() == I->getParent() && | ||||||||
| 1732 | isTypeLegal(TI->getOperand(0)->getType(), SourceVT)) { | ||||||||
| 1733 | unsigned TestOpc = 0; | ||||||||
| 1734 | switch (SourceVT.SimpleTy) { | ||||||||
| 1735 | default: break; | ||||||||
| 1736 | case MVT::i8: TestOpc = X86::TEST8ri; break; | ||||||||
| 1737 | case MVT::i16: TestOpc = X86::TEST16ri; break; | ||||||||
| 1738 | case MVT::i32: TestOpc = X86::TEST32ri; break; | ||||||||
| 1739 | case MVT::i64: TestOpc = X86::TEST64ri32; break; | ||||||||
| 1740 | } | ||||||||
| 1741 | if (TestOpc) { | ||||||||
| 1742 | Register OpReg = getRegForValue(TI->getOperand(0)); | ||||||||
| 1743 | if (OpReg == 0) return false; | ||||||||
| 1744 | |||||||||
| 1745 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TestOpc)) | ||||||||
| 1746 | .addReg(OpReg).addImm(1); | ||||||||
| 1747 | |||||||||
| 1748 | unsigned JmpCond = X86::COND_NE; | ||||||||
| 1749 | if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) { | ||||||||
| 1750 | std::swap(TrueMBB, FalseMBB); | ||||||||
| 1751 | JmpCond = X86::COND_E; | ||||||||
| 1752 | } | ||||||||
| 1753 | |||||||||
| 1754 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1)) | ||||||||
| 1755 | .addMBB(TrueMBB).addImm(JmpCond); | ||||||||
| 1756 | |||||||||
| 1757 | finishCondBranch(BI->getParent(), TrueMBB, FalseMBB); | ||||||||
| 1758 | return true; | ||||||||
| 1759 | } | ||||||||
| 1760 | } | ||||||||
| 1761 | } else if (foldX86XALUIntrinsic(CC, BI, BI->getCondition())) { | ||||||||
| 1762 | // Fake request the condition, otherwise the intrinsic might be completely | ||||||||
| 1763 | // optimized away. | ||||||||
| 1764 | Register TmpReg = getRegForValue(BI->getCondition()); | ||||||||
| 1765 | if (TmpReg == 0) | ||||||||
| 1766 | return false; | ||||||||
| 1767 | |||||||||
| 1768 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1)) | ||||||||
| 1769 | .addMBB(TrueMBB).addImm(CC); | ||||||||
| 1770 | finishCondBranch(BI->getParent(), TrueMBB, FalseMBB); | ||||||||
| 1771 | return true; | ||||||||
| 1772 | } | ||||||||
| 1773 | |||||||||
| 1774 | // Otherwise do a clumsy setcc and re-test it. | ||||||||
| 1775 | // Note that i1 essentially gets ANY_EXTEND'ed to i8 where it isn't used | ||||||||
| 1776 | // in an explicit cast, so make sure to handle that correctly. | ||||||||
| 1777 | Register OpReg = getRegForValue(BI->getCondition()); | ||||||||
| 1778 | if (OpReg == 0) return false; | ||||||||
| 1779 | |||||||||
| 1780 | // In case OpReg is a K register, COPY to a GPR | ||||||||
| 1781 | if (MRI.getRegClass(OpReg) == &X86::VK1RegClass) { | ||||||||
| 1782 | unsigned KOpReg = OpReg; | ||||||||
| 1783 | OpReg = createResultReg(&X86::GR32RegClass); | ||||||||
| 1784 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1785 | TII.get(TargetOpcode::COPY), OpReg) | ||||||||
| 1786 | .addReg(KOpReg); | ||||||||
| 1787 | OpReg = fastEmitInst_extractsubreg(MVT::i8, OpReg, X86::sub_8bit); | ||||||||
| 1788 | } | ||||||||
| 1789 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri)) | ||||||||
| 1790 | .addReg(OpReg) | ||||||||
| 1791 | .addImm(1); | ||||||||
| 1792 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::JCC_1)) | ||||||||
| 1793 | .addMBB(TrueMBB).addImm(X86::COND_NE); | ||||||||
| 1794 | finishCondBranch(BI->getParent(), TrueMBB, FalseMBB); | ||||||||
| 1795 | return true; | ||||||||
| 1796 | } | ||||||||
| 1797 | |||||||||
| 1798 | bool X86FastISel::X86SelectShift(const Instruction *I) { | ||||||||
| 1799 | unsigned CReg = 0, OpReg = 0; | ||||||||
| 1800 | const TargetRegisterClass *RC = nullptr; | ||||||||
| 1801 | if (I->getType()->isIntegerTy(8)) { | ||||||||
| 1802 | CReg = X86::CL; | ||||||||
| 1803 | RC = &X86::GR8RegClass; | ||||||||
| 1804 | switch (I->getOpcode()) { | ||||||||
| 1805 | case Instruction::LShr: OpReg = X86::SHR8rCL; break; | ||||||||
| 1806 | case Instruction::AShr: OpReg = X86::SAR8rCL; break; | ||||||||
| 1807 | case Instruction::Shl: OpReg = X86::SHL8rCL; break; | ||||||||
| 1808 | default: return false; | ||||||||
| 1809 | } | ||||||||
| 1810 | } else if (I->getType()->isIntegerTy(16)) { | ||||||||
| 1811 | CReg = X86::CX; | ||||||||
| 1812 | RC = &X86::GR16RegClass; | ||||||||
| 1813 | switch (I->getOpcode()) { | ||||||||
| 1814 | default: llvm_unreachable("Unexpected shift opcode")__builtin_unreachable(); | ||||||||
| 1815 | case Instruction::LShr: OpReg = X86::SHR16rCL; break; | ||||||||
| 1816 | case Instruction::AShr: OpReg = X86::SAR16rCL; break; | ||||||||
| 1817 | case Instruction::Shl: OpReg = X86::SHL16rCL; break; | ||||||||
| 1818 | } | ||||||||
| 1819 | } else if (I->getType()->isIntegerTy(32)) { | ||||||||
| 1820 | CReg = X86::ECX; | ||||||||
| 1821 | RC = &X86::GR32RegClass; | ||||||||
| 1822 | switch (I->getOpcode()) { | ||||||||
| 1823 | default: llvm_unreachable("Unexpected shift opcode")__builtin_unreachable(); | ||||||||
| 1824 | case Instruction::LShr: OpReg = X86::SHR32rCL; break; | ||||||||
| 1825 | case Instruction::AShr: OpReg = X86::SAR32rCL; break; | ||||||||
| 1826 | case Instruction::Shl: OpReg = X86::SHL32rCL; break; | ||||||||
| 1827 | } | ||||||||
| 1828 | } else if (I->getType()->isIntegerTy(64)) { | ||||||||
| 1829 | CReg = X86::RCX; | ||||||||
| 1830 | RC = &X86::GR64RegClass; | ||||||||
| 1831 | switch (I->getOpcode()) { | ||||||||
| 1832 | default: llvm_unreachable("Unexpected shift opcode")__builtin_unreachable(); | ||||||||
| 1833 | case Instruction::LShr: OpReg = X86::SHR64rCL; break; | ||||||||
| 1834 | case Instruction::AShr: OpReg = X86::SAR64rCL; break; | ||||||||
| 1835 | case Instruction::Shl: OpReg = X86::SHL64rCL; break; | ||||||||
| 1836 | } | ||||||||
| 1837 | } else { | ||||||||
| 1838 | return false; | ||||||||
| 1839 | } | ||||||||
| 1840 | |||||||||
| 1841 | MVT VT; | ||||||||
| 1842 | if (!isTypeLegal(I->getType(), VT)) | ||||||||
| 1843 | return false; | ||||||||
| 1844 | |||||||||
| 1845 | Register Op0Reg = getRegForValue(I->getOperand(0)); | ||||||||
| 1846 | if (Op0Reg == 0) return false; | ||||||||
| 1847 | |||||||||
| 1848 | Register Op1Reg = getRegForValue(I->getOperand(1)); | ||||||||
| 1849 | if (Op1Reg == 0) return false; | ||||||||
| 1850 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), | ||||||||
| 1851 | CReg).addReg(Op1Reg); | ||||||||
| 1852 | |||||||||
| 1853 | // The shift instruction uses X86::CL. If we defined a super-register | ||||||||
| 1854 | // of X86::CL, emit a subreg KILL to precisely describe what we're doing here. | ||||||||
| 1855 | if (CReg != X86::CL) | ||||||||
| 1856 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1857 | TII.get(TargetOpcode::KILL), X86::CL) | ||||||||
| 1858 | .addReg(CReg, RegState::Kill); | ||||||||
| 1859 | |||||||||
| 1860 | Register ResultReg = createResultReg(RC); | ||||||||
| 1861 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpReg), ResultReg) | ||||||||
| 1862 | .addReg(Op0Reg); | ||||||||
| 1863 | updateValueMap(I, ResultReg); | ||||||||
| 1864 | return true; | ||||||||
| 1865 | } | ||||||||
| 1866 | |||||||||
| 1867 | bool X86FastISel::X86SelectDivRem(const Instruction *I) { | ||||||||
| 1868 | const static unsigned NumTypes = 4; // i8, i16, i32, i64 | ||||||||
| 1869 | const static unsigned NumOps = 4; // SDiv, SRem, UDiv, URem | ||||||||
| 1870 | const static bool S = true; // IsSigned | ||||||||
| 1871 | const static bool U = false; // !IsSigned | ||||||||
| 1872 | const static unsigned Copy = TargetOpcode::COPY; | ||||||||
| 1873 | // For the X86 DIV/IDIV instruction, in most cases the dividend | ||||||||
| 1874 | // (numerator) must be in a specific register pair highreg:lowreg, | ||||||||
| 1875 | // producing the quotient in lowreg and the remainder in highreg. | ||||||||
| 1876 | // For most data types, to set up the instruction, the dividend is | ||||||||
| 1877 | // copied into lowreg, and lowreg is sign-extended or zero-extended | ||||||||
| 1878 | // into highreg. The exception is i8, where the dividend is defined | ||||||||
| 1879 | // as a single register rather than a register pair, and we | ||||||||
| 1880 | // therefore directly sign-extend or zero-extend the dividend into | ||||||||
| 1881 | // lowreg, instead of copying, and ignore the highreg. | ||||||||
| 1882 | const static struct DivRemEntry { | ||||||||
| 1883 | // The following portion depends only on the data type. | ||||||||
| 1884 | const TargetRegisterClass *RC; | ||||||||
| 1885 | unsigned LowInReg; // low part of the register pair | ||||||||
| 1886 | unsigned HighInReg; // high part of the register pair | ||||||||
| 1887 | // The following portion depends on both the data type and the operation. | ||||||||
| 1888 | struct DivRemResult { | ||||||||
| 1889 | unsigned OpDivRem; // The specific DIV/IDIV opcode to use. | ||||||||
| 1890 | unsigned OpSignExtend; // Opcode for sign-extending lowreg into | ||||||||
| 1891 | // highreg, or copying a zero into highreg. | ||||||||
| 1892 | unsigned OpCopy; // Opcode for copying dividend into lowreg, or | ||||||||
| 1893 | // zero/sign-extending into lowreg for i8. | ||||||||
| 1894 | unsigned DivRemResultReg; // Register containing the desired result. | ||||||||
| 1895 | bool IsOpSigned; // Whether to use signed or unsigned form. | ||||||||
| 1896 | } ResultTable[NumOps]; | ||||||||
| 1897 | } OpTable[NumTypes] = { | ||||||||
| 1898 | { &X86::GR8RegClass, X86::AX, 0, { | ||||||||
| 1899 | { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AL, S }, // SDiv | ||||||||
| 1900 | { X86::IDIV8r, 0, X86::MOVSX16rr8, X86::AH, S }, // SRem | ||||||||
| 1901 | { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AL, U }, // UDiv | ||||||||
| 1902 | { X86::DIV8r, 0, X86::MOVZX16rr8, X86::AH, U }, // URem | ||||||||
| 1903 | } | ||||||||
| 1904 | }, // i8 | ||||||||
| 1905 | { &X86::GR16RegClass, X86::AX, X86::DX, { | ||||||||
| 1906 | { X86::IDIV16r, X86::CWD, Copy, X86::AX, S }, // SDiv | ||||||||
| 1907 | { X86::IDIV16r, X86::CWD, Copy, X86::DX, S }, // SRem | ||||||||
| 1908 | { X86::DIV16r, X86::MOV32r0, Copy, X86::AX, U }, // UDiv | ||||||||
| 1909 | { X86::DIV16r, X86::MOV32r0, Copy, X86::DX, U }, // URem | ||||||||
| 1910 | } | ||||||||
| 1911 | }, // i16 | ||||||||
| 1912 | { &X86::GR32RegClass, X86::EAX, X86::EDX, { | ||||||||
| 1913 | { X86::IDIV32r, X86::CDQ, Copy, X86::EAX, S }, // SDiv | ||||||||
| 1914 | { X86::IDIV32r, X86::CDQ, Copy, X86::EDX, S }, // SRem | ||||||||
| 1915 | { X86::DIV32r, X86::MOV32r0, Copy, X86::EAX, U }, // UDiv | ||||||||
| 1916 | { X86::DIV32r, X86::MOV32r0, Copy, X86::EDX, U }, // URem | ||||||||
| 1917 | } | ||||||||
| 1918 | }, // i32 | ||||||||
| 1919 | { &X86::GR64RegClass, X86::RAX, X86::RDX, { | ||||||||
| 1920 | { X86::IDIV64r, X86::CQO, Copy, X86::RAX, S }, // SDiv | ||||||||
| 1921 | { X86::IDIV64r, X86::CQO, Copy, X86::RDX, S }, // SRem | ||||||||
| 1922 | { X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U }, // UDiv | ||||||||
| 1923 | { X86::DIV64r, X86::MOV32r0, Copy, X86::RDX, U }, // URem | ||||||||
| 1924 | } | ||||||||
| 1925 | }, // i64 | ||||||||
| 1926 | }; | ||||||||
| 1927 | |||||||||
| 1928 | MVT VT; | ||||||||
| 1929 | if (!isTypeLegal(I->getType(), VT)) | ||||||||
| 1930 | return false; | ||||||||
| 1931 | |||||||||
| 1932 | unsigned TypeIndex, OpIndex; | ||||||||
| 1933 | switch (VT.SimpleTy) { | ||||||||
| 1934 | default: return false; | ||||||||
| 1935 | case MVT::i8: TypeIndex = 0; break; | ||||||||
| 1936 | case MVT::i16: TypeIndex = 1; break; | ||||||||
| 1937 | case MVT::i32: TypeIndex = 2; break; | ||||||||
| 1938 | case MVT::i64: TypeIndex = 3; | ||||||||
| 1939 | if (!Subtarget->is64Bit()) | ||||||||
| 1940 | return false; | ||||||||
| 1941 | break; | ||||||||
| 1942 | } | ||||||||
| 1943 | |||||||||
| 1944 | switch (I->getOpcode()) { | ||||||||
| 1945 | default: llvm_unreachable("Unexpected div/rem opcode")__builtin_unreachable(); | ||||||||
| 1946 | case Instruction::SDiv: OpIndex = 0; break; | ||||||||
| 1947 | case Instruction::SRem: OpIndex = 1; break; | ||||||||
| 1948 | case Instruction::UDiv: OpIndex = 2; break; | ||||||||
| 1949 | case Instruction::URem: OpIndex = 3; break; | ||||||||
| 1950 | } | ||||||||
| 1951 | |||||||||
| 1952 | const DivRemEntry &TypeEntry = OpTable[TypeIndex]; | ||||||||
| 1953 | const DivRemEntry::DivRemResult &OpEntry = TypeEntry.ResultTable[OpIndex]; | ||||||||
| 1954 | Register Op0Reg = getRegForValue(I->getOperand(0)); | ||||||||
| 1955 | if (Op0Reg == 0) | ||||||||
| 1956 | return false; | ||||||||
| 1957 | Register Op1Reg = getRegForValue(I->getOperand(1)); | ||||||||
| 1958 | if (Op1Reg == 0) | ||||||||
| 1959 | return false; | ||||||||
| 1960 | |||||||||
| 1961 | // Move op0 into low-order input register. | ||||||||
| 1962 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1963 | TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg); | ||||||||
| 1964 | // Zero-extend or sign-extend into high-order input register. | ||||||||
| 1965 | if (OpEntry.OpSignExtend) { | ||||||||
| 1966 | if (OpEntry.IsOpSigned) | ||||||||
| 1967 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1968 | TII.get(OpEntry.OpSignExtend)); | ||||||||
| 1969 | else { | ||||||||
| 1970 | Register Zero32 = createResultReg(&X86::GR32RegClass); | ||||||||
| 1971 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1972 | TII.get(X86::MOV32r0), Zero32); | ||||||||
| 1973 | |||||||||
| 1974 | // Copy the zero into the appropriate sub/super/identical physical | ||||||||
| 1975 | // register. Unfortunately the operations needed are not uniform enough | ||||||||
| 1976 | // to fit neatly into the table above. | ||||||||
| 1977 | if (VT == MVT::i16) { | ||||||||
| 1978 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1979 | TII.get(Copy), TypeEntry.HighInReg) | ||||||||
| 1980 | .addReg(Zero32, 0, X86::sub_16bit); | ||||||||
| 1981 | } else if (VT == MVT::i32) { | ||||||||
| 1982 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1983 | TII.get(Copy), TypeEntry.HighInReg) | ||||||||
| 1984 | .addReg(Zero32); | ||||||||
| 1985 | } else if (VT == MVT::i64) { | ||||||||
| 1986 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1987 | TII.get(TargetOpcode::SUBREG_TO_REG), TypeEntry.HighInReg) | ||||||||
| 1988 | .addImm(0).addReg(Zero32).addImm(X86::sub_32bit); | ||||||||
| 1989 | } | ||||||||
| 1990 | } | ||||||||
| 1991 | } | ||||||||
| 1992 | // Generate the DIV/IDIV instruction. | ||||||||
| 1993 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 1994 | TII.get(OpEntry.OpDivRem)).addReg(Op1Reg); | ||||||||
| 1995 | // For i8 remainder, we can't reference ah directly, as we'll end | ||||||||
| 1996 | // up with bogus copies like %r9b = COPY %ah. Reference ax | ||||||||
| 1997 | // instead to prevent ah references in a rex instruction. | ||||||||
| 1998 | // | ||||||||
| 1999 | // The current assumption of the fast register allocator is that isel | ||||||||
| 2000 | // won't generate explicit references to the GR8_NOREX registers. If | ||||||||
| 2001 | // the allocator and/or the backend get enhanced to be more robust in | ||||||||
| 2002 | // that regard, this can be, and should be, removed. | ||||||||
| 2003 | unsigned ResultReg = 0; | ||||||||
| 2004 | if ((I->getOpcode() == Instruction::SRem || | ||||||||
| 2005 | I->getOpcode() == Instruction::URem) && | ||||||||
| 2006 | OpEntry.DivRemResultReg == X86::AH && Subtarget->is64Bit()) { | ||||||||
| 2007 | Register SourceSuperReg = createResultReg(&X86::GR16RegClass); | ||||||||
| 2008 | Register ResultSuperReg = createResultReg(&X86::GR16RegClass); | ||||||||
| 2009 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2010 | TII.get(Copy), SourceSuperReg).addReg(X86::AX); | ||||||||
| 2011 | |||||||||
| 2012 | // Shift AX right by 8 bits instead of using AH. | ||||||||
| 2013 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SHR16ri), | ||||||||
| 2014 | ResultSuperReg).addReg(SourceSuperReg).addImm(8); | ||||||||
| 2015 | |||||||||
| 2016 | // Now reference the 8-bit subreg of the result. | ||||||||
| 2017 | ResultReg = fastEmitInst_extractsubreg(MVT::i8, ResultSuperReg, | ||||||||
| 2018 | X86::sub_8bit); | ||||||||
| 2019 | } | ||||||||
| 2020 | // Copy the result out of the physreg if we haven't already. | ||||||||
| 2021 | if (!ResultReg) { | ||||||||
| 2022 | ResultReg = createResultReg(TypeEntry.RC); | ||||||||
| 2023 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Copy), ResultReg) | ||||||||
| 2024 | .addReg(OpEntry.DivRemResultReg); | ||||||||
| 2025 | } | ||||||||
| 2026 | updateValueMap(I, ResultReg); | ||||||||
| 2027 | |||||||||
| 2028 | return true; | ||||||||
| 2029 | } | ||||||||
| 2030 | |||||||||
| 2031 | /// Emit a conditional move instruction (if the are supported) to lower | ||||||||
| 2032 | /// the select. | ||||||||
| 2033 | bool X86FastISel::X86FastEmitCMoveSelect(MVT RetVT, const Instruction *I) { | ||||||||
| 2034 | // Check if the subtarget supports these instructions. | ||||||||
| 2035 | if (!Subtarget->hasCMov()) | ||||||||
| 2036 | return false; | ||||||||
| 2037 | |||||||||
| 2038 | // FIXME: Add support for i8. | ||||||||
| 2039 | if (RetVT < MVT::i16 || RetVT > MVT::i64) | ||||||||
| 2040 | return false; | ||||||||
| 2041 | |||||||||
| 2042 | const Value *Cond = I->getOperand(0); | ||||||||
| 2043 | const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); | ||||||||
| 2044 | bool NeedTest = true; | ||||||||
| 2045 | X86::CondCode CC = X86::COND_NE; | ||||||||
| 2046 | |||||||||
| 2047 | // Optimize conditions coming from a compare if both instructions are in the | ||||||||
| 2048 | // same basic block (values defined in other basic blocks may not have | ||||||||
| 2049 | // initialized registers). | ||||||||
| 2050 | const auto *CI = dyn_cast<CmpInst>(Cond); | ||||||||
| 2051 | if (CI && (CI->getParent() == I->getParent())) { | ||||||||
| 2052 | CmpInst::Predicate Predicate = optimizeCmpPredicate(CI); | ||||||||
| 2053 | |||||||||
| 2054 | // FCMP_OEQ and FCMP_UNE cannot be checked with a single instruction. | ||||||||
| 2055 | static const uint16_t SETFOpcTable[2][3] = { | ||||||||
| 2056 | { X86::COND_NP, X86::COND_E, X86::TEST8rr }, | ||||||||
| 2057 | { X86::COND_P, X86::COND_NE, X86::OR8rr } | ||||||||
| 2058 | }; | ||||||||
| 2059 | const uint16_t *SETFOpc = nullptr; | ||||||||
| 2060 | switch (Predicate) { | ||||||||
| 2061 | default: break; | ||||||||
| 2062 | case CmpInst::FCMP_OEQ: | ||||||||
| 2063 | SETFOpc = &SETFOpcTable[0][0]; | ||||||||
| 2064 | Predicate = CmpInst::ICMP_NE; | ||||||||
| 2065 | break; | ||||||||
| 2066 | case CmpInst::FCMP_UNE: | ||||||||
| 2067 | SETFOpc = &SETFOpcTable[1][0]; | ||||||||
| 2068 | Predicate = CmpInst::ICMP_NE; | ||||||||
| 2069 | break; | ||||||||
| 2070 | } | ||||||||
| 2071 | |||||||||
| 2072 | bool NeedSwap; | ||||||||
| 2073 | std::tie(CC, NeedSwap) = X86::getX86ConditionCode(Predicate); | ||||||||
| 2074 | assert(CC <= X86::LAST_VALID_COND && "Unexpected condition code.")((void)0); | ||||||||
| 2075 | |||||||||
| 2076 | const Value *CmpLHS = CI->getOperand(0); | ||||||||
| 2077 | const Value *CmpRHS = CI->getOperand(1); | ||||||||
| 2078 | if (NeedSwap) | ||||||||
| 2079 | std::swap(CmpLHS, CmpRHS); | ||||||||
| 2080 | |||||||||
| 2081 | EVT CmpVT = TLI.getValueType(DL, CmpLHS->getType()); | ||||||||
| 2082 | // Emit a compare of the LHS and RHS, setting the flags. | ||||||||
| 2083 | if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT, CI->getDebugLoc())) | ||||||||
| 2084 | return false; | ||||||||
| 2085 | |||||||||
| 2086 | if (SETFOpc) { | ||||||||
| 2087 | Register FlagReg1 = createResultReg(&X86::GR8RegClass); | ||||||||
| 2088 | Register FlagReg2 = createResultReg(&X86::GR8RegClass); | ||||||||
| 2089 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr), | ||||||||
| 2090 | FlagReg1).addImm(SETFOpc[0]); | ||||||||
| 2091 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr), | ||||||||
| 2092 | FlagReg2).addImm(SETFOpc[1]); | ||||||||
| 2093 | auto const &II = TII.get(SETFOpc[2]); | ||||||||
| 2094 | if (II.getNumDefs()) { | ||||||||
| 2095 | Register TmpReg = createResultReg(&X86::GR8RegClass); | ||||||||
| 2096 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, TmpReg) | ||||||||
| 2097 | .addReg(FlagReg2).addReg(FlagReg1); | ||||||||
| 2098 | } else { | ||||||||
| 2099 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) | ||||||||
| 2100 | .addReg(FlagReg2).addReg(FlagReg1); | ||||||||
| 2101 | } | ||||||||
| 2102 | } | ||||||||
| 2103 | NeedTest = false; | ||||||||
| 2104 | } else if (foldX86XALUIntrinsic(CC, I, Cond)) { | ||||||||
| 2105 | // Fake request the condition, otherwise the intrinsic might be completely | ||||||||
| 2106 | // optimized away. | ||||||||
| 2107 | Register TmpReg = getRegForValue(Cond); | ||||||||
| 2108 | if (TmpReg == 0) | ||||||||
| 2109 | return false; | ||||||||
| 2110 | |||||||||
| 2111 | NeedTest = false; | ||||||||
| 2112 | } | ||||||||
| 2113 | |||||||||
| 2114 | if (NeedTest) { | ||||||||
| 2115 | // Selects operate on i1, however, CondReg is 8 bits width and may contain | ||||||||
| 2116 | // garbage. Indeed, only the less significant bit is supposed to be | ||||||||
| 2117 | // accurate. If we read more than the lsb, we may see non-zero values | ||||||||
| 2118 | // whereas lsb is zero. Therefore, we have to truncate Op0Reg to i1 for | ||||||||
| 2119 | // the select. This is achieved by performing TEST against 1. | ||||||||
| 2120 | Register CondReg = getRegForValue(Cond); | ||||||||
| 2121 | if (CondReg == 0) | ||||||||
| 2122 | return false; | ||||||||
| 2123 | |||||||||
| 2124 | // In case OpReg is a K register, COPY to a GPR | ||||||||
| 2125 | if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) { | ||||||||
| 2126 | unsigned KCondReg = CondReg; | ||||||||
| 2127 | CondReg = createResultReg(&X86::GR32RegClass); | ||||||||
| 2128 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2129 | TII.get(TargetOpcode::COPY), CondReg) | ||||||||
| 2130 | .addReg(KCondReg); | ||||||||
| 2131 | CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, X86::sub_8bit); | ||||||||
| 2132 | } | ||||||||
| 2133 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri)) | ||||||||
| 2134 | .addReg(CondReg) | ||||||||
| 2135 | .addImm(1); | ||||||||
| 2136 | } | ||||||||
| 2137 | |||||||||
| 2138 | const Value *LHS = I->getOperand(1); | ||||||||
| 2139 | const Value *RHS = I->getOperand(2); | ||||||||
| 2140 | |||||||||
| 2141 | Register RHSReg = getRegForValue(RHS); | ||||||||
| 2142 | Register LHSReg = getRegForValue(LHS); | ||||||||
| 2143 | if (!LHSReg || !RHSReg) | ||||||||
| 2144 | return false; | ||||||||
| 2145 | |||||||||
| 2146 | const TargetRegisterInfo &TRI = *Subtarget->getRegisterInfo(); | ||||||||
| 2147 | unsigned Opc = X86::getCMovOpcode(TRI.getRegSizeInBits(*RC)/8); | ||||||||
| 2148 | Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC); | ||||||||
| 2149 | updateValueMap(I, ResultReg); | ||||||||
| 2150 | return true; | ||||||||
| 2151 | } | ||||||||
| 2152 | |||||||||
| 2153 | /// Emit SSE or AVX instructions to lower the select. | ||||||||
| 2154 | /// | ||||||||
| 2155 | /// Try to use SSE1/SSE2 instructions to simulate a select without branches. | ||||||||
| 2156 | /// This lowers fp selects into a CMP/AND/ANDN/OR sequence when the necessary | ||||||||
| 2157 | /// SSE instructions are available. If AVX is available, try to use a VBLENDV. | ||||||||
| 2158 | bool X86FastISel::X86FastEmitSSESelect(MVT RetVT, const Instruction *I) { | ||||||||
| 2159 | // Optimize conditions coming from a compare if both instructions are in the | ||||||||
| 2160 | // same basic block (values defined in other basic blocks may not have | ||||||||
| 2161 | // initialized registers). | ||||||||
| 2162 | const auto *CI = dyn_cast<FCmpInst>(I->getOperand(0)); | ||||||||
| 2163 | if (!CI || (CI->getParent() != I->getParent())) | ||||||||
| 2164 | return false; | ||||||||
| 2165 | |||||||||
| 2166 | if (I->getType() != CI->getOperand(0)->getType() || | ||||||||
| 2167 | !((Subtarget->hasSSE1() && RetVT == MVT::f32) || | ||||||||
| 2168 | (Subtarget->hasSSE2() && RetVT == MVT::f64))) | ||||||||
| 2169 | return false; | ||||||||
| 2170 | |||||||||
| 2171 | const Value *CmpLHS = CI->getOperand(0); | ||||||||
| 2172 | const Value *CmpRHS = CI->getOperand(1); | ||||||||
| 2173 | CmpInst::Predicate Predicate = optimizeCmpPredicate(CI); | ||||||||
| 2174 | |||||||||
| 2175 | // The optimizer might have replaced fcmp oeq %x, %x with fcmp ord %x, 0.0. | ||||||||
| 2176 | // We don't have to materialize a zero constant for this case and can just use | ||||||||
| 2177 | // %x again on the RHS. | ||||||||
| 2178 | if (Predicate == CmpInst::FCMP_ORD || Predicate == CmpInst::FCMP_UNO) { | ||||||||
| 2179 | const auto *CmpRHSC = dyn_cast<ConstantFP>(CmpRHS); | ||||||||
| 2180 | if (CmpRHSC && CmpRHSC->isNullValue()) | ||||||||
| 2181 | CmpRHS = CmpLHS; | ||||||||
| 2182 | } | ||||||||
| 2183 | |||||||||
| 2184 | unsigned CC; | ||||||||
| 2185 | bool NeedSwap; | ||||||||
| 2186 | std::tie(CC, NeedSwap) = getX86SSEConditionCode(Predicate); | ||||||||
| 2187 | if (CC > 7 && !Subtarget->hasAVX()) | ||||||||
| 2188 | return false; | ||||||||
| 2189 | |||||||||
| 2190 | if (NeedSwap) | ||||||||
| 2191 | std::swap(CmpLHS, CmpRHS); | ||||||||
| 2192 | |||||||||
| 2193 | const Value *LHS = I->getOperand(1); | ||||||||
| 2194 | const Value *RHS = I->getOperand(2); | ||||||||
| 2195 | |||||||||
| 2196 | Register LHSReg = getRegForValue(LHS); | ||||||||
| 2197 | Register RHSReg = getRegForValue(RHS); | ||||||||
| 2198 | Register CmpLHSReg = getRegForValue(CmpLHS); | ||||||||
| 2199 | Register CmpRHSReg = getRegForValue(CmpRHS); | ||||||||
| 2200 | if (!LHSReg || !RHSReg || !CmpLHSReg || !CmpRHSReg) | ||||||||
| 2201 | return false; | ||||||||
| 2202 | |||||||||
| 2203 | const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); | ||||||||
| 2204 | unsigned ResultReg; | ||||||||
| 2205 | |||||||||
| 2206 | if (Subtarget->hasAVX512()) { | ||||||||
| 2207 | // If we have AVX512 we can use a mask compare and masked movss/sd. | ||||||||
| 2208 | const TargetRegisterClass *VR128X = &X86::VR128XRegClass; | ||||||||
| 2209 | const TargetRegisterClass *VK1 = &X86::VK1RegClass; | ||||||||
| 2210 | |||||||||
| 2211 | unsigned CmpOpcode = | ||||||||
| 2212 | (RetVT == MVT::f32) ? X86::VCMPSSZrr : X86::VCMPSDZrr; | ||||||||
| 2213 | Register CmpReg = fastEmitInst_rri(CmpOpcode, VK1, CmpLHSReg, CmpRHSReg, | ||||||||
| 2214 | CC); | ||||||||
| 2215 | |||||||||
| 2216 | // Need an IMPLICIT_DEF for the input that is used to generate the upper | ||||||||
| 2217 | // bits of the result register since its not based on any of the inputs. | ||||||||
| 2218 | Register ImplicitDefReg = createResultReg(VR128X); | ||||||||
| 2219 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2220 | TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg); | ||||||||
| 2221 | |||||||||
| 2222 | // Place RHSReg is the passthru of the masked movss/sd operation and put | ||||||||
| 2223 | // LHS in the input. The mask input comes from the compare. | ||||||||
| 2224 | unsigned MovOpcode = | ||||||||
| 2225 | (RetVT == MVT::f32) ? X86::VMOVSSZrrk : X86::VMOVSDZrrk; | ||||||||
| 2226 | unsigned MovReg = fastEmitInst_rrrr(MovOpcode, VR128X, RHSReg, CmpReg, | ||||||||
| 2227 | ImplicitDefReg, LHSReg); | ||||||||
| 2228 | |||||||||
| 2229 | ResultReg = createResultReg(RC); | ||||||||
| 2230 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2231 | TII.get(TargetOpcode::COPY), ResultReg).addReg(MovReg); | ||||||||
| 2232 | |||||||||
| 2233 | } else if (Subtarget->hasAVX()) { | ||||||||
| 2234 | const TargetRegisterClass *VR128 = &X86::VR128RegClass; | ||||||||
| 2235 | |||||||||
| 2236 | // If we have AVX, create 1 blendv instead of 3 logic instructions. | ||||||||
| 2237 | // Blendv was introduced with SSE 4.1, but the 2 register form implicitly | ||||||||
| 2238 | // uses XMM0 as the selection register. That may need just as many | ||||||||
| 2239 | // instructions as the AND/ANDN/OR sequence due to register moves, so | ||||||||
| 2240 | // don't bother. | ||||||||
| 2241 | unsigned CmpOpcode = | ||||||||
| 2242 | (RetVT == MVT::f32) ? X86::VCMPSSrr : X86::VCMPSDrr; | ||||||||
| 2243 | unsigned BlendOpcode = | ||||||||
| 2244 | (RetVT == MVT::f32) ? X86::VBLENDVPSrr : X86::VBLENDVPDrr; | ||||||||
| 2245 | |||||||||
| 2246 | Register CmpReg = fastEmitInst_rri(CmpOpcode, RC, CmpLHSReg, CmpRHSReg, | ||||||||
| 2247 | CC); | ||||||||
| 2248 | Register VBlendReg = fastEmitInst_rrr(BlendOpcode, VR128, RHSReg, LHSReg, | ||||||||
| 2249 | CmpReg); | ||||||||
| 2250 | ResultReg = createResultReg(RC); | ||||||||
| 2251 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2252 | TII.get(TargetOpcode::COPY), ResultReg).addReg(VBlendReg); | ||||||||
| 2253 | } else { | ||||||||
| 2254 | // Choose the SSE instruction sequence based on data type (float or double). | ||||||||
| 2255 | static const uint16_t OpcTable[2][4] = { | ||||||||
| 2256 | { X86::CMPSSrr, X86::ANDPSrr, X86::ANDNPSrr, X86::ORPSrr }, | ||||||||
| 2257 | { X86::CMPSDrr, X86::ANDPDrr, X86::ANDNPDrr, X86::ORPDrr } | ||||||||
| 2258 | }; | ||||||||
| 2259 | |||||||||
| 2260 | const uint16_t *Opc = nullptr; | ||||||||
| 2261 | switch (RetVT.SimpleTy) { | ||||||||
| 2262 | default: return false; | ||||||||
| 2263 | case MVT::f32: Opc = &OpcTable[0][0]; break; | ||||||||
| 2264 | case MVT::f64: Opc = &OpcTable[1][0]; break; | ||||||||
| 2265 | } | ||||||||
| 2266 | |||||||||
| 2267 | const TargetRegisterClass *VR128 = &X86::VR128RegClass; | ||||||||
| 2268 | Register CmpReg = fastEmitInst_rri(Opc[0], RC, CmpLHSReg, CmpRHSReg, CC); | ||||||||
| 2269 | Register AndReg = fastEmitInst_rr(Opc[1], VR128, CmpReg, LHSReg); | ||||||||
| 2270 | Register AndNReg = fastEmitInst_rr(Opc[2], VR128, CmpReg, RHSReg); | ||||||||
| 2271 | Register OrReg = fastEmitInst_rr(Opc[3], VR128, AndNReg, AndReg); | ||||||||
| 2272 | ResultReg = createResultReg(RC); | ||||||||
| 2273 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2274 | TII.get(TargetOpcode::COPY), ResultReg).addReg(OrReg); | ||||||||
| 2275 | } | ||||||||
| 2276 | updateValueMap(I, ResultReg); | ||||||||
| 2277 | return true; | ||||||||
| 2278 | } | ||||||||
| 2279 | |||||||||
| 2280 | bool X86FastISel::X86FastEmitPseudoSelect(MVT RetVT, const Instruction *I) { | ||||||||
| 2281 | // These are pseudo CMOV instructions and will be later expanded into control- | ||||||||
| 2282 | // flow. | ||||||||
| 2283 | unsigned Opc; | ||||||||
| 2284 | switch (RetVT.SimpleTy) { | ||||||||
| 2285 | default: return false; | ||||||||
| 2286 | case MVT::i8: Opc = X86::CMOV_GR8; break; | ||||||||
| 2287 | case MVT::i16: Opc = X86::CMOV_GR16; break; | ||||||||
| 2288 | case MVT::i32: Opc = X86::CMOV_GR32; break; | ||||||||
| 2289 | case MVT::f32: Opc = Subtarget->hasAVX512() ? X86::CMOV_FR32X | ||||||||
| 2290 | : X86::CMOV_FR32; break; | ||||||||
| 2291 | case MVT::f64: Opc = Subtarget->hasAVX512() ? X86::CMOV_FR64X | ||||||||
| 2292 | : X86::CMOV_FR64; break; | ||||||||
| 2293 | } | ||||||||
| 2294 | |||||||||
| 2295 | const Value *Cond = I->getOperand(0); | ||||||||
| 2296 | X86::CondCode CC = X86::COND_NE; | ||||||||
| 2297 | |||||||||
| 2298 | // Optimize conditions coming from a compare if both instructions are in the | ||||||||
| 2299 | // same basic block (values defined in other basic blocks may not have | ||||||||
| 2300 | // initialized registers). | ||||||||
| 2301 | const auto *CI = dyn_cast<CmpInst>(Cond); | ||||||||
| 2302 | if (CI && (CI->getParent() == I->getParent())) { | ||||||||
| 2303 | bool NeedSwap; | ||||||||
| 2304 | std::tie(CC, NeedSwap) = X86::getX86ConditionCode(CI->getPredicate()); | ||||||||
| 2305 | if (CC > X86::LAST_VALID_COND) | ||||||||
| 2306 | return false; | ||||||||
| 2307 | |||||||||
| 2308 | const Value *CmpLHS = CI->getOperand(0); | ||||||||
| 2309 | const Value *CmpRHS = CI->getOperand(1); | ||||||||
| 2310 | |||||||||
| 2311 | if (NeedSwap) | ||||||||
| 2312 | std::swap(CmpLHS, CmpRHS); | ||||||||
| 2313 | |||||||||
| 2314 | EVT CmpVT = TLI.getValueType(DL, CmpLHS->getType()); | ||||||||
| 2315 | if (!X86FastEmitCompare(CmpLHS, CmpRHS, CmpVT, CI->getDebugLoc())) | ||||||||
| 2316 | return false; | ||||||||
| 2317 | } else { | ||||||||
| 2318 | Register CondReg = getRegForValue(Cond); | ||||||||
| 2319 | if (CondReg == 0) | ||||||||
| 2320 | return false; | ||||||||
| 2321 | |||||||||
| 2322 | // In case OpReg is a K register, COPY to a GPR | ||||||||
| 2323 | if (MRI.getRegClass(CondReg) == &X86::VK1RegClass) { | ||||||||
| 2324 | unsigned KCondReg = CondReg; | ||||||||
| 2325 | CondReg = createResultReg(&X86::GR32RegClass); | ||||||||
| 2326 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2327 | TII.get(TargetOpcode::COPY), CondReg) | ||||||||
| 2328 | .addReg(KCondReg); | ||||||||
| 2329 | CondReg = fastEmitInst_extractsubreg(MVT::i8, CondReg, X86::sub_8bit); | ||||||||
| 2330 | } | ||||||||
| 2331 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TEST8ri)) | ||||||||
| 2332 | .addReg(CondReg) | ||||||||
| 2333 | .addImm(1); | ||||||||
| 2334 | } | ||||||||
| 2335 | |||||||||
| 2336 | const Value *LHS = I->getOperand(1); | ||||||||
| 2337 | const Value *RHS = I->getOperand(2); | ||||||||
| 2338 | |||||||||
| 2339 | Register LHSReg = getRegForValue(LHS); | ||||||||
| 2340 | Register RHSReg = getRegForValue(RHS); | ||||||||
| 2341 | if (!LHSReg || !RHSReg) | ||||||||
| 2342 | return false; | ||||||||
| 2343 | |||||||||
| 2344 | const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); | ||||||||
| 2345 | |||||||||
| 2346 | Register ResultReg = | ||||||||
| 2347 | fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC); | ||||||||
| 2348 | updateValueMap(I, ResultReg); | ||||||||
| 2349 | return true; | ||||||||
| 2350 | } | ||||||||
| 2351 | |||||||||
| 2352 | bool X86FastISel::X86SelectSelect(const Instruction *I) { | ||||||||
| 2353 | MVT RetVT; | ||||||||
| 2354 | if (!isTypeLegal(I->getType(), RetVT)) | ||||||||
| 2355 | return false; | ||||||||
| 2356 | |||||||||
| 2357 | // Check if we can fold the select. | ||||||||
| 2358 | if (const auto *CI = dyn_cast<CmpInst>(I->getOperand(0))) { | ||||||||
| 2359 | CmpInst::Predicate Predicate = optimizeCmpPredicate(CI); | ||||||||
| 2360 | const Value *Opnd = nullptr; | ||||||||
| 2361 | switch (Predicate) { | ||||||||
| 2362 | default: break; | ||||||||
| 2363 | case CmpInst::FCMP_FALSE: Opnd = I->getOperand(2); break; | ||||||||
| 2364 | case CmpInst::FCMP_TRUE: Opnd = I->getOperand(1); break; | ||||||||
| 2365 | } | ||||||||
| 2366 | // No need for a select anymore - this is an unconditional move. | ||||||||
| 2367 | if (Opnd) { | ||||||||
| 2368 | Register OpReg = getRegForValue(Opnd); | ||||||||
| 2369 | if (OpReg == 0) | ||||||||
| 2370 | return false; | ||||||||
| 2371 | const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT); | ||||||||
| 2372 | Register ResultReg = createResultReg(RC); | ||||||||
| 2373 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2374 | TII.get(TargetOpcode::COPY), ResultReg) | ||||||||
| 2375 | .addReg(OpReg); | ||||||||
| 2376 | updateValueMap(I, ResultReg); | ||||||||
| 2377 | return true; | ||||||||
| 2378 | } | ||||||||
| 2379 | } | ||||||||
| 2380 | |||||||||
| 2381 | // First try to use real conditional move instructions. | ||||||||
| 2382 | if (X86FastEmitCMoveSelect(RetVT, I)) | ||||||||
| 2383 | return true; | ||||||||
| 2384 | |||||||||
| 2385 | // Try to use a sequence of SSE instructions to simulate a conditional move. | ||||||||
| 2386 | if (X86FastEmitSSESelect(RetVT, I)) | ||||||||
| 2387 | return true; | ||||||||
| 2388 | |||||||||
| 2389 | // Fall-back to pseudo conditional move instructions, which will be later | ||||||||
| 2390 | // converted to control-flow. | ||||||||
| 2391 | if (X86FastEmitPseudoSelect(RetVT, I)) | ||||||||
| 2392 | return true; | ||||||||
| 2393 | |||||||||
| 2394 | return false; | ||||||||
| 2395 | } | ||||||||
| 2396 | |||||||||
| 2397 | // Common code for X86SelectSIToFP and X86SelectUIToFP. | ||||||||
| 2398 | bool X86FastISel::X86SelectIntToFP(const Instruction *I, bool IsSigned) { | ||||||||
| 2399 | // The target-independent selection algorithm in FastISel already knows how | ||||||||
| 2400 | // to select a SINT_TO_FP if the target is SSE but not AVX. | ||||||||
| 2401 | // Early exit if the subtarget doesn't have AVX. | ||||||||
| 2402 | // Unsigned conversion requires avx512. | ||||||||
| 2403 | bool HasAVX512 = Subtarget->hasAVX512(); | ||||||||
| 2404 | if (!Subtarget->hasAVX() || (!IsSigned && !HasAVX512)) | ||||||||
| 2405 | return false; | ||||||||
| 2406 | |||||||||
| 2407 | // TODO: We could sign extend narrower types. | ||||||||
| 2408 | MVT SrcVT = TLI.getSimpleValueType(DL, I->getOperand(0)->getType()); | ||||||||
| 2409 | if (SrcVT != MVT::i32 && SrcVT != MVT::i64) | ||||||||
| 2410 | return false; | ||||||||
| 2411 | |||||||||
| 2412 | // Select integer to float/double conversion. | ||||||||
| 2413 | Register OpReg = getRegForValue(I->getOperand(0)); | ||||||||
| 2414 | if (OpReg == 0) | ||||||||
| 2415 | return false; | ||||||||
| 2416 | |||||||||
| 2417 | unsigned Opcode; | ||||||||
| 2418 | |||||||||
| 2419 | static const uint16_t SCvtOpc[2][2][2] = { | ||||||||
| 2420 | { { X86::VCVTSI2SSrr, X86::VCVTSI642SSrr }, | ||||||||
| 2421 | { X86::VCVTSI2SDrr, X86::VCVTSI642SDrr } }, | ||||||||
| 2422 | { { X86::VCVTSI2SSZrr, X86::VCVTSI642SSZrr }, | ||||||||
| 2423 | { X86::VCVTSI2SDZrr, X86::VCVTSI642SDZrr } }, | ||||||||
| 2424 | }; | ||||||||
| 2425 | static const uint16_t UCvtOpc[2][2] = { | ||||||||
| 2426 | { X86::VCVTUSI2SSZrr, X86::VCVTUSI642SSZrr }, | ||||||||
| 2427 | { X86::VCVTUSI2SDZrr, X86::VCVTUSI642SDZrr }, | ||||||||
| 2428 | }; | ||||||||
| 2429 | bool Is64Bit = SrcVT == MVT::i64; | ||||||||
| 2430 | |||||||||
| 2431 | if (I->getType()->isDoubleTy()) { | ||||||||
| 2432 | // s/uitofp int -> double | ||||||||
| 2433 | Opcode = IsSigned ? SCvtOpc[HasAVX512][1][Is64Bit] : UCvtOpc[1][Is64Bit]; | ||||||||
| 2434 | } else if (I->getType()->isFloatTy()) { | ||||||||
| 2435 | // s/uitofp int -> float | ||||||||
| 2436 | Opcode = IsSigned ? SCvtOpc[HasAVX512][0][Is64Bit] : UCvtOpc[0][Is64Bit]; | ||||||||
| 2437 | } else | ||||||||
| 2438 | return false; | ||||||||
| 2439 | |||||||||
| 2440 | MVT DstVT = TLI.getValueType(DL, I->getType()).getSimpleVT(); | ||||||||
| 2441 | const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT); | ||||||||
| 2442 | Register ImplicitDefReg = createResultReg(RC); | ||||||||
| 2443 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2444 | TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg); | ||||||||
| 2445 | Register ResultReg = fastEmitInst_rr(Opcode, RC, ImplicitDefReg, OpReg); | ||||||||
| 2446 | updateValueMap(I, ResultReg); | ||||||||
| 2447 | return true; | ||||||||
| 2448 | } | ||||||||
| 2449 | |||||||||
| 2450 | bool X86FastISel::X86SelectSIToFP(const Instruction *I) { | ||||||||
| 2451 | return X86SelectIntToFP(I, /*IsSigned*/true); | ||||||||
| 2452 | } | ||||||||
| 2453 | |||||||||
| 2454 | bool X86FastISel::X86SelectUIToFP(const Instruction *I) { | ||||||||
| 2455 | return X86SelectIntToFP(I, /*IsSigned*/false); | ||||||||
| 2456 | } | ||||||||
| 2457 | |||||||||
| 2458 | // Helper method used by X86SelectFPExt and X86SelectFPTrunc. | ||||||||
| 2459 | bool X86FastISel::X86SelectFPExtOrFPTrunc(const Instruction *I, | ||||||||
| 2460 | unsigned TargetOpc, | ||||||||
| 2461 | const TargetRegisterClass *RC) { | ||||||||
| 2462 | assert((I->getOpcode() == Instruction::FPExt ||((void)0) | ||||||||
| 2463 | I->getOpcode() == Instruction::FPTrunc) &&((void)0) | ||||||||
| 2464 | "Instruction must be an FPExt or FPTrunc!")((void)0); | ||||||||
| 2465 | bool HasAVX = Subtarget->hasAVX(); | ||||||||
| 2466 | |||||||||
| 2467 | Register OpReg = getRegForValue(I->getOperand(0)); | ||||||||
| 2468 | if (OpReg == 0) | ||||||||
| 2469 | return false; | ||||||||
| 2470 | |||||||||
| 2471 | unsigned ImplicitDefReg; | ||||||||
| 2472 | if (HasAVX) { | ||||||||
| 2473 | ImplicitDefReg = createResultReg(RC); | ||||||||
| 2474 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2475 | TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg); | ||||||||
| 2476 | |||||||||
| 2477 | } | ||||||||
| 2478 | |||||||||
| 2479 | Register ResultReg = createResultReg(RC); | ||||||||
| 2480 | MachineInstrBuilder MIB; | ||||||||
| 2481 | MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpc), | ||||||||
| 2482 | ResultReg); | ||||||||
| 2483 | |||||||||
| 2484 | if (HasAVX) | ||||||||
| 2485 | MIB.addReg(ImplicitDefReg); | ||||||||
| 2486 | |||||||||
| 2487 | MIB.addReg(OpReg); | ||||||||
| 2488 | updateValueMap(I, ResultReg); | ||||||||
| 2489 | return true; | ||||||||
| 2490 | } | ||||||||
| 2491 | |||||||||
| 2492 | bool X86FastISel::X86SelectFPExt(const Instruction *I) { | ||||||||
| 2493 | if (X86ScalarSSEf64 && I->getType()->isDoubleTy() && | ||||||||
| 2494 | I->getOperand(0)->getType()->isFloatTy()) { | ||||||||
| 2495 | bool HasAVX512 = Subtarget->hasAVX512(); | ||||||||
| 2496 | // fpext from float to double. | ||||||||
| 2497 | unsigned Opc = | ||||||||
| 2498 | HasAVX512 ? X86::VCVTSS2SDZrr | ||||||||
| 2499 | : Subtarget->hasAVX() ? X86::VCVTSS2SDrr : X86::CVTSS2SDrr; | ||||||||
| 2500 | return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f64)); | ||||||||
| 2501 | } | ||||||||
| 2502 | |||||||||
| 2503 | return false; | ||||||||
| 2504 | } | ||||||||
| 2505 | |||||||||
| 2506 | bool X86FastISel::X86SelectFPTrunc(const Instruction *I) { | ||||||||
| 2507 | if (X86ScalarSSEf64 && I->getType()->isFloatTy() && | ||||||||
| 2508 | I->getOperand(0)->getType()->isDoubleTy()) { | ||||||||
| 2509 | bool HasAVX512 = Subtarget->hasAVX512(); | ||||||||
| 2510 | // fptrunc from double to float. | ||||||||
| 2511 | unsigned Opc = | ||||||||
| 2512 | HasAVX512 ? X86::VCVTSD2SSZrr | ||||||||
| 2513 | : Subtarget->hasAVX() ? X86::VCVTSD2SSrr : X86::CVTSD2SSrr; | ||||||||
| 2514 | return X86SelectFPExtOrFPTrunc(I, Opc, TLI.getRegClassFor(MVT::f32)); | ||||||||
| 2515 | } | ||||||||
| 2516 | |||||||||
| 2517 | return false; | ||||||||
| 2518 | } | ||||||||
| 2519 | |||||||||
| 2520 | bool X86FastISel::X86SelectTrunc(const Instruction *I) { | ||||||||
| 2521 | EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); | ||||||||
| 2522 | EVT DstVT = TLI.getValueType(DL, I->getType()); | ||||||||
| 2523 | |||||||||
| 2524 | // This code only handles truncation to byte. | ||||||||
| 2525 | if (DstVT != MVT::i8 && DstVT != MVT::i1) | ||||||||
| 2526 | return false; | ||||||||
| 2527 | if (!TLI.isTypeLegal(SrcVT)) | ||||||||
| 2528 | return false; | ||||||||
| 2529 | |||||||||
| 2530 | Register InputReg = getRegForValue(I->getOperand(0)); | ||||||||
| 2531 | if (!InputReg) | ||||||||
| 2532 | // Unhandled operand. Halt "fast" selection and bail. | ||||||||
| 2533 | return false; | ||||||||
| 2534 | |||||||||
| 2535 | if (SrcVT == MVT::i8) { | ||||||||
| 2536 | // Truncate from i8 to i1; no code needed. | ||||||||
| 2537 | updateValueMap(I, InputReg); | ||||||||
| 2538 | return true; | ||||||||
| 2539 | } | ||||||||
| 2540 | |||||||||
| 2541 | // Issue an extract_subreg. | ||||||||
| 2542 | Register ResultReg = fastEmitInst_extractsubreg(MVT::i8, InputReg, | ||||||||
| 2543 | X86::sub_8bit); | ||||||||
| 2544 | if (!ResultReg) | ||||||||
| 2545 | return false; | ||||||||
| 2546 | |||||||||
| 2547 | updateValueMap(I, ResultReg); | ||||||||
| 2548 | return true; | ||||||||
| 2549 | } | ||||||||
| 2550 | |||||||||
| 2551 | bool X86FastISel::IsMemcpySmall(uint64_t Len) { | ||||||||
| 2552 | return Len <= (Subtarget->is64Bit() ? 32 : 16); | ||||||||
| 2553 | } | ||||||||
| 2554 | |||||||||
| 2555 | bool X86FastISel::TryEmitSmallMemcpy(X86AddressMode DestAM, | ||||||||
| 2556 | X86AddressMode SrcAM, uint64_t Len) { | ||||||||
| 2557 | |||||||||
| 2558 | // Make sure we don't bloat code by inlining very large memcpy's. | ||||||||
| 2559 | if (!IsMemcpySmall(Len)) | ||||||||
| 2560 | return false; | ||||||||
| 2561 | |||||||||
| 2562 | bool i64Legal = Subtarget->is64Bit(); | ||||||||
| 2563 | |||||||||
| 2564 | // We don't care about alignment here since we just emit integer accesses. | ||||||||
| 2565 | while (Len) { | ||||||||
| 2566 | MVT VT; | ||||||||
| 2567 | if (Len >= 8 && i64Legal) | ||||||||
| 2568 | VT = MVT::i64; | ||||||||
| 2569 | else if (Len >= 4) | ||||||||
| 2570 | VT = MVT::i32; | ||||||||
| 2571 | else if (Len >= 2) | ||||||||
| 2572 | VT = MVT::i16; | ||||||||
| 2573 | else | ||||||||
| 2574 | VT = MVT::i8; | ||||||||
| 2575 | |||||||||
| 2576 | unsigned Reg; | ||||||||
| 2577 | bool RV = X86FastEmitLoad(VT, SrcAM, nullptr, Reg); | ||||||||
| 2578 | RV &= X86FastEmitStore(VT, Reg, DestAM); | ||||||||
| 2579 | assert(RV && "Failed to emit load or store??")((void)0); | ||||||||
| 2580 | (void)RV; | ||||||||
| 2581 | |||||||||
| 2582 | unsigned Size = VT.getSizeInBits()/8; | ||||||||
| 2583 | Len -= Size; | ||||||||
| 2584 | DestAM.Disp += Size; | ||||||||
| 2585 | SrcAM.Disp += Size; | ||||||||
| 2586 | } | ||||||||
| 2587 | |||||||||
| 2588 | return true; | ||||||||
| 2589 | } | ||||||||
| 2590 | |||||||||
| 2591 | bool X86FastISel::fastLowerIntrinsicCall(const IntrinsicInst *II) { | ||||||||
| 2592 | // FIXME: Handle more intrinsics. | ||||||||
| 2593 | switch (II->getIntrinsicID()) { | ||||||||
| 2594 | default: return false; | ||||||||
| 2595 | case Intrinsic::convert_from_fp16: | ||||||||
| 2596 | case Intrinsic::convert_to_fp16: { | ||||||||
| 2597 | if (Subtarget->useSoftFloat() || !Subtarget->hasF16C()) | ||||||||
| 2598 | return false; | ||||||||
| 2599 | |||||||||
| 2600 | const Value *Op = II->getArgOperand(0); | ||||||||
| 2601 | Register InputReg = getRegForValue(Op); | ||||||||
| 2602 | if (InputReg == 0) | ||||||||
| 2603 | return false; | ||||||||
| 2604 | |||||||||
| 2605 | // F16C only allows converting from float to half and from half to float. | ||||||||
| 2606 | bool IsFloatToHalf = II->getIntrinsicID() == Intrinsic::convert_to_fp16; | ||||||||
| 2607 | if (IsFloatToHalf) { | ||||||||
| 2608 | if (!Op->getType()->isFloatTy()) | ||||||||
| 2609 | return false; | ||||||||
| 2610 | } else { | ||||||||
| 2611 | if (!II->getType()->isFloatTy()) | ||||||||
| 2612 | return false; | ||||||||
| 2613 | } | ||||||||
| 2614 | |||||||||
| 2615 | unsigned ResultReg = 0; | ||||||||
| 2616 | const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16); | ||||||||
| 2617 | if (IsFloatToHalf) { | ||||||||
| 2618 | // 'InputReg' is implicitly promoted from register class FR32 to | ||||||||
| 2619 | // register class VR128 by method 'constrainOperandRegClass' which is | ||||||||
| 2620 | // directly called by 'fastEmitInst_ri'. | ||||||||
| 2621 | // Instruction VCVTPS2PHrr takes an extra immediate operand which is | ||||||||
| 2622 | // used to provide rounding control: use MXCSR.RC, encoded as 0b100. | ||||||||
| 2623 | // It's consistent with the other FP instructions, which are usually | ||||||||
| 2624 | // controlled by MXCSR. | ||||||||
| 2625 | unsigned Opc = Subtarget->hasVLX() ? X86::VCVTPS2PHZ128rr | ||||||||
| 2626 | : X86::VCVTPS2PHrr; | ||||||||
| 2627 | InputReg = fastEmitInst_ri(Opc, RC, InputReg, 4); | ||||||||
| 2628 | |||||||||
| 2629 | // Move the lower 32-bits of ResultReg to another register of class GR32. | ||||||||
| 2630 | Opc = Subtarget->hasAVX512() ? X86::VMOVPDI2DIZrr | ||||||||
| 2631 | : X86::VMOVPDI2DIrr; | ||||||||
| 2632 | ResultReg = createResultReg(&X86::GR32RegClass); | ||||||||
| 2633 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) | ||||||||
| 2634 | .addReg(InputReg, RegState::Kill); | ||||||||
| 2635 | |||||||||
| 2636 | // The result value is in the lower 16-bits of ResultReg. | ||||||||
| 2637 | unsigned RegIdx = X86::sub_16bit; | ||||||||
| 2638 | ResultReg = fastEmitInst_extractsubreg(MVT::i16, ResultReg, RegIdx); | ||||||||
| 2639 | } else { | ||||||||
| 2640 | assert(Op->getType()->isIntegerTy(16) && "Expected a 16-bit integer!")((void)0); | ||||||||
| 2641 | // Explicitly zero-extend the input to 32-bit. | ||||||||
| 2642 | InputReg = fastEmit_r(MVT::i16, MVT::i32, ISD::ZERO_EXTEND, InputReg); | ||||||||
| 2643 | |||||||||
| 2644 | // The following SCALAR_TO_VECTOR will be expanded into a VMOVDI2PDIrr. | ||||||||
| 2645 | InputReg = fastEmit_r(MVT::i32, MVT::v4i32, ISD::SCALAR_TO_VECTOR, | ||||||||
| 2646 | InputReg); | ||||||||
| 2647 | |||||||||
| 2648 | unsigned Opc = Subtarget->hasVLX() ? X86::VCVTPH2PSZ128rr | ||||||||
| 2649 | : X86::VCVTPH2PSrr; | ||||||||
| 2650 | InputReg = fastEmitInst_r(Opc, RC, InputReg); | ||||||||
| 2651 | |||||||||
| 2652 | // The result value is in the lower 32-bits of ResultReg. | ||||||||
| 2653 | // Emit an explicit copy from register class VR128 to register class FR32. | ||||||||
| 2654 | ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); | ||||||||
| 2655 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2656 | TII.get(TargetOpcode::COPY), ResultReg) | ||||||||
| 2657 | .addReg(InputReg, RegState::Kill); | ||||||||
| 2658 | } | ||||||||
| 2659 | |||||||||
| 2660 | updateValueMap(II, ResultReg); | ||||||||
| 2661 | return true; | ||||||||
| 2662 | } | ||||||||
| 2663 | case Intrinsic::frameaddress: { | ||||||||
| 2664 | MachineFunction *MF = FuncInfo.MF; | ||||||||
| 2665 | if (MF->getTarget().getMCAsmInfo()->usesWindowsCFI()) | ||||||||
| 2666 | return false; | ||||||||
| 2667 | |||||||||
| 2668 | Type *RetTy = II->getCalledFunction()->getReturnType(); | ||||||||
| 2669 | |||||||||
| 2670 | MVT VT; | ||||||||
| 2671 | if (!isTypeLegal(RetTy, VT)) | ||||||||
| 2672 | return false; | ||||||||
| 2673 | |||||||||
| 2674 | unsigned Opc; | ||||||||
| 2675 | const TargetRegisterClass *RC = nullptr; | ||||||||
| 2676 | |||||||||
| 2677 | switch (VT.SimpleTy) { | ||||||||
| 2678 | default: llvm_unreachable("Invalid result type for frameaddress.")__builtin_unreachable(); | ||||||||
| 2679 | case MVT::i32: Opc = X86::MOV32rm; RC = &X86::GR32RegClass; break; | ||||||||
| 2680 | case MVT::i64: Opc = X86::MOV64rm; RC = &X86::GR64RegClass; break; | ||||||||
| 2681 | } | ||||||||
| 2682 | |||||||||
| 2683 | // This needs to be set before we call getPtrSizedFrameRegister, otherwise | ||||||||
| 2684 | // we get the wrong frame register. | ||||||||
| 2685 | MachineFrameInfo &MFI = MF->getFrameInfo(); | ||||||||
| 2686 | MFI.setFrameAddressIsTaken(true); | ||||||||
| 2687 | |||||||||
| 2688 | const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo(); | ||||||||
| 2689 | unsigned FrameReg = RegInfo->getPtrSizedFrameRegister(*MF); | ||||||||
| 2690 | assert(((FrameReg == X86::RBP && VT == MVT::i64) ||((void)0) | ||||||||
| 2691 | (FrameReg == X86::EBP && VT == MVT::i32)) &&((void)0) | ||||||||
| 2692 | "Invalid Frame Register!")((void)0); | ||||||||
| 2693 | |||||||||
| 2694 | // Always make a copy of the frame register to a vreg first, so that we | ||||||||
| 2695 | // never directly reference the frame register (the TwoAddressInstruction- | ||||||||
| 2696 | // Pass doesn't like that). | ||||||||
| 2697 | Register SrcReg = createResultReg(RC); | ||||||||
| 2698 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2699 | TII.get(TargetOpcode::COPY), SrcReg).addReg(FrameReg); | ||||||||
| 2700 | |||||||||
| 2701 | // Now recursively load from the frame address. | ||||||||
| 2702 | // movq (%rbp), %rax | ||||||||
| 2703 | // movq (%rax), %rax | ||||||||
| 2704 | // movq (%rax), %rax | ||||||||
| 2705 | // ... | ||||||||
| 2706 | unsigned Depth = cast<ConstantInt>(II->getOperand(0))->getZExtValue(); | ||||||||
| 2707 | while (Depth--) { | ||||||||
| 2708 | Register DestReg = createResultReg(RC); | ||||||||
| 2709 | addDirectMem(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2710 | TII.get(Opc), DestReg), SrcReg); | ||||||||
| 2711 | SrcReg = DestReg; | ||||||||
| 2712 | } | ||||||||
| 2713 | |||||||||
| 2714 | updateValueMap(II, SrcReg); | ||||||||
| 2715 | return true; | ||||||||
| 2716 | } | ||||||||
| 2717 | case Intrinsic::memcpy: { | ||||||||
| 2718 | const MemCpyInst *MCI = cast<MemCpyInst>(II); | ||||||||
| 2719 | // Don't handle volatile or variable length memcpys. | ||||||||
| 2720 | if (MCI->isVolatile()) | ||||||||
| 2721 | return false; | ||||||||
| 2722 | |||||||||
| 2723 | if (isa<ConstantInt>(MCI->getLength())) { | ||||||||
| 2724 | // Small memcpy's are common enough that we want to do them | ||||||||
| 2725 | // without a call if possible. | ||||||||
| 2726 | uint64_t Len = cast<ConstantInt>(MCI->getLength())->getZExtValue(); | ||||||||
| 2727 | if (IsMemcpySmall(Len)) { | ||||||||
| 2728 | X86AddressMode DestAM, SrcAM; | ||||||||
| 2729 | if (!X86SelectAddress(MCI->getRawDest(), DestAM) || | ||||||||
| 2730 | !X86SelectAddress(MCI->getRawSource(), SrcAM)) | ||||||||
| 2731 | return false; | ||||||||
| 2732 | TryEmitSmallMemcpy(DestAM, SrcAM, Len); | ||||||||
| 2733 | return true; | ||||||||
| 2734 | } | ||||||||
| 2735 | } | ||||||||
| 2736 | |||||||||
| 2737 | unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32; | ||||||||
| 2738 | if (!MCI->getLength()->getType()->isIntegerTy(SizeWidth)) | ||||||||
| 2739 | return false; | ||||||||
| 2740 | |||||||||
| 2741 | if (MCI->getSourceAddressSpace() > 255 || MCI->getDestAddressSpace() > 255) | ||||||||
| 2742 | return false; | ||||||||
| 2743 | |||||||||
| 2744 | return lowerCallTo(II, "memcpy", II->getNumArgOperands() - 1); | ||||||||
| 2745 | } | ||||||||
| 2746 | case Intrinsic::memset: { | ||||||||
| 2747 | const MemSetInst *MSI = cast<MemSetInst>(II); | ||||||||
| 2748 | |||||||||
| 2749 | if (MSI->isVolatile()) | ||||||||
| 2750 | return false; | ||||||||
| 2751 | |||||||||
| 2752 | unsigned SizeWidth = Subtarget->is64Bit() ? 64 : 32; | ||||||||
| 2753 | if (!MSI->getLength()->getType()->isIntegerTy(SizeWidth)) | ||||||||
| 2754 | return false; | ||||||||
| 2755 | |||||||||
| 2756 | if (MSI->getDestAddressSpace() > 255) | ||||||||
| 2757 | return false; | ||||||||
| 2758 | |||||||||
| 2759 | return lowerCallTo(II, "memset", II->getNumArgOperands() - 1); | ||||||||
| 2760 | } | ||||||||
| 2761 | case Intrinsic::stackprotector: { | ||||||||
| 2762 | // Emit code to store the stack guard onto the stack. | ||||||||
| 2763 | EVT PtrTy = TLI.getPointerTy(DL); | ||||||||
| 2764 | |||||||||
| 2765 | const Value *Op1 = II->getArgOperand(0); // The guard's value. | ||||||||
| 2766 | const AllocaInst *Slot = cast<AllocaInst>(II->getArgOperand(1)); | ||||||||
| 2767 | |||||||||
| 2768 | MFI.setStackProtectorIndex(FuncInfo.StaticAllocaMap[Slot]); | ||||||||
| 2769 | |||||||||
| 2770 | // Grab the frame index. | ||||||||
| 2771 | X86AddressMode AM; | ||||||||
| 2772 | if (!X86SelectAddress(Slot, AM)) return false; | ||||||||
| 2773 | if (!X86FastEmitStore(PtrTy, Op1, AM)) return false; | ||||||||
| 2774 | return true; | ||||||||
| 2775 | } | ||||||||
| 2776 | case Intrinsic::dbg_declare: { | ||||||||
| 2777 | const DbgDeclareInst *DI = cast<DbgDeclareInst>(II); | ||||||||
| 2778 | X86AddressMode AM; | ||||||||
| 2779 | assert(DI->getAddress() && "Null address should be checked earlier!")((void)0); | ||||||||
| 2780 | if (!X86SelectAddress(DI->getAddress(), AM)) | ||||||||
| 2781 | return false; | ||||||||
| 2782 | const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); | ||||||||
| 2783 | // FIXME may need to add RegState::Debug to any registers produced, | ||||||||
| 2784 | // although ESP/EBP should be the only ones at the moment. | ||||||||
| 2785 | assert(DI->getVariable()->isValidLocationForIntrinsic(DbgLoc) &&((void)0) | ||||||||
| 2786 | "Expected inlined-at fields to agree")((void)0); | ||||||||
| 2787 | addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II), AM) | ||||||||
| 2788 | .addImm(0) | ||||||||
| 2789 | .addMetadata(DI->getVariable()) | ||||||||
| 2790 | .addMetadata(DI->getExpression()); | ||||||||
| 2791 | return true; | ||||||||
| 2792 | } | ||||||||
| 2793 | case Intrinsic::trap: { | ||||||||
| 2794 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::TRAP)); | ||||||||
| 2795 | return true; | ||||||||
| 2796 | } | ||||||||
| 2797 | case Intrinsic::sqrt: { | ||||||||
| 2798 | if (!Subtarget->hasSSE1()) | ||||||||
| 2799 | return false; | ||||||||
| 2800 | |||||||||
| 2801 | Type *RetTy = II->getCalledFunction()->getReturnType(); | ||||||||
| 2802 | |||||||||
| 2803 | MVT VT; | ||||||||
| 2804 | if (!isTypeLegal(RetTy, VT)) | ||||||||
| 2805 | return false; | ||||||||
| 2806 | |||||||||
| 2807 | // Unfortunately we can't use fastEmit_r, because the AVX version of FSQRT | ||||||||
| 2808 | // is not generated by FastISel yet. | ||||||||
| 2809 | // FIXME: Update this code once tablegen can handle it. | ||||||||
| 2810 | static const uint16_t SqrtOpc[3][2] = { | ||||||||
| 2811 | { X86::SQRTSSr, X86::SQRTSDr }, | ||||||||
| 2812 | { X86::VSQRTSSr, X86::VSQRTSDr }, | ||||||||
| 2813 | { X86::VSQRTSSZr, X86::VSQRTSDZr }, | ||||||||
| 2814 | }; | ||||||||
| 2815 | unsigned AVXLevel = Subtarget->hasAVX512() ? 2 : | ||||||||
| 2816 | Subtarget->hasAVX() ? 1 : | ||||||||
| 2817 | 0; | ||||||||
| 2818 | unsigned Opc; | ||||||||
| 2819 | switch (VT.SimpleTy) { | ||||||||
| 2820 | default: return false; | ||||||||
| 2821 | case MVT::f32: Opc = SqrtOpc[AVXLevel][0]; break; | ||||||||
| 2822 | case MVT::f64: Opc = SqrtOpc[AVXLevel][1]; break; | ||||||||
| 2823 | } | ||||||||
| 2824 | |||||||||
| 2825 | const Value *SrcVal = II->getArgOperand(0); | ||||||||
| 2826 | Register SrcReg = getRegForValue(SrcVal); | ||||||||
| 2827 | |||||||||
| 2828 | if (SrcReg == 0) | ||||||||
| 2829 | return false; | ||||||||
| 2830 | |||||||||
| 2831 | const TargetRegisterClass *RC = TLI.getRegClassFor(VT); | ||||||||
| 2832 | unsigned ImplicitDefReg = 0; | ||||||||
| 2833 | if (AVXLevel > 0) { | ||||||||
| 2834 | ImplicitDefReg = createResultReg(RC); | ||||||||
| 2835 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2836 | TII.get(TargetOpcode::IMPLICIT_DEF), ImplicitDefReg); | ||||||||
| 2837 | } | ||||||||
| 2838 | |||||||||
| 2839 | Register ResultReg = createResultReg(RC); | ||||||||
| 2840 | MachineInstrBuilder MIB; | ||||||||
| 2841 | MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), | ||||||||
| 2842 | ResultReg); | ||||||||
| 2843 | |||||||||
| 2844 | if (ImplicitDefReg) | ||||||||
| 2845 | MIB.addReg(ImplicitDefReg); | ||||||||
| 2846 | |||||||||
| 2847 | MIB.addReg(SrcReg); | ||||||||
| 2848 | |||||||||
| 2849 | updateValueMap(II, ResultReg); | ||||||||
| 2850 | return true; | ||||||||
| 2851 | } | ||||||||
| 2852 | case Intrinsic::sadd_with_overflow: | ||||||||
| 2853 | case Intrinsic::uadd_with_overflow: | ||||||||
| 2854 | case Intrinsic::ssub_with_overflow: | ||||||||
| 2855 | case Intrinsic::usub_with_overflow: | ||||||||
| 2856 | case Intrinsic::smul_with_overflow: | ||||||||
| 2857 | case Intrinsic::umul_with_overflow: { | ||||||||
| 2858 | // This implements the basic lowering of the xalu with overflow intrinsics | ||||||||
| 2859 | // into add/sub/mul followed by either seto or setb. | ||||||||
| 2860 | const Function *Callee = II->getCalledFunction(); | ||||||||
| 2861 | auto *Ty = cast<StructType>(Callee->getReturnType()); | ||||||||
| 2862 | Type *RetTy = Ty->getTypeAtIndex(0U); | ||||||||
| 2863 | assert(Ty->getTypeAtIndex(1)->isIntegerTy() &&((void)0) | ||||||||
| 2864 | Ty->getTypeAtIndex(1)->getScalarSizeInBits() == 1 &&((void)0) | ||||||||
| 2865 | "Overflow value expected to be an i1")((void)0); | ||||||||
| 2866 | |||||||||
| 2867 | MVT VT; | ||||||||
| 2868 | if (!isTypeLegal(RetTy, VT)) | ||||||||
| 2869 | return false; | ||||||||
| 2870 | |||||||||
| 2871 | if (VT < MVT::i8 || VT > MVT::i64) | ||||||||
| 2872 | return false; | ||||||||
| 2873 | |||||||||
| 2874 | const Value *LHS = II->getArgOperand(0); | ||||||||
| 2875 | const Value *RHS = II->getArgOperand(1); | ||||||||
| 2876 | |||||||||
| 2877 | // Canonicalize immediate to the RHS. | ||||||||
| 2878 | if (isa<ConstantInt>(LHS) && !isa<ConstantInt>(RHS) && II->isCommutative()) | ||||||||
| 2879 | std::swap(LHS, RHS); | ||||||||
| 2880 | |||||||||
| 2881 | unsigned BaseOpc, CondCode; | ||||||||
| 2882 | switch (II->getIntrinsicID()) { | ||||||||
| 2883 | default: llvm_unreachable("Unexpected intrinsic!")__builtin_unreachable(); | ||||||||
| 2884 | case Intrinsic::sadd_with_overflow: | ||||||||
| 2885 | BaseOpc = ISD::ADD; CondCode = X86::COND_O; break; | ||||||||
| 2886 | case Intrinsic::uadd_with_overflow: | ||||||||
| 2887 | BaseOpc = ISD::ADD; CondCode = X86::COND_B; break; | ||||||||
| 2888 | case Intrinsic::ssub_with_overflow: | ||||||||
| 2889 | BaseOpc = ISD::SUB; CondCode = X86::COND_O; break; | ||||||||
| 2890 | case Intrinsic::usub_with_overflow: | ||||||||
| 2891 | BaseOpc = ISD::SUB; CondCode = X86::COND_B; break; | ||||||||
| 2892 | case Intrinsic::smul_with_overflow: | ||||||||
| 2893 | BaseOpc = X86ISD::SMUL; CondCode = X86::COND_O; break; | ||||||||
| 2894 | case Intrinsic::umul_with_overflow: | ||||||||
| 2895 | BaseOpc = X86ISD::UMUL; CondCode = X86::COND_O; break; | ||||||||
| 2896 | } | ||||||||
| 2897 | |||||||||
| 2898 | Register LHSReg = getRegForValue(LHS); | ||||||||
| 2899 | if (LHSReg == 0) | ||||||||
| 2900 | return false; | ||||||||
| 2901 | |||||||||
| 2902 | unsigned ResultReg = 0; | ||||||||
| 2903 | // Check if we have an immediate version. | ||||||||
| 2904 | if (const auto *CI = dyn_cast<ConstantInt>(RHS)) { | ||||||||
| 2905 | static const uint16_t Opc[2][4] = { | ||||||||
| 2906 | { X86::INC8r, X86::INC16r, X86::INC32r, X86::INC64r }, | ||||||||
| 2907 | { X86::DEC8r, X86::DEC16r, X86::DEC32r, X86::DEC64r } | ||||||||
| 2908 | }; | ||||||||
| 2909 | |||||||||
| 2910 | if (CI->isOne() && (BaseOpc == ISD::ADD || BaseOpc == ISD::SUB) && | ||||||||
| 2911 | CondCode == X86::COND_O) { | ||||||||
| 2912 | // We can use INC/DEC. | ||||||||
| 2913 | ResultReg = createResultReg(TLI.getRegClassFor(VT)); | ||||||||
| 2914 | bool IsDec = BaseOpc == ISD::SUB; | ||||||||
| 2915 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2916 | TII.get(Opc[IsDec][VT.SimpleTy-MVT::i8]), ResultReg) | ||||||||
| 2917 | .addReg(LHSReg); | ||||||||
| 2918 | } else | ||||||||
| 2919 | ResultReg = fastEmit_ri(VT, VT, BaseOpc, LHSReg, CI->getZExtValue()); | ||||||||
| 2920 | } | ||||||||
| 2921 | |||||||||
| 2922 | unsigned RHSReg; | ||||||||
| 2923 | if (!ResultReg) { | ||||||||
| 2924 | RHSReg = getRegForValue(RHS); | ||||||||
| 2925 | if (RHSReg == 0) | ||||||||
| 2926 | return false; | ||||||||
| 2927 | ResultReg = fastEmit_rr(VT, VT, BaseOpc, LHSReg, RHSReg); | ||||||||
| 2928 | } | ||||||||
| 2929 | |||||||||
| 2930 | // FastISel doesn't have a pattern for all X86::MUL*r and X86::IMUL*r. Emit | ||||||||
| 2931 | // it manually. | ||||||||
| 2932 | if (BaseOpc == X86ISD::UMUL && !ResultReg) { | ||||||||
| 2933 | static const uint16_t MULOpc[] = | ||||||||
| 2934 | { X86::MUL8r, X86::MUL16r, X86::MUL32r, X86::MUL64r }; | ||||||||
| 2935 | static const MCPhysReg Reg[] = { X86::AL, X86::AX, X86::EAX, X86::RAX }; | ||||||||
| 2936 | // First copy the first operand into RAX, which is an implicit input to | ||||||||
| 2937 | // the X86::MUL*r instruction. | ||||||||
| 2938 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2939 | TII.get(TargetOpcode::COPY), Reg[VT.SimpleTy-MVT::i8]) | ||||||||
| 2940 | .addReg(LHSReg); | ||||||||
| 2941 | ResultReg = fastEmitInst_r(MULOpc[VT.SimpleTy-MVT::i8], | ||||||||
| 2942 | TLI.getRegClassFor(VT), RHSReg); | ||||||||
| 2943 | } else if (BaseOpc == X86ISD::SMUL && !ResultReg) { | ||||||||
| 2944 | static const uint16_t MULOpc[] = | ||||||||
| 2945 | { X86::IMUL8r, X86::IMUL16rr, X86::IMUL32rr, X86::IMUL64rr }; | ||||||||
| 2946 | if (VT == MVT::i8) { | ||||||||
| 2947 | // Copy the first operand into AL, which is an implicit input to the | ||||||||
| 2948 | // X86::IMUL8r instruction. | ||||||||
| 2949 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 2950 | TII.get(TargetOpcode::COPY), X86::AL) | ||||||||
| 2951 | .addReg(LHSReg); | ||||||||
| 2952 | ResultReg = fastEmitInst_r(MULOpc[0], TLI.getRegClassFor(VT), RHSReg); | ||||||||
| 2953 | } else | ||||||||
| 2954 | ResultReg = fastEmitInst_rr(MULOpc[VT.SimpleTy-MVT::i8], | ||||||||
| 2955 | TLI.getRegClassFor(VT), LHSReg, RHSReg); | ||||||||
| 2956 | } | ||||||||
| 2957 | |||||||||
| 2958 | if (!ResultReg) | ||||||||
| 2959 | return false; | ||||||||
| 2960 | |||||||||
| 2961 | // Assign to a GPR since the overflow return value is lowered to a SETcc. | ||||||||
| 2962 | Register ResultReg2 = createResultReg(&X86::GR8RegClass); | ||||||||
| 2963 | assert((ResultReg+1) == ResultReg2 && "Nonconsecutive result registers.")((void)0); | ||||||||
| 2964 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr), | ||||||||
| 2965 | ResultReg2).addImm(CondCode); | ||||||||
| 2966 | |||||||||
| 2967 | updateValueMap(II, ResultReg, 2); | ||||||||
| 2968 | return true; | ||||||||
| 2969 | } | ||||||||
| 2970 | case Intrinsic::x86_sse_cvttss2si: | ||||||||
| 2971 | case Intrinsic::x86_sse_cvttss2si64: | ||||||||
| 2972 | case Intrinsic::x86_sse2_cvttsd2si: | ||||||||
| 2973 | case Intrinsic::x86_sse2_cvttsd2si64: { | ||||||||
| 2974 | bool IsInputDouble; | ||||||||
| 2975 | switch (II->getIntrinsicID()) { | ||||||||
| 2976 | default: llvm_unreachable("Unexpected intrinsic.")__builtin_unreachable(); | ||||||||
| 2977 | case Intrinsic::x86_sse_cvttss2si: | ||||||||
| 2978 | case Intrinsic::x86_sse_cvttss2si64: | ||||||||
| 2979 | if (!Subtarget->hasSSE1()) | ||||||||
| 2980 | return false; | ||||||||
| 2981 | IsInputDouble = false; | ||||||||
| 2982 | break; | ||||||||
| 2983 | case Intrinsic::x86_sse2_cvttsd2si: | ||||||||
| 2984 | case Intrinsic::x86_sse2_cvttsd2si64: | ||||||||
| 2985 | if (!Subtarget->hasSSE2()) | ||||||||
| 2986 | return false; | ||||||||
| 2987 | IsInputDouble = true; | ||||||||
| 2988 | break; | ||||||||
| 2989 | } | ||||||||
| 2990 | |||||||||
| 2991 | Type *RetTy = II->getCalledFunction()->getReturnType(); | ||||||||
| 2992 | MVT VT; | ||||||||
| 2993 | if (!isTypeLegal(RetTy, VT)) | ||||||||
| 2994 | return false; | ||||||||
| 2995 | |||||||||
| 2996 | static const uint16_t CvtOpc[3][2][2] = { | ||||||||
| 2997 | { { X86::CVTTSS2SIrr, X86::CVTTSS2SI64rr }, | ||||||||
| 2998 | { X86::CVTTSD2SIrr, X86::CVTTSD2SI64rr } }, | ||||||||
| 2999 | { { X86::VCVTTSS2SIrr, X86::VCVTTSS2SI64rr }, | ||||||||
| 3000 | { X86::VCVTTSD2SIrr, X86::VCVTTSD2SI64rr } }, | ||||||||
| 3001 | { { X86::VCVTTSS2SIZrr, X86::VCVTTSS2SI64Zrr }, | ||||||||
| 3002 | { X86::VCVTTSD2SIZrr, X86::VCVTTSD2SI64Zrr } }, | ||||||||
| 3003 | }; | ||||||||
| 3004 | unsigned AVXLevel = Subtarget->hasAVX512() ? 2 : | ||||||||
| 3005 | Subtarget->hasAVX() ? 1 : | ||||||||
| 3006 | 0; | ||||||||
| 3007 | unsigned Opc; | ||||||||
| 3008 | switch (VT.SimpleTy) { | ||||||||
| 3009 | default: llvm_unreachable("Unexpected result type.")__builtin_unreachable(); | ||||||||
| 3010 | case MVT::i32: Opc = CvtOpc[AVXLevel][IsInputDouble][0]; break; | ||||||||
| 3011 | case MVT::i64: Opc = CvtOpc[AVXLevel][IsInputDouble][1]; break; | ||||||||
| 3012 | } | ||||||||
| 3013 | |||||||||
| 3014 | // Check if we can fold insertelement instructions into the convert. | ||||||||
| 3015 | const Value *Op = II->getArgOperand(0); | ||||||||
| 3016 | while (auto *IE = dyn_cast<InsertElementInst>(Op)) { | ||||||||
| 3017 | const Value *Index = IE->getOperand(2); | ||||||||
| 3018 | if (!isa<ConstantInt>(Index)) | ||||||||
| 3019 | break; | ||||||||
| 3020 | unsigned Idx = cast<ConstantInt>(Index)->getZExtValue(); | ||||||||
| 3021 | |||||||||
| 3022 | if (Idx == 0) { | ||||||||
| 3023 | Op = IE->getOperand(1); | ||||||||
| 3024 | break; | ||||||||
| 3025 | } | ||||||||
| 3026 | Op = IE->getOperand(0); | ||||||||
| 3027 | } | ||||||||
| 3028 | |||||||||
| 3029 | Register Reg = getRegForValue(Op); | ||||||||
| 3030 | if (Reg == 0) | ||||||||
| 3031 | return false; | ||||||||
| 3032 | |||||||||
| 3033 | Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); | ||||||||
| 3034 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) | ||||||||
| 3035 | .addReg(Reg); | ||||||||
| 3036 | |||||||||
| 3037 | updateValueMap(II, ResultReg); | ||||||||
| 3038 | return true; | ||||||||
| 3039 | } | ||||||||
| 3040 | } | ||||||||
| 3041 | } | ||||||||
| 3042 | |||||||||
| 3043 | bool X86FastISel::fastLowerArguments() { | ||||||||
| 3044 | if (!FuncInfo.CanLowerReturn) | ||||||||
| 3045 | return false; | ||||||||
| 3046 | |||||||||
| 3047 | const Function *F = FuncInfo.Fn; | ||||||||
| 3048 | if (F->isVarArg()) | ||||||||
| 3049 | return false; | ||||||||
| 3050 | |||||||||
| 3051 | CallingConv::ID CC = F->getCallingConv(); | ||||||||
| 3052 | if (CC != CallingConv::C) | ||||||||
| 3053 | return false; | ||||||||
| 3054 | |||||||||
| 3055 | if (Subtarget->isCallingConvWin64(CC)) | ||||||||
| 3056 | return false; | ||||||||
| 3057 | |||||||||
| 3058 | if (!Subtarget->is64Bit()) | ||||||||
| 3059 | return false; | ||||||||
| 3060 | |||||||||
| 3061 | if (Subtarget->useSoftFloat()) | ||||||||
| 3062 | return false; | ||||||||
| 3063 | |||||||||
| 3064 | // Only handle simple cases. i.e. Up to 6 i32/i64 scalar arguments. | ||||||||
| 3065 | unsigned GPRCnt = 0; | ||||||||
| 3066 | unsigned FPRCnt = 0; | ||||||||
| 3067 | for (auto const &Arg : F->args()) { | ||||||||
| 3068 | if (Arg.hasAttribute(Attribute::ByVal) || | ||||||||
| 3069 | Arg.hasAttribute(Attribute::InReg) || | ||||||||
| 3070 | Arg.hasAttribute(Attribute::StructRet) || | ||||||||
| 3071 | Arg.hasAttribute(Attribute::SwiftSelf) || | ||||||||
| 3072 | Arg.hasAttribute(Attribute::SwiftAsync) || | ||||||||
| 3073 | Arg.hasAttribute(Attribute::SwiftError) || | ||||||||
| 3074 | Arg.hasAttribute(Attribute::Nest)) | ||||||||
| 3075 | return false; | ||||||||
| 3076 | |||||||||
| 3077 | Type *ArgTy = Arg.getType(); | ||||||||
| 3078 | if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) | ||||||||
| 3079 | return false; | ||||||||
| 3080 | |||||||||
| 3081 | EVT ArgVT = TLI.getValueType(DL, ArgTy); | ||||||||
| 3082 | if (!ArgVT.isSimple()) return false; | ||||||||
| 3083 | switch (ArgVT.getSimpleVT().SimpleTy) { | ||||||||
| 3084 | default: return false; | ||||||||
| 3085 | case MVT::i32: | ||||||||
| 3086 | case MVT::i64: | ||||||||
| 3087 | ++GPRCnt; | ||||||||
| 3088 | break; | ||||||||
| 3089 | case MVT::f32: | ||||||||
| 3090 | case MVT::f64: | ||||||||
| 3091 | if (!Subtarget->hasSSE1()) | ||||||||
| 3092 | return false; | ||||||||
| 3093 | ++FPRCnt; | ||||||||
| 3094 | break; | ||||||||
| 3095 | } | ||||||||
| 3096 | |||||||||
| 3097 | if (GPRCnt > 6) | ||||||||
| 3098 | return false; | ||||||||
| 3099 | |||||||||
| 3100 | if (FPRCnt > 8) | ||||||||
| 3101 | return false; | ||||||||
| 3102 | } | ||||||||
| 3103 | |||||||||
| 3104 | static const MCPhysReg GPR32ArgRegs[] = { | ||||||||
| 3105 | X86::EDI, X86::ESI, X86::EDX, X86::ECX, X86::R8D, X86::R9D | ||||||||
| 3106 | }; | ||||||||
| 3107 | static const MCPhysReg GPR64ArgRegs[] = { | ||||||||
| 3108 | X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8 , X86::R9 | ||||||||
| 3109 | }; | ||||||||
| 3110 | static const MCPhysReg XMMArgRegs[] = { | ||||||||
| 3111 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, | ||||||||
| 3112 | X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 | ||||||||
| 3113 | }; | ||||||||
| 3114 | |||||||||
| 3115 | unsigned GPRIdx = 0; | ||||||||
| 3116 | unsigned FPRIdx = 0; | ||||||||
| 3117 | for (auto const &Arg : F->args()) { | ||||||||
| 3118 | MVT VT = TLI.getSimpleValueType(DL, Arg.getType()); | ||||||||
| 3119 | const TargetRegisterClass *RC = TLI.getRegClassFor(VT); | ||||||||
| 3120 | unsigned SrcReg; | ||||||||
| 3121 | switch (VT.SimpleTy) { | ||||||||
| 3122 | default: llvm_unreachable("Unexpected value type.")__builtin_unreachable(); | ||||||||
| 3123 | case MVT::i32: SrcReg = GPR32ArgRegs[GPRIdx++]; break; | ||||||||
| 3124 | case MVT::i64: SrcReg = GPR64ArgRegs[GPRIdx++]; break; | ||||||||
| 3125 | case MVT::f32: LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||
| 3126 | case MVT::f64: SrcReg = XMMArgRegs[FPRIdx++]; break; | ||||||||
| 3127 | } | ||||||||
| 3128 | Register DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC); | ||||||||
| 3129 | // FIXME: Unfortunately it's necessary to emit a copy from the livein copy. | ||||||||
| 3130 | // Without this, EmitLiveInCopies may eliminate the livein if its only | ||||||||
| 3131 | // use is a bitcast (which isn't turned into an instruction). | ||||||||
| 3132 | Register ResultReg = createResultReg(RC); | ||||||||
| 3133 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 3134 | TII.get(TargetOpcode::COPY), ResultReg) | ||||||||
| 3135 | .addReg(DstReg, getKillRegState(true)); | ||||||||
| 3136 | updateValueMap(&Arg, ResultReg); | ||||||||
| 3137 | } | ||||||||
| 3138 | return true; | ||||||||
| 3139 | } | ||||||||
| 3140 | |||||||||
| 3141 | static unsigned computeBytesPoppedByCalleeForSRet(const X86Subtarget *Subtarget, | ||||||||
| 3142 | CallingConv::ID CC, | ||||||||
| 3143 | const CallBase *CB) { | ||||||||
| 3144 | if (Subtarget->is64Bit()) | ||||||||
| 3145 | return 0; | ||||||||
| 3146 | if (Subtarget->getTargetTriple().isOSMSVCRT()) | ||||||||
| 3147 | return 0; | ||||||||
| 3148 | if (CC == CallingConv::Fast || CC == CallingConv::GHC || | ||||||||
| 3149 | CC == CallingConv::HiPE || CC == CallingConv::Tail || | ||||||||
| 3150 | CC == CallingConv::SwiftTail) | ||||||||
| 3151 | return 0; | ||||||||
| 3152 | |||||||||
| 3153 | if (CB) | ||||||||
| 3154 | if (CB->arg_empty() || !CB->paramHasAttr(0, Attribute::StructRet) || | ||||||||
| 3155 | CB->paramHasAttr(0, Attribute::InReg) || Subtarget->isTargetMCU()) | ||||||||
| 3156 | return 0; | ||||||||
| 3157 | |||||||||
| 3158 | return 4; | ||||||||
| 3159 | } | ||||||||
| 3160 | |||||||||
| 3161 | bool X86FastISel::fastLowerCall(CallLoweringInfo &CLI) { | ||||||||
| 3162 | auto &OutVals = CLI.OutVals; | ||||||||
| 3163 | auto &OutFlags = CLI.OutFlags; | ||||||||
| 3164 | auto &OutRegs = CLI.OutRegs; | ||||||||
| 3165 | auto &Ins = CLI.Ins; | ||||||||
| 3166 | auto &InRegs = CLI.InRegs; | ||||||||
| 3167 | CallingConv::ID CC = CLI.CallConv; | ||||||||
| 3168 | bool &IsTailCall = CLI.IsTailCall; | ||||||||
| 3169 | bool IsVarArg = CLI.IsVarArg; | ||||||||
| 3170 | const Value *Callee = CLI.Callee; | ||||||||
| 3171 | MCSymbol *Symbol = CLI.Symbol; | ||||||||
| 3172 | const auto *CB = CLI.CB; | ||||||||
| 3173 | |||||||||
| 3174 | bool Is64Bit = Subtarget->is64Bit(); | ||||||||
| 3175 | bool IsWin64 = Subtarget->isCallingConvWin64(CC); | ||||||||
| 3176 | |||||||||
| 3177 | // Call / invoke instructions with NoCfCheck attribute require special | ||||||||
| 3178 | // handling. | ||||||||
| 3179 | if (CB && CB->doesNoCfCheck()) | ||||||||
| 3180 | return false; | ||||||||
| 3181 | |||||||||
| 3182 | // Functions with no_caller_saved_registers that need special handling. | ||||||||
| 3183 | if ((CB && isa<CallInst>(CB) && CB->hasFnAttr("no_caller_saved_registers"))) | ||||||||
| 3184 | return false; | ||||||||
| 3185 | |||||||||
| 3186 | // Functions with no_callee_saved_registers that need special handling. | ||||||||
| 3187 | if ((CB && CB->hasFnAttr("no_callee_saved_registers"))) | ||||||||
| 3188 | return false; | ||||||||
| 3189 | |||||||||
| 3190 | // Functions using thunks for indirect calls need to use SDISel. | ||||||||
| 3191 | if (Subtarget->useIndirectThunkCalls()) | ||||||||
| 3192 | return false; | ||||||||
| 3193 | |||||||||
| 3194 | // Handle only C, fastcc, and webkit_js calling conventions for now. | ||||||||
| 3195 | switch (CC) { | ||||||||
| 3196 | default: return false; | ||||||||
| 3197 | case CallingConv::C: | ||||||||
| 3198 | case CallingConv::Fast: | ||||||||
| 3199 | case CallingConv::Tail: | ||||||||
| 3200 | case CallingConv::WebKit_JS: | ||||||||
| 3201 | case CallingConv::Swift: | ||||||||
| 3202 | case CallingConv::SwiftTail: | ||||||||
| 3203 | case CallingConv::X86_FastCall: | ||||||||
| 3204 | case CallingConv::X86_StdCall: | ||||||||
| 3205 | case CallingConv::X86_ThisCall: | ||||||||
| 3206 | case CallingConv::Win64: | ||||||||
| 3207 | case CallingConv::X86_64_SysV: | ||||||||
| 3208 | case CallingConv::CFGuard_Check: | ||||||||
| 3209 | break; | ||||||||
| 3210 | } | ||||||||
| 3211 | |||||||||
| 3212 | // Allow SelectionDAG isel to handle tail calls. | ||||||||
| 3213 | if (IsTailCall) | ||||||||
| 3214 | return false; | ||||||||
| 3215 | |||||||||
| 3216 | // fastcc with -tailcallopt is intended to provide a guaranteed | ||||||||
| 3217 | // tail call optimization. Fastisel doesn't know how to do that. | ||||||||
| 3218 | if ((CC == CallingConv::Fast && TM.Options.GuaranteedTailCallOpt) || | ||||||||
| 3219 | CC == CallingConv::Tail || CC == CallingConv::SwiftTail) | ||||||||
| 3220 | return false; | ||||||||
| 3221 | |||||||||
| 3222 | // Don't know how to handle Win64 varargs yet. Nothing special needed for | ||||||||
| 3223 | // x86-32. Special handling for x86-64 is implemented. | ||||||||
| 3224 | if (IsVarArg && IsWin64) | ||||||||
| 3225 | return false; | ||||||||
| 3226 | |||||||||
| 3227 | // Don't know about inalloca yet. | ||||||||
| 3228 | if (CLI.CB && CLI.CB->hasInAllocaArgument()) | ||||||||
| 3229 | return false; | ||||||||
| 3230 | |||||||||
| 3231 | for (auto Flag : CLI.OutFlags) | ||||||||
| 3232 | if (Flag.isSwiftError() || Flag.isPreallocated()) | ||||||||
| 3233 | return false; | ||||||||
| 3234 | |||||||||
| 3235 | SmallVector<MVT, 16> OutVTs; | ||||||||
| 3236 | SmallVector<unsigned, 16> ArgRegs; | ||||||||
| 3237 | |||||||||
| 3238 | // If this is a constant i1/i8/i16 argument, promote to i32 to avoid an extra | ||||||||
| 3239 | // instruction. This is safe because it is common to all FastISel supported | ||||||||
| 3240 | // calling conventions on x86. | ||||||||
| 3241 | for (int i = 0, e = OutVals.size(); i != e; ++i) { | ||||||||
| 3242 | Value *&Val = OutVals[i]; | ||||||||
| 3243 | ISD::ArgFlagsTy Flags = OutFlags[i]; | ||||||||
| 3244 | if (auto *CI = dyn_cast<ConstantInt>(Val)) { | ||||||||
| 3245 | if (CI->getBitWidth() < 32) { | ||||||||
| 3246 | if (Flags.isSExt()) | ||||||||
| 3247 | Val = ConstantExpr::getSExt(CI, Type::getInt32Ty(CI->getContext())); | ||||||||
| 3248 | else | ||||||||
| 3249 | Val = ConstantExpr::getZExt(CI, Type::getInt32Ty(CI->getContext())); | ||||||||
| 3250 | } | ||||||||
| 3251 | } | ||||||||
| 3252 | |||||||||
| 3253 | // Passing bools around ends up doing a trunc to i1 and passing it. | ||||||||
| 3254 | // Codegen this as an argument + "and 1". | ||||||||
| 3255 | MVT VT; | ||||||||
| 3256 | auto *TI = dyn_cast<TruncInst>(Val); | ||||||||
| 3257 | unsigned ResultReg; | ||||||||
| 3258 | if (TI && TI->getType()->isIntegerTy(1) && CLI.CB && | ||||||||
| 3259 | (TI->getParent() == CLI.CB->getParent()) && TI->hasOneUse()) { | ||||||||
| 3260 | Value *PrevVal = TI->getOperand(0); | ||||||||
| 3261 | ResultReg = getRegForValue(PrevVal); | ||||||||
| 3262 | |||||||||
| 3263 | if (!ResultReg) | ||||||||
| 3264 | return false; | ||||||||
| 3265 | |||||||||
| 3266 | if (!isTypeLegal(PrevVal->getType(), VT)) | ||||||||
| 3267 | return false; | ||||||||
| 3268 | |||||||||
| 3269 | ResultReg = fastEmit_ri(VT, VT, ISD::AND, ResultReg, 1); | ||||||||
| 3270 | } else { | ||||||||
| 3271 | if (!isTypeLegal(Val->getType(), VT) || | ||||||||
| 3272 | (VT.isVector() && VT.getVectorElementType() == MVT::i1)) | ||||||||
| 3273 | return false; | ||||||||
| 3274 | ResultReg = getRegForValue(Val); | ||||||||
| 3275 | } | ||||||||
| 3276 | |||||||||
| 3277 | if (!ResultReg) | ||||||||
| 3278 | return false; | ||||||||
| 3279 | |||||||||
| 3280 | ArgRegs.push_back(ResultReg); | ||||||||
| 3281 | OutVTs.push_back(VT); | ||||||||
| 3282 | } | ||||||||
| 3283 | |||||||||
| 3284 | // Analyze operands of the call, assigning locations to each operand. | ||||||||
| 3285 | SmallVector<CCValAssign, 16> ArgLocs; | ||||||||
| 3286 | CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, CLI.RetTy->getContext()); | ||||||||
| 3287 | |||||||||
| 3288 | // Allocate shadow area for Win64 | ||||||||
| 3289 | if (IsWin64) | ||||||||
| 3290 | CCInfo.AllocateStack(32, Align(8)); | ||||||||
| 3291 | |||||||||
| 3292 | CCInfo.AnalyzeCallOperands(OutVTs, OutFlags, CC_X86); | ||||||||
| 3293 | |||||||||
| 3294 | // Get a count of how many bytes are to be pushed on the stack. | ||||||||
| 3295 | unsigned NumBytes = CCInfo.getAlignedCallFrameSize(); | ||||||||
| 3296 | |||||||||
| 3297 | // Issue CALLSEQ_START | ||||||||
| 3298 | unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); | ||||||||
| 3299 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackDown)) | ||||||||
| 3300 | .addImm(NumBytes).addImm(0).addImm(0); | ||||||||
| 3301 | |||||||||
| 3302 | // Walk the register/memloc assignments, inserting copies/loads. | ||||||||
| 3303 | const X86RegisterInfo *RegInfo = Subtarget->getRegisterInfo(); | ||||||||
| 3304 | for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { | ||||||||
| 3305 | CCValAssign const &VA = ArgLocs[i]; | ||||||||
| 3306 | const Value *ArgVal = OutVals[VA.getValNo()]; | ||||||||
| 3307 | MVT ArgVT = OutVTs[VA.getValNo()]; | ||||||||
| 3308 | |||||||||
| 3309 | if (ArgVT == MVT::x86mmx) | ||||||||
| 3310 | return false; | ||||||||
| 3311 | |||||||||
| 3312 | unsigned ArgReg = ArgRegs[VA.getValNo()]; | ||||||||
| 3313 | |||||||||
| 3314 | // Promote the value if needed. | ||||||||
| 3315 | switch (VA.getLocInfo()) { | ||||||||
| 3316 | case CCValAssign::Full: break; | ||||||||
| 3317 | case CCValAssign::SExt: { | ||||||||
| 3318 | assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&((void)0) | ||||||||
| 3319 | "Unexpected extend")((void)0); | ||||||||
| 3320 | |||||||||
| 3321 | if (ArgVT == MVT::i1) | ||||||||
| 3322 | return false; | ||||||||
| 3323 | |||||||||
| 3324 | bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, | ||||||||
| 3325 | ArgVT, ArgReg); | ||||||||
| 3326 | assert(Emitted && "Failed to emit a sext!")((void)0); (void)Emitted; | ||||||||
| 3327 | ArgVT = VA.getLocVT(); | ||||||||
| 3328 | break; | ||||||||
| 3329 | } | ||||||||
| 3330 | case CCValAssign::ZExt: { | ||||||||
| 3331 | assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&((void)0) | ||||||||
| 3332 | "Unexpected extend")((void)0); | ||||||||
| 3333 | |||||||||
| 3334 | // Handle zero-extension from i1 to i8, which is common. | ||||||||
| 3335 | if (ArgVT == MVT::i1) { | ||||||||
| 3336 | // Set the high bits to zero. | ||||||||
| 3337 | ArgReg = fastEmitZExtFromI1(MVT::i8, ArgReg); | ||||||||
| 3338 | ArgVT = MVT::i8; | ||||||||
| 3339 | |||||||||
| 3340 | if (ArgReg == 0) | ||||||||
| 3341 | return false; | ||||||||
| 3342 | } | ||||||||
| 3343 | |||||||||
| 3344 | bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, | ||||||||
| 3345 | ArgVT, ArgReg); | ||||||||
| 3346 | assert(Emitted && "Failed to emit a zext!")((void)0); (void)Emitted; | ||||||||
| 3347 | ArgVT = VA.getLocVT(); | ||||||||
| 3348 | break; | ||||||||
| 3349 | } | ||||||||
| 3350 | case CCValAssign::AExt: { | ||||||||
| 3351 | assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() &&((void)0) | ||||||||
| 3352 | "Unexpected extend")((void)0); | ||||||||
| 3353 | bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), ArgReg, | ||||||||
| 3354 | ArgVT, ArgReg); | ||||||||
| 3355 | if (!Emitted) | ||||||||
| 3356 | Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, | ||||||||
| 3357 | ArgVT, ArgReg); | ||||||||
| 3358 | if (!Emitted) | ||||||||
| 3359 | Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, | ||||||||
| 3360 | ArgVT, ArgReg); | ||||||||
| 3361 | |||||||||
| 3362 | assert(Emitted && "Failed to emit a aext!")((void)0); (void)Emitted; | ||||||||
| 3363 | ArgVT = VA.getLocVT(); | ||||||||
| 3364 | break; | ||||||||
| 3365 | } | ||||||||
| 3366 | case CCValAssign::BCvt: { | ||||||||
| 3367 | ArgReg = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, ArgReg); | ||||||||
| 3368 | assert(ArgReg && "Failed to emit a bitcast!")((void)0); | ||||||||
| 3369 | ArgVT = VA.getLocVT(); | ||||||||
| 3370 | break; | ||||||||
| 3371 | } | ||||||||
| 3372 | case CCValAssign::VExt: | ||||||||
| 3373 | // VExt has not been implemented, so this should be impossible to reach | ||||||||
| 3374 | // for now. However, fallback to Selection DAG isel once implemented. | ||||||||
| 3375 | return false; | ||||||||
| 3376 | case CCValAssign::AExtUpper: | ||||||||
| 3377 | case CCValAssign::SExtUpper: | ||||||||
| 3378 | case CCValAssign::ZExtUpper: | ||||||||
| 3379 | case CCValAssign::FPExt: | ||||||||
| 3380 | case CCValAssign::Trunc: | ||||||||
| 3381 | llvm_unreachable("Unexpected loc info!")__builtin_unreachable(); | ||||||||
| 3382 | case CCValAssign::Indirect: | ||||||||
| 3383 | // FIXME: Indirect doesn't need extending, but fast-isel doesn't fully | ||||||||
| 3384 | // support this. | ||||||||
| 3385 | return false; | ||||||||
| 3386 | } | ||||||||
| 3387 | |||||||||
| 3388 | if (VA.isRegLoc()) { | ||||||||
| 3389 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 3390 | TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg); | ||||||||
| 3391 | OutRegs.push_back(VA.getLocReg()); | ||||||||
| 3392 | } else { | ||||||||
| 3393 | assert(VA.isMemLoc() && "Unknown value location!")((void)0); | ||||||||
| 3394 | |||||||||
| 3395 | // Don't emit stores for undef values. | ||||||||
| 3396 | if (isa<UndefValue>(ArgVal)) | ||||||||
| 3397 | continue; | ||||||||
| 3398 | |||||||||
| 3399 | unsigned LocMemOffset = VA.getLocMemOffset(); | ||||||||
| 3400 | X86AddressMode AM; | ||||||||
| 3401 | AM.Base.Reg = RegInfo->getStackRegister(); | ||||||||
| 3402 | AM.Disp = LocMemOffset; | ||||||||
| 3403 | ISD::ArgFlagsTy Flags = OutFlags[VA.getValNo()]; | ||||||||
| 3404 | Align Alignment = DL.getABITypeAlign(ArgVal->getType()); | ||||||||
| 3405 | MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand( | ||||||||
| 3406 | MachinePointerInfo::getStack(*FuncInfo.MF, LocMemOffset), | ||||||||
| 3407 | MachineMemOperand::MOStore, ArgVT.getStoreSize(), Alignment); | ||||||||
| 3408 | if (Flags.isByVal()) { | ||||||||
| 3409 | X86AddressMode SrcAM; | ||||||||
| 3410 | SrcAM.Base.Reg = ArgReg; | ||||||||
| 3411 | if (!TryEmitSmallMemcpy(AM, SrcAM, Flags.getByValSize())) | ||||||||
| 3412 | return false; | ||||||||
| 3413 | } else if (isa<ConstantInt>(ArgVal) || isa<ConstantPointerNull>(ArgVal)) { | ||||||||
| 3414 | // If this is a really simple value, emit this with the Value* version | ||||||||
| 3415 | // of X86FastEmitStore. If it isn't simple, we don't want to do this, | ||||||||
| 3416 | // as it can cause us to reevaluate the argument. | ||||||||
| 3417 | if (!X86FastEmitStore(ArgVT, ArgVal, AM, MMO)) | ||||||||
| 3418 | return false; | ||||||||
| 3419 | } else { | ||||||||
| 3420 | if (!X86FastEmitStore(ArgVT, ArgReg, AM, MMO)) | ||||||||
| 3421 | return false; | ||||||||
| 3422 | } | ||||||||
| 3423 | } | ||||||||
| 3424 | } | ||||||||
| 3425 | |||||||||
| 3426 | // ELF / PIC requires GOT in the EBX register before function calls via PLT | ||||||||
| 3427 | // GOT pointer. | ||||||||
| 3428 | if (Subtarget->isPICStyleGOT()) { | ||||||||
| 3429 | unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF); | ||||||||
| 3430 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 3431 | TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base); | ||||||||
| 3432 | } | ||||||||
| 3433 | |||||||||
| 3434 | if (Is64Bit && IsVarArg && !IsWin64) { | ||||||||
| 3435 | // From AMD64 ABI document: | ||||||||
| 3436 | // For calls that may call functions that use varargs or stdargs | ||||||||
| 3437 | // (prototype-less calls or calls to functions containing ellipsis (...) in | ||||||||
| 3438 | // the declaration) %al is used as hidden argument to specify the number | ||||||||
| 3439 | // of SSE registers used. The contents of %al do not need to match exactly | ||||||||
| 3440 | // the number of registers, but must be an ubound on the number of SSE | ||||||||
| 3441 | // registers used and is in the range 0 - 8 inclusive. | ||||||||
| 3442 | |||||||||
| 3443 | // Count the number of XMM registers allocated. | ||||||||
| 3444 | static const MCPhysReg XMMArgRegs[] = { | ||||||||
| 3445 | X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, | ||||||||
| 3446 | X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 | ||||||||
| 3447 | }; | ||||||||
| 3448 | unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs); | ||||||||
| 3449 | assert((Subtarget->hasSSE1() || !NumXMMRegs)((void)0) | ||||||||
| 3450 | && "SSE registers cannot be used when SSE is disabled")((void)0); | ||||||||
| 3451 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri), | ||||||||
| 3452 | X86::AL).addImm(NumXMMRegs); | ||||||||
| 3453 | } | ||||||||
| 3454 | |||||||||
| 3455 | // Materialize callee address in a register. FIXME: GV address can be | ||||||||
| 3456 | // handled with a CALLpcrel32 instead. | ||||||||
| 3457 | X86AddressMode CalleeAM; | ||||||||
| 3458 | if (!X86SelectCallAddress(Callee, CalleeAM)) | ||||||||
| 3459 | return false; | ||||||||
| 3460 | |||||||||
| 3461 | unsigned CalleeOp = 0; | ||||||||
| 3462 | const GlobalValue *GV = nullptr; | ||||||||
| 3463 | if (CalleeAM.GV != nullptr) { | ||||||||
| 3464 | GV = CalleeAM.GV; | ||||||||
| 3465 | } else if (CalleeAM.Base.Reg != 0) { | ||||||||
| 3466 | CalleeOp = CalleeAM.Base.Reg; | ||||||||
| 3467 | } else | ||||||||
| 3468 | return false; | ||||||||
| 3469 | |||||||||
| 3470 | // Issue the call. | ||||||||
| 3471 | MachineInstrBuilder MIB; | ||||||||
| 3472 | if (CalleeOp) { | ||||||||
| 3473 | // Register-indirect call. | ||||||||
| 3474 | unsigned CallOpc = Is64Bit ? X86::CALL64r : X86::CALL32r; | ||||||||
| 3475 | MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc)) | ||||||||
| 3476 | .addReg(CalleeOp); | ||||||||
| 3477 | } else { | ||||||||
| 3478 | // Direct call. | ||||||||
| 3479 | assert(GV && "Not a direct call")((void)0); | ||||||||
| 3480 | // See if we need any target-specific flags on the GV operand. | ||||||||
| 3481 | unsigned char OpFlags = Subtarget->classifyGlobalFunctionReference(GV); | ||||||||
| 3482 | |||||||||
| 3483 | // This will be a direct call, or an indirect call through memory for | ||||||||
| 3484 | // NonLazyBind calls or dllimport calls. | ||||||||
| 3485 | bool NeedLoad = OpFlags == X86II::MO_DLLIMPORT || | ||||||||
| 3486 | OpFlags == X86II::MO_GOTPCREL || | ||||||||
| 3487 | OpFlags == X86II::MO_COFFSTUB; | ||||||||
| 3488 | unsigned CallOpc = NeedLoad | ||||||||
| 3489 | ? (Is64Bit ? X86::CALL64m : X86::CALL32m) | ||||||||
| 3490 | : (Is64Bit ? X86::CALL64pcrel32 : X86::CALLpcrel32); | ||||||||
| 3491 | |||||||||
| 3492 | MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc)); | ||||||||
| 3493 | if (NeedLoad) | ||||||||
| 3494 | MIB.addReg(Is64Bit ? X86::RIP : 0).addImm(1).addReg(0); | ||||||||
| 3495 | if (Symbol) | ||||||||
| 3496 | MIB.addSym(Symbol, OpFlags); | ||||||||
| 3497 | else | ||||||||
| 3498 | MIB.addGlobalAddress(GV, 0, OpFlags); | ||||||||
| 3499 | if (NeedLoad) | ||||||||
| 3500 | MIB.addReg(0); | ||||||||
| 3501 | } | ||||||||
| 3502 | |||||||||
| 3503 | // Add a register mask operand representing the call-preserved registers. | ||||||||
| 3504 | // Proper defs for return values will be added by setPhysRegsDeadExcept(). | ||||||||
| 3505 | MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC)); | ||||||||
| 3506 | |||||||||
| 3507 | // Add an implicit use GOT pointer in EBX. | ||||||||
| 3508 | if (Subtarget->isPICStyleGOT()) | ||||||||
| 3509 | MIB.addReg(X86::EBX, RegState::Implicit); | ||||||||
| 3510 | |||||||||
| 3511 | if (Is64Bit && IsVarArg && !IsWin64) | ||||||||
| 3512 | MIB.addReg(X86::AL, RegState::Implicit); | ||||||||
| 3513 | |||||||||
| 3514 | // Add implicit physical register uses to the call. | ||||||||
| 3515 | for (auto Reg : OutRegs) | ||||||||
| 3516 | MIB.addReg(Reg, RegState::Implicit); | ||||||||
| 3517 | |||||||||
| 3518 | // Issue CALLSEQ_END | ||||||||
| 3519 | unsigned NumBytesForCalleeToPop = | ||||||||
| 3520 | X86::isCalleePop(CC, Subtarget->is64Bit(), IsVarArg, | ||||||||
| 3521 | TM.Options.GuaranteedTailCallOpt) | ||||||||
| 3522 | ? NumBytes // Callee pops everything. | ||||||||
| 3523 | : computeBytesPoppedByCalleeForSRet(Subtarget, CC, CLI.CB); | ||||||||
| 3524 | unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); | ||||||||
| 3525 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AdjStackUp)) | ||||||||
| 3526 | .addImm(NumBytes).addImm(NumBytesForCalleeToPop); | ||||||||
| 3527 | |||||||||
| 3528 | // Now handle call return values. | ||||||||
| 3529 | SmallVector<CCValAssign, 16> RVLocs; | ||||||||
| 3530 | CCState CCRetInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, | ||||||||
| 3531 | CLI.RetTy->getContext()); | ||||||||
| 3532 | CCRetInfo.AnalyzeCallResult(Ins, RetCC_X86); | ||||||||
| 3533 | |||||||||
| 3534 | // Copy all of the result registers out of their specified physreg. | ||||||||
| 3535 | Register ResultReg = FuncInfo.CreateRegs(CLI.RetTy); | ||||||||
| 3536 | for (unsigned i = 0; i != RVLocs.size(); ++i) { | ||||||||
| 3537 | CCValAssign &VA = RVLocs[i]; | ||||||||
| 3538 | EVT CopyVT = VA.getValVT(); | ||||||||
| 3539 | unsigned CopyReg = ResultReg + i; | ||||||||
| 3540 | Register SrcReg = VA.getLocReg(); | ||||||||
| 3541 | |||||||||
| 3542 | // If this is x86-64, and we disabled SSE, we can't return FP values | ||||||||
| 3543 | if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && | ||||||||
| 3544 | ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasSSE1())) { | ||||||||
| 3545 | report_fatal_error("SSE register return with SSE disabled"); | ||||||||
| 3546 | } | ||||||||
| 3547 | |||||||||
| 3548 | // If we prefer to use the value in xmm registers, copy it out as f80 and | ||||||||
| 3549 | // use a truncate to move it from fp stack reg to xmm reg. | ||||||||
| 3550 | if ((SrcReg == X86::FP0 || SrcReg == X86::FP1) && | ||||||||
| 3551 | isScalarFPTypeInSSEReg(VA.getValVT())) { | ||||||||
| 3552 | CopyVT = MVT::f80; | ||||||||
| 3553 | CopyReg = createResultReg(&X86::RFP80RegClass); | ||||||||
| 3554 | } | ||||||||
| 3555 | |||||||||
| 3556 | // Copy out the result. | ||||||||
| 3557 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 3558 | TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg); | ||||||||
| 3559 | InRegs.push_back(VA.getLocReg()); | ||||||||
| 3560 | |||||||||
| 3561 | // Round the f80 to the right size, which also moves it to the appropriate | ||||||||
| 3562 | // xmm register. This is accomplished by storing the f80 value in memory | ||||||||
| 3563 | // and then loading it back. | ||||||||
| 3564 | if (CopyVT != VA.getValVT()) { | ||||||||
| 3565 | EVT ResVT = VA.getValVT(); | ||||||||
| 3566 | unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64; | ||||||||
| 3567 | unsigned MemSize = ResVT.getSizeInBits()/8; | ||||||||
| 3568 | int FI = MFI.CreateStackObject(MemSize, Align(MemSize), false); | ||||||||
| 3569 | addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 3570 | TII.get(Opc)), FI) | ||||||||
| 3571 | .addReg(CopyReg); | ||||||||
| 3572 | Opc = ResVT == MVT::f32 ? X86::MOVSSrm_alt : X86::MOVSDrm_alt; | ||||||||
| 3573 | addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 3574 | TII.get(Opc), ResultReg + i), FI); | ||||||||
| 3575 | } | ||||||||
| 3576 | } | ||||||||
| 3577 | |||||||||
| 3578 | CLI.ResultReg = ResultReg; | ||||||||
| 3579 | CLI.NumResultRegs = RVLocs.size(); | ||||||||
| 3580 | CLI.Call = MIB; | ||||||||
| 3581 | |||||||||
| 3582 | return true; | ||||||||
| 3583 | } | ||||||||
| 3584 | |||||||||
| 3585 | bool | ||||||||
| 3586 | X86FastISel::fastSelectInstruction(const Instruction *I) { | ||||||||
| 3587 | switch (I->getOpcode()) { | ||||||||
| |||||||||
| 3588 | default: break; | ||||||||
| 3589 | case Instruction::Load: | ||||||||
| 3590 | return X86SelectLoad(I); | ||||||||
| 3591 | case Instruction::Store: | ||||||||
| 3592 | return X86SelectStore(I); | ||||||||
| 3593 | case Instruction::Ret: | ||||||||
| 3594 | return X86SelectRet(I); | ||||||||
| 3595 | case Instruction::ICmp: | ||||||||
| 3596 | case Instruction::FCmp: | ||||||||
| 3597 | return X86SelectCmp(I); | ||||||||
| 3598 | case Instruction::ZExt: | ||||||||
| 3599 | return X86SelectZExt(I); | ||||||||
| 3600 | case Instruction::SExt: | ||||||||
| 3601 | return X86SelectSExt(I); | ||||||||
| 3602 | case Instruction::Br: | ||||||||
| 3603 | return X86SelectBranch(I); | ||||||||
| 3604 | case Instruction::LShr: | ||||||||
| 3605 | case Instruction::AShr: | ||||||||
| 3606 | case Instruction::Shl: | ||||||||
| 3607 | return X86SelectShift(I); | ||||||||
| 3608 | case Instruction::SDiv: | ||||||||
| 3609 | case Instruction::UDiv: | ||||||||
| 3610 | case Instruction::SRem: | ||||||||
| 3611 | case Instruction::URem: | ||||||||
| 3612 | return X86SelectDivRem(I); | ||||||||
| 3613 | case Instruction::Select: | ||||||||
| 3614 | return X86SelectSelect(I); | ||||||||
| 3615 | case Instruction::Trunc: | ||||||||
| 3616 | return X86SelectTrunc(I); | ||||||||
| 3617 | case Instruction::FPExt: | ||||||||
| 3618 | return X86SelectFPExt(I); | ||||||||
| 3619 | case Instruction::FPTrunc: | ||||||||
| 3620 | return X86SelectFPTrunc(I); | ||||||||
| 3621 | case Instruction::SIToFP: | ||||||||
| 3622 | return X86SelectSIToFP(I); | ||||||||
| 3623 | case Instruction::UIToFP: | ||||||||
| 3624 | return X86SelectUIToFP(I); | ||||||||
| 3625 | case Instruction::IntToPtr: // Deliberate fall-through. | ||||||||
| 3626 | case Instruction::PtrToInt: { | ||||||||
| 3627 | EVT SrcVT = TLI.getValueType(DL, I->getOperand(0)->getType()); | ||||||||
| 3628 | EVT DstVT = TLI.getValueType(DL, I->getType()); | ||||||||
| 3629 | if (DstVT.bitsGT(SrcVT)) | ||||||||
| 3630 | return X86SelectZExt(I); | ||||||||
| 3631 | if (DstVT.bitsLT(SrcVT)) | ||||||||
| 3632 | return X86SelectTrunc(I); | ||||||||
| 3633 | Register Reg = getRegForValue(I->getOperand(0)); | ||||||||
| 3634 | if (Reg == 0) return false; | ||||||||
| 3635 | updateValueMap(I, Reg); | ||||||||
| 3636 | return true; | ||||||||
| 3637 | } | ||||||||
| 3638 | case Instruction::BitCast: { | ||||||||
| 3639 | // Select SSE2/AVX bitcasts between 128/256/512 bit vector types. | ||||||||
| 3640 | if (!Subtarget->hasSSE2()) | ||||||||
| 3641 | return false; | ||||||||
| 3642 | |||||||||
| 3643 | MVT SrcVT, DstVT; | ||||||||
| 3644 | if (!isTypeLegal(I->getOperand(0)->getType(), SrcVT) || | ||||||||
| 3645 | !isTypeLegal(I->getType(), DstVT)) | ||||||||
| 3646 | return false; | ||||||||
| 3647 | |||||||||
| 3648 | // Only allow vectors that use xmm/ymm/zmm. | ||||||||
| 3649 | if (!SrcVT.isVector() || !DstVT.isVector() || | ||||||||
| 3650 | SrcVT.getVectorElementType() == MVT::i1 || | ||||||||
| 3651 | DstVT.getVectorElementType() == MVT::i1) | ||||||||
| 3652 | return false; | ||||||||
| 3653 | |||||||||
| 3654 | Register Reg = getRegForValue(I->getOperand(0)); | ||||||||
| 3655 | if (!Reg) | ||||||||
| 3656 | return false; | ||||||||
| 3657 | |||||||||
| 3658 | // Emit a reg-reg copy so we don't propagate cached known bits information | ||||||||
| 3659 | // with the wrong VT if we fall out of fast isel after selecting this. | ||||||||
| 3660 | const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT); | ||||||||
| 3661 | Register ResultReg = createResultReg(DstClass); | ||||||||
| 3662 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 3663 | TII.get(TargetOpcode::COPY), ResultReg).addReg(Reg); | ||||||||
| 3664 | |||||||||
| 3665 | updateValueMap(I, ResultReg); | ||||||||
| 3666 | return true; | ||||||||
| 3667 | } | ||||||||
| 3668 | } | ||||||||
| 3669 | |||||||||
| 3670 | return false; | ||||||||
| 3671 | } | ||||||||
| 3672 | |||||||||
| 3673 | unsigned X86FastISel::X86MaterializeInt(const ConstantInt *CI, MVT VT) { | ||||||||
| 3674 | if (VT > MVT::i64) | ||||||||
| 3675 | return 0; | ||||||||
| 3676 | |||||||||
| 3677 | uint64_t Imm = CI->getZExtValue(); | ||||||||
| 3678 | if (Imm == 0) { | ||||||||
| 3679 | Register SrcReg = fastEmitInst_(X86::MOV32r0, &X86::GR32RegClass); | ||||||||
| 3680 | switch (VT.SimpleTy) { | ||||||||
| 3681 | default: llvm_unreachable("Unexpected value type")__builtin_unreachable(); | ||||||||
| 3682 | case MVT::i1: | ||||||||
| 3683 | case MVT::i8: | ||||||||
| 3684 | return fastEmitInst_extractsubreg(MVT::i8, SrcReg, X86::sub_8bit); | ||||||||
| 3685 | case MVT::i16: | ||||||||
| 3686 | return fastEmitInst_extractsubreg(MVT::i16, SrcReg, X86::sub_16bit); | ||||||||
| 3687 | case MVT::i32: | ||||||||
| 3688 | return SrcReg; | ||||||||
| 3689 | case MVT::i64: { | ||||||||
| 3690 | Register ResultReg = createResultReg(&X86::GR64RegClass); | ||||||||
| 3691 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 3692 | TII.get(TargetOpcode::SUBREG_TO_REG), ResultReg) | ||||||||
| 3693 | .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit); | ||||||||
| 3694 | return ResultReg; | ||||||||
| 3695 | } | ||||||||
| 3696 | } | ||||||||
| 3697 | } | ||||||||
| 3698 | |||||||||
| 3699 | unsigned Opc = 0; | ||||||||
| 3700 | switch (VT.SimpleTy) { | ||||||||
| 3701 | default: llvm_unreachable("Unexpected value type")__builtin_unreachable(); | ||||||||
| 3702 | case MVT::i1: | ||||||||
| 3703 | VT = MVT::i8; | ||||||||
| 3704 | LLVM_FALLTHROUGH[[gnu::fallthrough]]; | ||||||||
| 3705 | case MVT::i8: Opc = X86::MOV8ri; break; | ||||||||
| 3706 | case MVT::i16: Opc = X86::MOV16ri; break; | ||||||||
| 3707 | case MVT::i32: Opc = X86::MOV32ri; break; | ||||||||
| 3708 | case MVT::i64: { | ||||||||
| 3709 | if (isUInt<32>(Imm)) | ||||||||
| 3710 | Opc = X86::MOV32ri64; | ||||||||
| 3711 | else if (isInt<32>(Imm)) | ||||||||
| 3712 | Opc = X86::MOV64ri32; | ||||||||
| 3713 | else | ||||||||
| 3714 | Opc = X86::MOV64ri; | ||||||||
| 3715 | break; | ||||||||
| 3716 | } | ||||||||
| 3717 | } | ||||||||
| 3718 | return fastEmitInst_i(Opc, TLI.getRegClassFor(VT), Imm); | ||||||||
| 3719 | } | ||||||||
| 3720 | |||||||||
| 3721 | unsigned X86FastISel::X86MaterializeFP(const ConstantFP *CFP, MVT VT) { | ||||||||
| 3722 | if (CFP->isNullValue()) | ||||||||
| 3723 | return fastMaterializeFloatZero(CFP); | ||||||||
| 3724 | |||||||||
| 3725 | // Can't handle alternate code models yet. | ||||||||
| 3726 | CodeModel::Model CM = TM.getCodeModel(); | ||||||||
| 3727 | if (CM != CodeModel::Small && CM != CodeModel::Large) | ||||||||
| 3728 | return 0; | ||||||||
| 3729 | |||||||||
| 3730 | // Get opcode and regclass of the output for the given load instruction. | ||||||||
| 3731 | unsigned Opc = 0; | ||||||||
| 3732 | bool HasAVX = Subtarget->hasAVX(); | ||||||||
| 3733 | bool HasAVX512 = Subtarget->hasAVX512(); | ||||||||
| 3734 | switch (VT.SimpleTy) { | ||||||||
| 3735 | default: return 0; | ||||||||
| 3736 | case MVT::f32: | ||||||||
| 3737 | if (X86ScalarSSEf32) | ||||||||
| 3738 | Opc = HasAVX512 ? X86::VMOVSSZrm_alt : | ||||||||
| 3739 | HasAVX ? X86::VMOVSSrm_alt : | ||||||||
| 3740 | X86::MOVSSrm_alt; | ||||||||
| 3741 | else | ||||||||
| 3742 | Opc = X86::LD_Fp32m; | ||||||||
| 3743 | break; | ||||||||
| 3744 | case MVT::f64: | ||||||||
| 3745 | if (X86ScalarSSEf64) | ||||||||
| 3746 | Opc = HasAVX512 ? X86::VMOVSDZrm_alt : | ||||||||
| 3747 | HasAVX ? X86::VMOVSDrm_alt : | ||||||||
| 3748 | X86::MOVSDrm_alt; | ||||||||
| 3749 | else | ||||||||
| 3750 | Opc = X86::LD_Fp64m; | ||||||||
| 3751 | break; | ||||||||
| 3752 | case MVT::f80: | ||||||||
| 3753 | // No f80 support yet. | ||||||||
| 3754 | return 0; | ||||||||
| 3755 | } | ||||||||
| 3756 | |||||||||
| 3757 | // MachineConstantPool wants an explicit alignment. | ||||||||
| 3758 | Align Alignment = DL.getPrefTypeAlign(CFP->getType()); | ||||||||
| 3759 | |||||||||
| 3760 | // x86-32 PIC requires a PIC base register for constant pools. | ||||||||
| 3761 | unsigned PICBase = 0; | ||||||||
| 3762 | unsigned char OpFlag = Subtarget->classifyLocalReference(nullptr); | ||||||||
| 3763 | if (OpFlag == X86II::MO_PIC_BASE_OFFSET) | ||||||||
| 3764 | PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF); | ||||||||
| 3765 | else if (OpFlag == X86II::MO_GOTOFF) | ||||||||
| 3766 | PICBase = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF); | ||||||||
| 3767 | else if (Subtarget->is64Bit() && TM.getCodeModel() == CodeModel::Small) | ||||||||
| 3768 | PICBase = X86::RIP; | ||||||||
| 3769 | |||||||||
| 3770 | // Create the load from the constant pool. | ||||||||
| 3771 | unsigned CPI = MCP.getConstantPoolIndex(CFP, Alignment); | ||||||||
| 3772 | Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); | ||||||||
| 3773 | |||||||||
| 3774 | // Large code model only applies to 64-bit mode. | ||||||||
| 3775 | if (Subtarget->is64Bit() && CM == CodeModel::Large) { | ||||||||
| 3776 | Register AddrReg = createResultReg(&X86::GR64RegClass); | ||||||||
| 3777 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV64ri), | ||||||||
| 3778 | AddrReg) | ||||||||
| 3779 | .addConstantPoolIndex(CPI, 0, OpFlag); | ||||||||
| 3780 | MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 3781 | TII.get(Opc), ResultReg); | ||||||||
| 3782 | addRegReg(MIB, AddrReg, false, PICBase, false); | ||||||||
| 3783 | MachineMemOperand *MMO = FuncInfo.MF->getMachineMemOperand( | ||||||||
| 3784 | MachinePointerInfo::getConstantPool(*FuncInfo.MF), | ||||||||
| 3785 | MachineMemOperand::MOLoad, DL.getPointerSize(), Alignment); | ||||||||
| 3786 | MIB->addMemOperand(*FuncInfo.MF, MMO); | ||||||||
| 3787 | return ResultReg; | ||||||||
| 3788 | } | ||||||||
| 3789 | |||||||||
| 3790 | addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 3791 | TII.get(Opc), ResultReg), | ||||||||
| 3792 | CPI, PICBase, OpFlag); | ||||||||
| 3793 | return ResultReg; | ||||||||
| 3794 | } | ||||||||
| 3795 | |||||||||
| 3796 | unsigned X86FastISel::X86MaterializeGV(const GlobalValue *GV, MVT VT) { | ||||||||
| 3797 | // Can't handle alternate code models yet. | ||||||||
| 3798 | if (TM.getCodeModel() != CodeModel::Small) | ||||||||
| 3799 | return 0; | ||||||||
| 3800 | |||||||||
| 3801 | // Materialize addresses with LEA/MOV instructions. | ||||||||
| 3802 | X86AddressMode AM; | ||||||||
| 3803 | if (X86SelectAddress(GV, AM)) { | ||||||||
| 3804 | // If the expression is just a basereg, then we're done, otherwise we need | ||||||||
| 3805 | // to emit an LEA. | ||||||||
| 3806 | if (AM.BaseType == X86AddressMode::RegBase && | ||||||||
| 3807 | AM.IndexReg == 0 && AM.Disp == 0 && AM.GV == nullptr) | ||||||||
| 3808 | return AM.Base.Reg; | ||||||||
| 3809 | |||||||||
| 3810 | Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); | ||||||||
| 3811 | if (TM.getRelocationModel() == Reloc::Static && | ||||||||
| 3812 | TLI.getPointerTy(DL) == MVT::i64) { | ||||||||
| 3813 | // The displacement code could be more than 32 bits away so we need to use | ||||||||
| 3814 | // an instruction with a 64 bit immediate | ||||||||
| 3815 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV64ri), | ||||||||
| 3816 | ResultReg) | ||||||||
| 3817 | .addGlobalAddress(GV); | ||||||||
| 3818 | } else { | ||||||||
| 3819 | unsigned Opc = | ||||||||
| 3820 | TLI.getPointerTy(DL) == MVT::i32 | ||||||||
| 3821 | ? (Subtarget->isTarget64BitILP32() ? X86::LEA64_32r : X86::LEA32r) | ||||||||
| 3822 | : X86::LEA64r; | ||||||||
| 3823 | addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 3824 | TII.get(Opc), ResultReg), AM); | ||||||||
| 3825 | } | ||||||||
| 3826 | return ResultReg; | ||||||||
| 3827 | } | ||||||||
| 3828 | return 0; | ||||||||
| 3829 | } | ||||||||
| 3830 | |||||||||
| 3831 | unsigned X86FastISel::fastMaterializeConstant(const Constant *C) { | ||||||||
| 3832 | EVT CEVT = TLI.getValueType(DL, C->getType(), true); | ||||||||
| 3833 | |||||||||
| 3834 | // Only handle simple types. | ||||||||
| 3835 | if (!CEVT.isSimple()) | ||||||||
| 3836 | return 0; | ||||||||
| 3837 | MVT VT = CEVT.getSimpleVT(); | ||||||||
| 3838 | |||||||||
| 3839 | if (const auto *CI = dyn_cast<ConstantInt>(C)) | ||||||||
| 3840 | return X86MaterializeInt(CI, VT); | ||||||||
| 3841 | else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) | ||||||||
| 3842 | return X86MaterializeFP(CFP, VT); | ||||||||
| 3843 | else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) | ||||||||
| 3844 | return X86MaterializeGV(GV, VT); | ||||||||
| 3845 | else if (isa<UndefValue>(C)) { | ||||||||
| 3846 | unsigned Opc = 0; | ||||||||
| 3847 | switch (VT.SimpleTy) { | ||||||||
| 3848 | default: | ||||||||
| 3849 | break; | ||||||||
| 3850 | case MVT::f32: | ||||||||
| 3851 | if (!X86ScalarSSEf32) | ||||||||
| 3852 | Opc = X86::LD_Fp032; | ||||||||
| 3853 | break; | ||||||||
| 3854 | case MVT::f64: | ||||||||
| 3855 | if (!X86ScalarSSEf64) | ||||||||
| 3856 | Opc = X86::LD_Fp064; | ||||||||
| 3857 | break; | ||||||||
| 3858 | case MVT::f80: | ||||||||
| 3859 | Opc = X86::LD_Fp080; | ||||||||
| 3860 | break; | ||||||||
| 3861 | } | ||||||||
| 3862 | |||||||||
| 3863 | if (Opc) { | ||||||||
| 3864 | Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); | ||||||||
| 3865 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), | ||||||||
| 3866 | ResultReg); | ||||||||
| 3867 | return ResultReg; | ||||||||
| 3868 | } | ||||||||
| 3869 | } | ||||||||
| 3870 | |||||||||
| 3871 | return 0; | ||||||||
| 3872 | } | ||||||||
| 3873 | |||||||||
| 3874 | unsigned X86FastISel::fastMaterializeAlloca(const AllocaInst *C) { | ||||||||
| 3875 | // Fail on dynamic allocas. At this point, getRegForValue has already | ||||||||
| 3876 | // checked its CSE maps, so if we're here trying to handle a dynamic | ||||||||
| 3877 | // alloca, we're not going to succeed. X86SelectAddress has a | ||||||||
| 3878 | // check for dynamic allocas, because it's called directly from | ||||||||
| 3879 | // various places, but targetMaterializeAlloca also needs a check | ||||||||
| 3880 | // in order to avoid recursion between getRegForValue, | ||||||||
| 3881 | // X86SelectAddrss, and targetMaterializeAlloca. | ||||||||
| 3882 | if (!FuncInfo.StaticAllocaMap.count(C)) | ||||||||
| 3883 | return 0; | ||||||||
| 3884 | assert(C->isStaticAlloca() && "dynamic alloca in the static alloca map?")((void)0); | ||||||||
| 3885 | |||||||||
| 3886 | X86AddressMode AM; | ||||||||
| 3887 | if (!X86SelectAddress(C, AM)) | ||||||||
| 3888 | return 0; | ||||||||
| 3889 | unsigned Opc = | ||||||||
| 3890 | TLI.getPointerTy(DL) == MVT::i32 | ||||||||
| 3891 | ? (Subtarget->isTarget64BitILP32() ? X86::LEA64_32r : X86::LEA32r) | ||||||||
| 3892 | : X86::LEA64r; | ||||||||
| 3893 | const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL)); | ||||||||
| 3894 | Register ResultReg = createResultReg(RC); | ||||||||
| 3895 | addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 3896 | TII.get(Opc), ResultReg), AM); | ||||||||
| 3897 | return ResultReg; | ||||||||
| 3898 | } | ||||||||
| 3899 | |||||||||
| 3900 | unsigned X86FastISel::fastMaterializeFloatZero(const ConstantFP *CF) { | ||||||||
| 3901 | MVT VT; | ||||||||
| 3902 | if (!isTypeLegal(CF->getType(), VT)) | ||||||||
| 3903 | return 0; | ||||||||
| 3904 | |||||||||
| 3905 | // Get opcode and regclass for the given zero. | ||||||||
| 3906 | bool HasAVX512 = Subtarget->hasAVX512(); | ||||||||
| 3907 | unsigned Opc = 0; | ||||||||
| 3908 | switch (VT.SimpleTy) { | ||||||||
| 3909 | default: return 0; | ||||||||
| 3910 | case MVT::f32: | ||||||||
| 3911 | if (X86ScalarSSEf32) | ||||||||
| 3912 | Opc = HasAVX512 ? X86::AVX512_FsFLD0SS : X86::FsFLD0SS; | ||||||||
| 3913 | else | ||||||||
| 3914 | Opc = X86::LD_Fp032; | ||||||||
| 3915 | break; | ||||||||
| 3916 | case MVT::f64: | ||||||||
| 3917 | if (X86ScalarSSEf64) | ||||||||
| 3918 | Opc = HasAVX512 ? X86::AVX512_FsFLD0SD : X86::FsFLD0SD; | ||||||||
| 3919 | else | ||||||||
| 3920 | Opc = X86::LD_Fp064; | ||||||||
| 3921 | break; | ||||||||
| 3922 | case MVT::f80: | ||||||||
| 3923 | // No f80 support yet. | ||||||||
| 3924 | return 0; | ||||||||
| 3925 | } | ||||||||
| 3926 | |||||||||
| 3927 | Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); | ||||||||
| 3928 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); | ||||||||
| 3929 | return ResultReg; | ||||||||
| 3930 | } | ||||||||
| 3931 | |||||||||
| 3932 | |||||||||
| 3933 | bool X86FastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, | ||||||||
| 3934 | const LoadInst *LI) { | ||||||||
| 3935 | const Value *Ptr = LI->getPointerOperand(); | ||||||||
| 3936 | X86AddressMode AM; | ||||||||
| 3937 | if (!X86SelectAddress(Ptr, AM)) | ||||||||
| 3938 | return false; | ||||||||
| 3939 | |||||||||
| 3940 | const X86InstrInfo &XII = (const X86InstrInfo &)TII; | ||||||||
| 3941 | |||||||||
| 3942 | unsigned Size = DL.getTypeAllocSize(LI->getType()); | ||||||||
| 3943 | |||||||||
| 3944 | SmallVector<MachineOperand, 8> AddrOps; | ||||||||
| 3945 | AM.getFullAddress(AddrOps); | ||||||||
| 3946 | |||||||||
| 3947 | MachineInstr *Result = XII.foldMemoryOperandImpl( | ||||||||
| 3948 | *FuncInfo.MF, *MI, OpNo, AddrOps, FuncInfo.InsertPt, Size, LI->getAlign(), | ||||||||
| 3949 | /*AllowCommute=*/true); | ||||||||
| 3950 | if (!Result) | ||||||||
| 3951 | return false; | ||||||||
| 3952 | |||||||||
| 3953 | // The index register could be in the wrong register class. Unfortunately, | ||||||||
| 3954 | // foldMemoryOperandImpl could have commuted the instruction so its not enough | ||||||||
| 3955 | // to just look at OpNo + the offset to the index reg. We actually need to | ||||||||
| 3956 | // scan the instruction to find the index reg and see if its the correct reg | ||||||||
| 3957 | // class. | ||||||||
| 3958 | unsigned OperandNo = 0; | ||||||||
| 3959 | for (MachineInstr::mop_iterator I = Result->operands_begin(), | ||||||||
| 3960 | E = Result->operands_end(); I != E; ++I, ++OperandNo) { | ||||||||
| 3961 | MachineOperand &MO = *I; | ||||||||
| 3962 | if (!MO.isReg() || MO.isDef() || MO.getReg() != AM.IndexReg) | ||||||||
| 3963 | continue; | ||||||||
| 3964 | // Found the index reg, now try to rewrite it. | ||||||||
| 3965 | Register IndexReg = constrainOperandRegClass(Result->getDesc(), | ||||||||
| 3966 | MO.getReg(), OperandNo); | ||||||||
| 3967 | if (IndexReg == MO.getReg()) | ||||||||
| 3968 | continue; | ||||||||
| 3969 | MO.setReg(IndexReg); | ||||||||
| 3970 | } | ||||||||
| 3971 | |||||||||
| 3972 | Result->addMemOperand(*FuncInfo.MF, createMachineMemOperandFor(LI)); | ||||||||
| 3973 | Result->cloneInstrSymbols(*FuncInfo.MF, *MI); | ||||||||
| 3974 | MachineBasicBlock::iterator I(MI); | ||||||||
| 3975 | removeDeadCode(I, std::next(I)); | ||||||||
| 3976 | return true; | ||||||||
| 3977 | } | ||||||||
| 3978 | |||||||||
| 3979 | unsigned X86FastISel::fastEmitInst_rrrr(unsigned MachineInstOpcode, | ||||||||
| 3980 | const TargetRegisterClass *RC, | ||||||||
| 3981 | unsigned Op0, unsigned Op1, | ||||||||
| 3982 | unsigned Op2, unsigned Op3) { | ||||||||
| 3983 | const MCInstrDesc &II = TII.get(MachineInstOpcode); | ||||||||
| 3984 | |||||||||
| 3985 | Register ResultReg = createResultReg(RC); | ||||||||
| 3986 | Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); | ||||||||
| 3987 | Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); | ||||||||
| 3988 | Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); | ||||||||
| 3989 | Op3 = constrainOperandRegClass(II, Op3, II.getNumDefs() + 3); | ||||||||
| 3990 | |||||||||
| 3991 | if (II.getNumDefs() >= 1) | ||||||||
| 3992 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) | ||||||||
| 3993 | .addReg(Op0) | ||||||||
| 3994 | .addReg(Op1) | ||||||||
| 3995 | .addReg(Op2) | ||||||||
| 3996 | .addReg(Op3); | ||||||||
| 3997 | else { | ||||||||
| 3998 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II) | ||||||||
| 3999 | .addReg(Op0) | ||||||||
| 4000 | .addReg(Op1) | ||||||||
| 4001 | .addReg(Op2) | ||||||||
| 4002 | .addReg(Op3); | ||||||||
| 4003 | BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, | ||||||||
| 4004 | TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]); | ||||||||
| 4005 | } | ||||||||
| 4006 | return ResultReg; | ||||||||
| 4007 | } | ||||||||
| 4008 | |||||||||
| 4009 | |||||||||
| 4010 | namespace llvm { | ||||||||
| 4011 | FastISel *X86::createFastISel(FunctionLoweringInfo &funcInfo, | ||||||||
| 4012 | const TargetLibraryInfo *libInfo) { | ||||||||
| 4013 | return new X86FastISel(funcInfo, libInfo); | ||||||||
| 4014 | } | ||||||||
| 4015 | } |
| 1 | //===- llvm/Instructions.h - Instruction subclass definitions ---*- C++ -*-===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // |
| 9 | // This file exposes the class definitions of all of the subclasses of the |
| 10 | // Instruction class. This is meant to be an easy way to get access to all |
| 11 | // instruction subclasses. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | #ifndef LLVM_IR_INSTRUCTIONS_H |
| 16 | #define LLVM_IR_INSTRUCTIONS_H |
| 17 | |
| 18 | #include "llvm/ADT/ArrayRef.h" |
| 19 | #include "llvm/ADT/Bitfields.h" |
| 20 | #include "llvm/ADT/MapVector.h" |
| 21 | #include "llvm/ADT/None.h" |
| 22 | #include "llvm/ADT/STLExtras.h" |
| 23 | #include "llvm/ADT/SmallVector.h" |
| 24 | #include "llvm/ADT/StringRef.h" |
| 25 | #include "llvm/ADT/Twine.h" |
| 26 | #include "llvm/ADT/iterator.h" |
| 27 | #include "llvm/ADT/iterator_range.h" |
| 28 | #include "llvm/IR/Attributes.h" |
| 29 | #include "llvm/IR/BasicBlock.h" |
| 30 | #include "llvm/IR/CallingConv.h" |
| 31 | #include "llvm/IR/CFG.h" |
| 32 | #include "llvm/IR/Constant.h" |
| 33 | #include "llvm/IR/DerivedTypes.h" |
| 34 | #include "llvm/IR/Function.h" |
| 35 | #include "llvm/IR/InstrTypes.h" |
| 36 | #include "llvm/IR/Instruction.h" |
| 37 | #include "llvm/IR/OperandTraits.h" |
| 38 | #include "llvm/IR/Type.h" |
| 39 | #include "llvm/IR/Use.h" |
| 40 | #include "llvm/IR/User.h" |
| 41 | #include "llvm/IR/Value.h" |
| 42 | #include "llvm/Support/AtomicOrdering.h" |
| 43 | #include "llvm/Support/Casting.h" |
| 44 | #include "llvm/Support/ErrorHandling.h" |
| 45 | #include <cassert> |
| 46 | #include <cstddef> |
| 47 | #include <cstdint> |
| 48 | #include <iterator> |
| 49 | |
| 50 | namespace llvm { |
| 51 | |
| 52 | class APInt; |
| 53 | class ConstantInt; |
| 54 | class DataLayout; |
| 55 | class LLVMContext; |
| 56 | |
| 57 | //===----------------------------------------------------------------------===// |
| 58 | // AllocaInst Class |
| 59 | //===----------------------------------------------------------------------===// |
| 60 | |
| 61 | /// an instruction to allocate memory on the stack |
| 62 | class AllocaInst : public UnaryInstruction { |
| 63 | Type *AllocatedType; |
| 64 | |
| 65 | using AlignmentField = AlignmentBitfieldElementT<0>; |
| 66 | using UsedWithInAllocaField = BoolBitfieldElementT<AlignmentField::NextBit>; |
| 67 | using SwiftErrorField = BoolBitfieldElementT<UsedWithInAllocaField::NextBit>; |
| 68 | static_assert(Bitfield::areContiguous<AlignmentField, UsedWithInAllocaField, |
| 69 | SwiftErrorField>(), |
| 70 | "Bitfields must be contiguous"); |
| 71 | |
| 72 | protected: |
| 73 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 74 | friend class Instruction; |
| 75 | |
| 76 | AllocaInst *cloneImpl() const; |
| 77 | |
| 78 | public: |
| 79 | explicit AllocaInst(Type *Ty, unsigned AddrSpace, Value *ArraySize, |
| 80 | const Twine &Name, Instruction *InsertBefore); |
| 81 | AllocaInst(Type *Ty, unsigned AddrSpace, Value *ArraySize, |
| 82 | const Twine &Name, BasicBlock *InsertAtEnd); |
| 83 | |
| 84 | AllocaInst(Type *Ty, unsigned AddrSpace, const Twine &Name, |
| 85 | Instruction *InsertBefore); |
| 86 | AllocaInst(Type *Ty, unsigned AddrSpace, |
| 87 | const Twine &Name, BasicBlock *InsertAtEnd); |
| 88 | |
| 89 | AllocaInst(Type *Ty, unsigned AddrSpace, Value *ArraySize, Align Align, |
| 90 | const Twine &Name = "", Instruction *InsertBefore = nullptr); |
| 91 | AllocaInst(Type *Ty, unsigned AddrSpace, Value *ArraySize, Align Align, |
| 92 | const Twine &Name, BasicBlock *InsertAtEnd); |
| 93 | |
| 94 | /// Return true if there is an allocation size parameter to the allocation |
| 95 | /// instruction that is not 1. |
| 96 | bool isArrayAllocation() const; |
| 97 | |
| 98 | /// Get the number of elements allocated. For a simple allocation of a single |
| 99 | /// element, this will return a constant 1 value. |
| 100 | const Value *getArraySize() const { return getOperand(0); } |
| 101 | Value *getArraySize() { return getOperand(0); } |
| 102 | |
| 103 | /// Overload to return most specific pointer type. |
| 104 | PointerType *getType() const { |
| 105 | return cast<PointerType>(Instruction::getType()); |
| 106 | } |
| 107 | |
| 108 | /// Get allocation size in bits. Returns None if size can't be determined, |
| 109 | /// e.g. in case of a VLA. |
| 110 | Optional<TypeSize> getAllocationSizeInBits(const DataLayout &DL) const; |
| 111 | |
| 112 | /// Return the type that is being allocated by the instruction. |
| 113 | Type *getAllocatedType() const { return AllocatedType; } |
| 114 | /// for use only in special circumstances that need to generically |
| 115 | /// transform a whole instruction (eg: IR linking and vectorization). |
| 116 | void setAllocatedType(Type *Ty) { AllocatedType = Ty; } |
| 117 | |
| 118 | /// Return the alignment of the memory that is being allocated by the |
| 119 | /// instruction. |
| 120 | Align getAlign() const { |
| 121 | return Align(1ULL << getSubclassData<AlignmentField>()); |
| 122 | } |
| 123 | |
| 124 | void setAlignment(Align Align) { |
| 125 | setSubclassData<AlignmentField>(Log2(Align)); |
| 126 | } |
| 127 | |
| 128 | // FIXME: Remove this one transition to Align is over. |
| 129 | unsigned getAlignment() const { return getAlign().value(); } |
| 130 | |
| 131 | /// Return true if this alloca is in the entry block of the function and is a |
| 132 | /// constant size. If so, the code generator will fold it into the |
| 133 | /// prolog/epilog code, so it is basically free. |
| 134 | bool isStaticAlloca() const; |
| 135 | |
| 136 | /// Return true if this alloca is used as an inalloca argument to a call. Such |
| 137 | /// allocas are never considered static even if they are in the entry block. |
| 138 | bool isUsedWithInAlloca() const { |
| 139 | return getSubclassData<UsedWithInAllocaField>(); |
| 140 | } |
| 141 | |
| 142 | /// Specify whether this alloca is used to represent the arguments to a call. |
| 143 | void setUsedWithInAlloca(bool V) { |
| 144 | setSubclassData<UsedWithInAllocaField>(V); |
| 145 | } |
| 146 | |
| 147 | /// Return true if this alloca is used as a swifterror argument to a call. |
| 148 | bool isSwiftError() const { return getSubclassData<SwiftErrorField>(); } |
| 149 | /// Specify whether this alloca is used to represent a swifterror. |
| 150 | void setSwiftError(bool V) { setSubclassData<SwiftErrorField>(V); } |
| 151 | |
| 152 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 153 | static bool classof(const Instruction *I) { |
| 154 | return (I->getOpcode() == Instruction::Alloca); |
| 155 | } |
| 156 | static bool classof(const Value *V) { |
| 157 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 158 | } |
| 159 | |
| 160 | private: |
| 161 | // Shadow Instruction::setInstructionSubclassData with a private forwarding |
| 162 | // method so that subclasses cannot accidentally use it. |
| 163 | template <typename Bitfield> |
| 164 | void setSubclassData(typename Bitfield::Type Value) { |
| 165 | Instruction::setSubclassData<Bitfield>(Value); |
| 166 | } |
| 167 | }; |
| 168 | |
| 169 | //===----------------------------------------------------------------------===// |
| 170 | // LoadInst Class |
| 171 | //===----------------------------------------------------------------------===// |
| 172 | |
| 173 | /// An instruction for reading from memory. This uses the SubclassData field in |
| 174 | /// Value to store whether or not the load is volatile. |
| 175 | class LoadInst : public UnaryInstruction { |
| 176 | using VolatileField = BoolBitfieldElementT<0>; |
| 177 | using AlignmentField = AlignmentBitfieldElementT<VolatileField::NextBit>; |
| 178 | using OrderingField = AtomicOrderingBitfieldElementT<AlignmentField::NextBit>; |
| 179 | static_assert( |
| 180 | Bitfield::areContiguous<VolatileField, AlignmentField, OrderingField>(), |
| 181 | "Bitfields must be contiguous"); |
| 182 | |
| 183 | void AssertOK(); |
| 184 | |
| 185 | protected: |
| 186 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 187 | friend class Instruction; |
| 188 | |
| 189 | LoadInst *cloneImpl() const; |
| 190 | |
| 191 | public: |
| 192 | LoadInst(Type *Ty, Value *Ptr, const Twine &NameStr, |
| 193 | Instruction *InsertBefore); |
| 194 | LoadInst(Type *Ty, Value *Ptr, const Twine &NameStr, BasicBlock *InsertAtEnd); |
| 195 | LoadInst(Type *Ty, Value *Ptr, const Twine &NameStr, bool isVolatile, |
| 196 | Instruction *InsertBefore); |
| 197 | LoadInst(Type *Ty, Value *Ptr, const Twine &NameStr, bool isVolatile, |
| 198 | BasicBlock *InsertAtEnd); |
| 199 | LoadInst(Type *Ty, Value *Ptr, const Twine &NameStr, bool isVolatile, |
| 200 | Align Align, Instruction *InsertBefore = nullptr); |
| 201 | LoadInst(Type *Ty, Value *Ptr, const Twine &NameStr, bool isVolatile, |
| 202 | Align Align, BasicBlock *InsertAtEnd); |
| 203 | LoadInst(Type *Ty, Value *Ptr, const Twine &NameStr, bool isVolatile, |
| 204 | Align Align, AtomicOrdering Order, |
| 205 | SyncScope::ID SSID = SyncScope::System, |
| 206 | Instruction *InsertBefore = nullptr); |
| 207 | LoadInst(Type *Ty, Value *Ptr, const Twine &NameStr, bool isVolatile, |
| 208 | Align Align, AtomicOrdering Order, SyncScope::ID SSID, |
| 209 | BasicBlock *InsertAtEnd); |
| 210 | |
| 211 | /// Return true if this is a load from a volatile memory location. |
| 212 | bool isVolatile() const { return getSubclassData<VolatileField>(); } |
| 213 | |
| 214 | /// Specify whether this is a volatile load or not. |
| 215 | void setVolatile(bool V) { setSubclassData<VolatileField>(V); } |
| 216 | |
| 217 | /// Return the alignment of the access that is being performed. |
| 218 | /// FIXME: Remove this function once transition to Align is over. |
| 219 | /// Use getAlign() instead. |
| 220 | unsigned getAlignment() const { return getAlign().value(); } |
| 221 | |
| 222 | /// Return the alignment of the access that is being performed. |
| 223 | Align getAlign() const { |
| 224 | return Align(1ULL << (getSubclassData<AlignmentField>())); |
| 225 | } |
| 226 | |
| 227 | void setAlignment(Align Align) { |
| 228 | setSubclassData<AlignmentField>(Log2(Align)); |
| 229 | } |
| 230 | |
| 231 | /// Returns the ordering constraint of this load instruction. |
| 232 | AtomicOrdering getOrdering() const { |
| 233 | return getSubclassData<OrderingField>(); |
| 234 | } |
| 235 | /// Sets the ordering constraint of this load instruction. May not be Release |
| 236 | /// or AcquireRelease. |
| 237 | void setOrdering(AtomicOrdering Ordering) { |
| 238 | setSubclassData<OrderingField>(Ordering); |
| 239 | } |
| 240 | |
| 241 | /// Returns the synchronization scope ID of this load instruction. |
| 242 | SyncScope::ID getSyncScopeID() const { |
| 243 | return SSID; |
| 244 | } |
| 245 | |
| 246 | /// Sets the synchronization scope ID of this load instruction. |
| 247 | void setSyncScopeID(SyncScope::ID SSID) { |
| 248 | this->SSID = SSID; |
| 249 | } |
| 250 | |
| 251 | /// Sets the ordering constraint and the synchronization scope ID of this load |
| 252 | /// instruction. |
| 253 | void setAtomic(AtomicOrdering Ordering, |
| 254 | SyncScope::ID SSID = SyncScope::System) { |
| 255 | setOrdering(Ordering); |
| 256 | setSyncScopeID(SSID); |
| 257 | } |
| 258 | |
| 259 | bool isSimple() const { return !isAtomic() && !isVolatile(); } |
| 260 | |
| 261 | bool isUnordered() const { |
| 262 | return (getOrdering() == AtomicOrdering::NotAtomic || |
| 263 | getOrdering() == AtomicOrdering::Unordered) && |
| 264 | !isVolatile(); |
| 265 | } |
| 266 | |
| 267 | Value *getPointerOperand() { return getOperand(0); } |
| 268 | const Value *getPointerOperand() const { return getOperand(0); } |
| 269 | static unsigned getPointerOperandIndex() { return 0U; } |
| 270 | Type *getPointerOperandType() const { return getPointerOperand()->getType(); } |
| 271 | |
| 272 | /// Returns the address space of the pointer operand. |
| 273 | unsigned getPointerAddressSpace() const { |
| 274 | return getPointerOperandType()->getPointerAddressSpace(); |
| 275 | } |
| 276 | |
| 277 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 278 | static bool classof(const Instruction *I) { |
| 279 | return I->getOpcode() == Instruction::Load; |
| 280 | } |
| 281 | static bool classof(const Value *V) { |
| 282 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 283 | } |
| 284 | |
| 285 | private: |
| 286 | // Shadow Instruction::setInstructionSubclassData with a private forwarding |
| 287 | // method so that subclasses cannot accidentally use it. |
| 288 | template <typename Bitfield> |
| 289 | void setSubclassData(typename Bitfield::Type Value) { |
| 290 | Instruction::setSubclassData<Bitfield>(Value); |
| 291 | } |
| 292 | |
| 293 | /// The synchronization scope ID of this load instruction. Not quite enough |
| 294 | /// room in SubClassData for everything, so synchronization scope ID gets its |
| 295 | /// own field. |
| 296 | SyncScope::ID SSID; |
| 297 | }; |
| 298 | |
| 299 | //===----------------------------------------------------------------------===// |
| 300 | // StoreInst Class |
| 301 | //===----------------------------------------------------------------------===// |
| 302 | |
| 303 | /// An instruction for storing to memory. |
| 304 | class StoreInst : public Instruction { |
| 305 | using VolatileField = BoolBitfieldElementT<0>; |
| 306 | using AlignmentField = AlignmentBitfieldElementT<VolatileField::NextBit>; |
| 307 | using OrderingField = AtomicOrderingBitfieldElementT<AlignmentField::NextBit>; |
| 308 | static_assert( |
| 309 | Bitfield::areContiguous<VolatileField, AlignmentField, OrderingField>(), |
| 310 | "Bitfields must be contiguous"); |
| 311 | |
| 312 | void AssertOK(); |
| 313 | |
| 314 | protected: |
| 315 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 316 | friend class Instruction; |
| 317 | |
| 318 | StoreInst *cloneImpl() const; |
| 319 | |
| 320 | public: |
| 321 | StoreInst(Value *Val, Value *Ptr, Instruction *InsertBefore); |
| 322 | StoreInst(Value *Val, Value *Ptr, BasicBlock *InsertAtEnd); |
| 323 | StoreInst(Value *Val, Value *Ptr, bool isVolatile, Instruction *InsertBefore); |
| 324 | StoreInst(Value *Val, Value *Ptr, bool isVolatile, BasicBlock *InsertAtEnd); |
| 325 | StoreInst(Value *Val, Value *Ptr, bool isVolatile, Align Align, |
| 326 | Instruction *InsertBefore = nullptr); |
| 327 | StoreInst(Value *Val, Value *Ptr, bool isVolatile, Align Align, |
| 328 | BasicBlock *InsertAtEnd); |
| 329 | StoreInst(Value *Val, Value *Ptr, bool isVolatile, Align Align, |
| 330 | AtomicOrdering Order, SyncScope::ID SSID = SyncScope::System, |
| 331 | Instruction *InsertBefore = nullptr); |
| 332 | StoreInst(Value *Val, Value *Ptr, bool isVolatile, Align Align, |
| 333 | AtomicOrdering Order, SyncScope::ID SSID, BasicBlock *InsertAtEnd); |
| 334 | |
| 335 | // allocate space for exactly two operands |
| 336 | void *operator new(size_t S) { return User::operator new(S, 2); } |
| 337 | void operator delete(void *Ptr) { User::operator delete(Ptr); } |
| 338 | |
| 339 | /// Return true if this is a store to a volatile memory location. |
| 340 | bool isVolatile() const { return getSubclassData<VolatileField>(); } |
| 341 | |
| 342 | /// Specify whether this is a volatile store or not. |
| 343 | void setVolatile(bool V) { setSubclassData<VolatileField>(V); } |
| 344 | |
| 345 | /// Transparently provide more efficient getOperand methods. |
| 346 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 347 | |
| 348 | /// Return the alignment of the access that is being performed |
| 349 | /// FIXME: Remove this function once transition to Align is over. |
| 350 | /// Use getAlign() instead. |
| 351 | unsigned getAlignment() const { return getAlign().value(); } |
| 352 | |
| 353 | Align getAlign() const { |
| 354 | return Align(1ULL << (getSubclassData<AlignmentField>())); |
| 355 | } |
| 356 | |
| 357 | void setAlignment(Align Align) { |
| 358 | setSubclassData<AlignmentField>(Log2(Align)); |
| 359 | } |
| 360 | |
| 361 | /// Returns the ordering constraint of this store instruction. |
| 362 | AtomicOrdering getOrdering() const { |
| 363 | return getSubclassData<OrderingField>(); |
| 364 | } |
| 365 | |
| 366 | /// Sets the ordering constraint of this store instruction. May not be |
| 367 | /// Acquire or AcquireRelease. |
| 368 | void setOrdering(AtomicOrdering Ordering) { |
| 369 | setSubclassData<OrderingField>(Ordering); |
| 370 | } |
| 371 | |
| 372 | /// Returns the synchronization scope ID of this store instruction. |
| 373 | SyncScope::ID getSyncScopeID() const { |
| 374 | return SSID; |
| 375 | } |
| 376 | |
| 377 | /// Sets the synchronization scope ID of this store instruction. |
| 378 | void setSyncScopeID(SyncScope::ID SSID) { |
| 379 | this->SSID = SSID; |
| 380 | } |
| 381 | |
| 382 | /// Sets the ordering constraint and the synchronization scope ID of this |
| 383 | /// store instruction. |
| 384 | void setAtomic(AtomicOrdering Ordering, |
| 385 | SyncScope::ID SSID = SyncScope::System) { |
| 386 | setOrdering(Ordering); |
| 387 | setSyncScopeID(SSID); |
| 388 | } |
| 389 | |
| 390 | bool isSimple() const { return !isAtomic() && !isVolatile(); } |
| 391 | |
| 392 | bool isUnordered() const { |
| 393 | return (getOrdering() == AtomicOrdering::NotAtomic || |
| 394 | getOrdering() == AtomicOrdering::Unordered) && |
| 395 | !isVolatile(); |
| 396 | } |
| 397 | |
| 398 | Value *getValueOperand() { return getOperand(0); } |
| 399 | const Value *getValueOperand() const { return getOperand(0); } |
| 400 | |
| 401 | Value *getPointerOperand() { return getOperand(1); } |
| 402 | const Value *getPointerOperand() const { return getOperand(1); } |
| 403 | static unsigned getPointerOperandIndex() { return 1U; } |
| 404 | Type *getPointerOperandType() const { return getPointerOperand()->getType(); } |
| 405 | |
| 406 | /// Returns the address space of the pointer operand. |
| 407 | unsigned getPointerAddressSpace() const { |
| 408 | return getPointerOperandType()->getPointerAddressSpace(); |
| 409 | } |
| 410 | |
| 411 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 412 | static bool classof(const Instruction *I) { |
| 413 | return I->getOpcode() == Instruction::Store; |
| 414 | } |
| 415 | static bool classof(const Value *V) { |
| 416 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 417 | } |
| 418 | |
| 419 | private: |
| 420 | // Shadow Instruction::setInstructionSubclassData with a private forwarding |
| 421 | // method so that subclasses cannot accidentally use it. |
| 422 | template <typename Bitfield> |
| 423 | void setSubclassData(typename Bitfield::Type Value) { |
| 424 | Instruction::setSubclassData<Bitfield>(Value); |
| 425 | } |
| 426 | |
| 427 | /// The synchronization scope ID of this store instruction. Not quite enough |
| 428 | /// room in SubClassData for everything, so synchronization scope ID gets its |
| 429 | /// own field. |
| 430 | SyncScope::ID SSID; |
| 431 | }; |
| 432 | |
| 433 | template <> |
| 434 | struct OperandTraits<StoreInst> : public FixedNumOperandTraits<StoreInst, 2> { |
| 435 | }; |
| 436 | |
| 437 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(StoreInst, Value)StoreInst::op_iterator StoreInst::op_begin() { return OperandTraits <StoreInst>::op_begin(this); } StoreInst::const_op_iterator StoreInst::op_begin() const { return OperandTraits<StoreInst >::op_begin(const_cast<StoreInst*>(this)); } StoreInst ::op_iterator StoreInst::op_end() { return OperandTraits<StoreInst >::op_end(this); } StoreInst::const_op_iterator StoreInst:: op_end() const { return OperandTraits<StoreInst>::op_end (const_cast<StoreInst*>(this)); } Value *StoreInst::getOperand (unsigned i_nocapture) const { ((void)0); return cast_or_null <Value>( OperandTraits<StoreInst>::op_begin(const_cast <StoreInst*>(this))[i_nocapture].get()); } void StoreInst ::setOperand(unsigned i_nocapture, Value *Val_nocapture) { (( void)0); OperandTraits<StoreInst>::op_begin(this)[i_nocapture ] = Val_nocapture; } unsigned StoreInst::getNumOperands() const { return OperandTraits<StoreInst>::operands(this); } template <int Idx_nocapture> Use &StoreInst::Op() { return this ->OpFrom<Idx_nocapture>(this); } template <int Idx_nocapture > const Use &StoreInst::Op() const { return this->OpFrom <Idx_nocapture>(this); } |
| 438 | |
| 439 | //===----------------------------------------------------------------------===// |
| 440 | // FenceInst Class |
| 441 | //===----------------------------------------------------------------------===// |
| 442 | |
| 443 | /// An instruction for ordering other memory operations. |
| 444 | class FenceInst : public Instruction { |
| 445 | using OrderingField = AtomicOrderingBitfieldElementT<0>; |
| 446 | |
| 447 | void Init(AtomicOrdering Ordering, SyncScope::ID SSID); |
| 448 | |
| 449 | protected: |
| 450 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 451 | friend class Instruction; |
| 452 | |
| 453 | FenceInst *cloneImpl() const; |
| 454 | |
| 455 | public: |
| 456 | // Ordering may only be Acquire, Release, AcquireRelease, or |
| 457 | // SequentiallyConsistent. |
| 458 | FenceInst(LLVMContext &C, AtomicOrdering Ordering, |
| 459 | SyncScope::ID SSID = SyncScope::System, |
| 460 | Instruction *InsertBefore = nullptr); |
| 461 | FenceInst(LLVMContext &C, AtomicOrdering Ordering, SyncScope::ID SSID, |
| 462 | BasicBlock *InsertAtEnd); |
| 463 | |
| 464 | // allocate space for exactly zero operands |
| 465 | void *operator new(size_t S) { return User::operator new(S, 0); } |
| 466 | void operator delete(void *Ptr) { User::operator delete(Ptr); } |
| 467 | |
| 468 | /// Returns the ordering constraint of this fence instruction. |
| 469 | AtomicOrdering getOrdering() const { |
| 470 | return getSubclassData<OrderingField>(); |
| 471 | } |
| 472 | |
| 473 | /// Sets the ordering constraint of this fence instruction. May only be |
| 474 | /// Acquire, Release, AcquireRelease, or SequentiallyConsistent. |
| 475 | void setOrdering(AtomicOrdering Ordering) { |
| 476 | setSubclassData<OrderingField>(Ordering); |
| 477 | } |
| 478 | |
| 479 | /// Returns the synchronization scope ID of this fence instruction. |
| 480 | SyncScope::ID getSyncScopeID() const { |
| 481 | return SSID; |
| 482 | } |
| 483 | |
| 484 | /// Sets the synchronization scope ID of this fence instruction. |
| 485 | void setSyncScopeID(SyncScope::ID SSID) { |
| 486 | this->SSID = SSID; |
| 487 | } |
| 488 | |
| 489 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 490 | static bool classof(const Instruction *I) { |
| 491 | return I->getOpcode() == Instruction::Fence; |
| 492 | } |
| 493 | static bool classof(const Value *V) { |
| 494 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 495 | } |
| 496 | |
| 497 | private: |
| 498 | // Shadow Instruction::setInstructionSubclassData with a private forwarding |
| 499 | // method so that subclasses cannot accidentally use it. |
| 500 | template <typename Bitfield> |
| 501 | void setSubclassData(typename Bitfield::Type Value) { |
| 502 | Instruction::setSubclassData<Bitfield>(Value); |
| 503 | } |
| 504 | |
| 505 | /// The synchronization scope ID of this fence instruction. Not quite enough |
| 506 | /// room in SubClassData for everything, so synchronization scope ID gets its |
| 507 | /// own field. |
| 508 | SyncScope::ID SSID; |
| 509 | }; |
| 510 | |
| 511 | //===----------------------------------------------------------------------===// |
| 512 | // AtomicCmpXchgInst Class |
| 513 | //===----------------------------------------------------------------------===// |
| 514 | |
| 515 | /// An instruction that atomically checks whether a |
| 516 | /// specified value is in a memory location, and, if it is, stores a new value |
| 517 | /// there. The value returned by this instruction is a pair containing the |
| 518 | /// original value as first element, and an i1 indicating success (true) or |
| 519 | /// failure (false) as second element. |
| 520 | /// |
| 521 | class AtomicCmpXchgInst : public Instruction { |
| 522 | void Init(Value *Ptr, Value *Cmp, Value *NewVal, Align Align, |
| 523 | AtomicOrdering SuccessOrdering, AtomicOrdering FailureOrdering, |
| 524 | SyncScope::ID SSID); |
| 525 | |
| 526 | template <unsigned Offset> |
| 527 | using AtomicOrderingBitfieldElement = |
| 528 | typename Bitfield::Element<AtomicOrdering, Offset, 3, |
| 529 | AtomicOrdering::LAST>; |
| 530 | |
| 531 | protected: |
| 532 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 533 | friend class Instruction; |
| 534 | |
| 535 | AtomicCmpXchgInst *cloneImpl() const; |
| 536 | |
| 537 | public: |
| 538 | AtomicCmpXchgInst(Value *Ptr, Value *Cmp, Value *NewVal, Align Alignment, |
| 539 | AtomicOrdering SuccessOrdering, |
| 540 | AtomicOrdering FailureOrdering, SyncScope::ID SSID, |
| 541 | Instruction *InsertBefore = nullptr); |
| 542 | AtomicCmpXchgInst(Value *Ptr, Value *Cmp, Value *NewVal, Align Alignment, |
| 543 | AtomicOrdering SuccessOrdering, |
| 544 | AtomicOrdering FailureOrdering, SyncScope::ID SSID, |
| 545 | BasicBlock *InsertAtEnd); |
| 546 | |
| 547 | // allocate space for exactly three operands |
| 548 | void *operator new(size_t S) { return User::operator new(S, 3); } |
| 549 | void operator delete(void *Ptr) { User::operator delete(Ptr); } |
| 550 | |
| 551 | using VolatileField = BoolBitfieldElementT<0>; |
| 552 | using WeakField = BoolBitfieldElementT<VolatileField::NextBit>; |
| 553 | using SuccessOrderingField = |
| 554 | AtomicOrderingBitfieldElementT<WeakField::NextBit>; |
| 555 | using FailureOrderingField = |
| 556 | AtomicOrderingBitfieldElementT<SuccessOrderingField::NextBit>; |
| 557 | using AlignmentField = |
| 558 | AlignmentBitfieldElementT<FailureOrderingField::NextBit>; |
| 559 | static_assert( |
| 560 | Bitfield::areContiguous<VolatileField, WeakField, SuccessOrderingField, |
| 561 | FailureOrderingField, AlignmentField>(), |
| 562 | "Bitfields must be contiguous"); |
| 563 | |
| 564 | /// Return the alignment of the memory that is being allocated by the |
| 565 | /// instruction. |
| 566 | Align getAlign() const { |
| 567 | return Align(1ULL << getSubclassData<AlignmentField>()); |
| 568 | } |
| 569 | |
| 570 | void setAlignment(Align Align) { |
| 571 | setSubclassData<AlignmentField>(Log2(Align)); |
| 572 | } |
| 573 | |
| 574 | /// Return true if this is a cmpxchg from a volatile memory |
| 575 | /// location. |
| 576 | /// |
| 577 | bool isVolatile() const { return getSubclassData<VolatileField>(); } |
| 578 | |
| 579 | /// Specify whether this is a volatile cmpxchg. |
| 580 | /// |
| 581 | void setVolatile(bool V) { setSubclassData<VolatileField>(V); } |
| 582 | |
| 583 | /// Return true if this cmpxchg may spuriously fail. |
| 584 | bool isWeak() const { return getSubclassData<WeakField>(); } |
| 585 | |
| 586 | void setWeak(bool IsWeak) { setSubclassData<WeakField>(IsWeak); } |
| 587 | |
| 588 | /// Transparently provide more efficient getOperand methods. |
| 589 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 590 | |
| 591 | static bool isValidSuccessOrdering(AtomicOrdering Ordering) { |
| 592 | return Ordering != AtomicOrdering::NotAtomic && |
| 593 | Ordering != AtomicOrdering::Unordered; |
| 594 | } |
| 595 | |
| 596 | static bool isValidFailureOrdering(AtomicOrdering Ordering) { |
| 597 | return Ordering != AtomicOrdering::NotAtomic && |
| 598 | Ordering != AtomicOrdering::Unordered && |
| 599 | Ordering != AtomicOrdering::AcquireRelease && |
| 600 | Ordering != AtomicOrdering::Release; |
| 601 | } |
| 602 | |
| 603 | /// Returns the success ordering constraint of this cmpxchg instruction. |
| 604 | AtomicOrdering getSuccessOrdering() const { |
| 605 | return getSubclassData<SuccessOrderingField>(); |
| 606 | } |
| 607 | |
| 608 | /// Sets the success ordering constraint of this cmpxchg instruction. |
| 609 | void setSuccessOrdering(AtomicOrdering Ordering) { |
| 610 | assert(isValidSuccessOrdering(Ordering) &&((void)0) |
| 611 | "invalid CmpXchg success ordering")((void)0); |
| 612 | setSubclassData<SuccessOrderingField>(Ordering); |
| 613 | } |
| 614 | |
| 615 | /// Returns the failure ordering constraint of this cmpxchg instruction. |
| 616 | AtomicOrdering getFailureOrdering() const { |
| 617 | return getSubclassData<FailureOrderingField>(); |
| 618 | } |
| 619 | |
| 620 | /// Sets the failure ordering constraint of this cmpxchg instruction. |
| 621 | void setFailureOrdering(AtomicOrdering Ordering) { |
| 622 | assert(isValidFailureOrdering(Ordering) &&((void)0) |
| 623 | "invalid CmpXchg failure ordering")((void)0); |
| 624 | setSubclassData<FailureOrderingField>(Ordering); |
| 625 | } |
| 626 | |
| 627 | /// Returns a single ordering which is at least as strong as both the |
| 628 | /// success and failure orderings for this cmpxchg. |
| 629 | AtomicOrdering getMergedOrdering() const { |
| 630 | if (getFailureOrdering() == AtomicOrdering::SequentiallyConsistent) |
| 631 | return AtomicOrdering::SequentiallyConsistent; |
| 632 | if (getFailureOrdering() == AtomicOrdering::Acquire) { |
| 633 | if (getSuccessOrdering() == AtomicOrdering::Monotonic) |
| 634 | return AtomicOrdering::Acquire; |
| 635 | if (getSuccessOrdering() == AtomicOrdering::Release) |
| 636 | return AtomicOrdering::AcquireRelease; |
| 637 | } |
| 638 | return getSuccessOrdering(); |
| 639 | } |
| 640 | |
| 641 | /// Returns the synchronization scope ID of this cmpxchg instruction. |
| 642 | SyncScope::ID getSyncScopeID() const { |
| 643 | return SSID; |
| 644 | } |
| 645 | |
| 646 | /// Sets the synchronization scope ID of this cmpxchg instruction. |
| 647 | void setSyncScopeID(SyncScope::ID SSID) { |
| 648 | this->SSID = SSID; |
| 649 | } |
| 650 | |
| 651 | Value *getPointerOperand() { return getOperand(0); } |
| 652 | const Value *getPointerOperand() const { return getOperand(0); } |
| 653 | static unsigned getPointerOperandIndex() { return 0U; } |
| 654 | |
| 655 | Value *getCompareOperand() { return getOperand(1); } |
| 656 | const Value *getCompareOperand() const { return getOperand(1); } |
| 657 | |
| 658 | Value *getNewValOperand() { return getOperand(2); } |
| 659 | const Value *getNewValOperand() const { return getOperand(2); } |
| 660 | |
| 661 | /// Returns the address space of the pointer operand. |
| 662 | unsigned getPointerAddressSpace() const { |
| 663 | return getPointerOperand()->getType()->getPointerAddressSpace(); |
| 664 | } |
| 665 | |
| 666 | /// Returns the strongest permitted ordering on failure, given the |
| 667 | /// desired ordering on success. |
| 668 | /// |
| 669 | /// If the comparison in a cmpxchg operation fails, there is no atomic store |
| 670 | /// so release semantics cannot be provided. So this function drops explicit |
| 671 | /// Release requests from the AtomicOrdering. A SequentiallyConsistent |
| 672 | /// operation would remain SequentiallyConsistent. |
| 673 | static AtomicOrdering |
| 674 | getStrongestFailureOrdering(AtomicOrdering SuccessOrdering) { |
| 675 | switch (SuccessOrdering) { |
| 676 | default: |
| 677 | llvm_unreachable("invalid cmpxchg success ordering")__builtin_unreachable(); |
| 678 | case AtomicOrdering::Release: |
| 679 | case AtomicOrdering::Monotonic: |
| 680 | return AtomicOrdering::Monotonic; |
| 681 | case AtomicOrdering::AcquireRelease: |
| 682 | case AtomicOrdering::Acquire: |
| 683 | return AtomicOrdering::Acquire; |
| 684 | case AtomicOrdering::SequentiallyConsistent: |
| 685 | return AtomicOrdering::SequentiallyConsistent; |
| 686 | } |
| 687 | } |
| 688 | |
| 689 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 690 | static bool classof(const Instruction *I) { |
| 691 | return I->getOpcode() == Instruction::AtomicCmpXchg; |
| 692 | } |
| 693 | static bool classof(const Value *V) { |
| 694 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 695 | } |
| 696 | |
| 697 | private: |
| 698 | // Shadow Instruction::setInstructionSubclassData with a private forwarding |
| 699 | // method so that subclasses cannot accidentally use it. |
| 700 | template <typename Bitfield> |
| 701 | void setSubclassData(typename Bitfield::Type Value) { |
| 702 | Instruction::setSubclassData<Bitfield>(Value); |
| 703 | } |
| 704 | |
| 705 | /// The synchronization scope ID of this cmpxchg instruction. Not quite |
| 706 | /// enough room in SubClassData for everything, so synchronization scope ID |
| 707 | /// gets its own field. |
| 708 | SyncScope::ID SSID; |
| 709 | }; |
| 710 | |
| 711 | template <> |
| 712 | struct OperandTraits<AtomicCmpXchgInst> : |
| 713 | public FixedNumOperandTraits<AtomicCmpXchgInst, 3> { |
| 714 | }; |
| 715 | |
| 716 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(AtomicCmpXchgInst, Value)AtomicCmpXchgInst::op_iterator AtomicCmpXchgInst::op_begin() { return OperandTraits<AtomicCmpXchgInst>::op_begin(this ); } AtomicCmpXchgInst::const_op_iterator AtomicCmpXchgInst:: op_begin() const { return OperandTraits<AtomicCmpXchgInst> ::op_begin(const_cast<AtomicCmpXchgInst*>(this)); } AtomicCmpXchgInst ::op_iterator AtomicCmpXchgInst::op_end() { return OperandTraits <AtomicCmpXchgInst>::op_end(this); } AtomicCmpXchgInst:: const_op_iterator AtomicCmpXchgInst::op_end() const { return OperandTraits <AtomicCmpXchgInst>::op_end(const_cast<AtomicCmpXchgInst *>(this)); } Value *AtomicCmpXchgInst::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null<Value >( OperandTraits<AtomicCmpXchgInst>::op_begin(const_cast <AtomicCmpXchgInst*>(this))[i_nocapture].get()); } void AtomicCmpXchgInst::setOperand(unsigned i_nocapture, Value *Val_nocapture ) { ((void)0); OperandTraits<AtomicCmpXchgInst>::op_begin (this)[i_nocapture] = Val_nocapture; } unsigned AtomicCmpXchgInst ::getNumOperands() const { return OperandTraits<AtomicCmpXchgInst >::operands(this); } template <int Idx_nocapture> Use &AtomicCmpXchgInst::Op() { return this->OpFrom<Idx_nocapture >(this); } template <int Idx_nocapture> const Use & AtomicCmpXchgInst::Op() const { return this->OpFrom<Idx_nocapture >(this); } |
| 717 | |
| 718 | //===----------------------------------------------------------------------===// |
| 719 | // AtomicRMWInst Class |
| 720 | //===----------------------------------------------------------------------===// |
| 721 | |
| 722 | /// an instruction that atomically reads a memory location, |
| 723 | /// combines it with another value, and then stores the result back. Returns |
| 724 | /// the old value. |
| 725 | /// |
| 726 | class AtomicRMWInst : public Instruction { |
| 727 | protected: |
| 728 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 729 | friend class Instruction; |
| 730 | |
| 731 | AtomicRMWInst *cloneImpl() const; |
| 732 | |
| 733 | public: |
| 734 | /// This enumeration lists the possible modifications atomicrmw can make. In |
| 735 | /// the descriptions, 'p' is the pointer to the instruction's memory location, |
| 736 | /// 'old' is the initial value of *p, and 'v' is the other value passed to the |
| 737 | /// instruction. These instructions always return 'old'. |
| 738 | enum BinOp : unsigned { |
| 739 | /// *p = v |
| 740 | Xchg, |
| 741 | /// *p = old + v |
| 742 | Add, |
| 743 | /// *p = old - v |
| 744 | Sub, |
| 745 | /// *p = old & v |
| 746 | And, |
| 747 | /// *p = ~(old & v) |
| 748 | Nand, |
| 749 | /// *p = old | v |
| 750 | Or, |
| 751 | /// *p = old ^ v |
| 752 | Xor, |
| 753 | /// *p = old >signed v ? old : v |
| 754 | Max, |
| 755 | /// *p = old <signed v ? old : v |
| 756 | Min, |
| 757 | /// *p = old >unsigned v ? old : v |
| 758 | UMax, |
| 759 | /// *p = old <unsigned v ? old : v |
| 760 | UMin, |
| 761 | |
| 762 | /// *p = old + v |
| 763 | FAdd, |
| 764 | |
| 765 | /// *p = old - v |
| 766 | FSub, |
| 767 | |
| 768 | FIRST_BINOP = Xchg, |
| 769 | LAST_BINOP = FSub, |
| 770 | BAD_BINOP |
| 771 | }; |
| 772 | |
| 773 | private: |
| 774 | template <unsigned Offset> |
| 775 | using AtomicOrderingBitfieldElement = |
| 776 | typename Bitfield::Element<AtomicOrdering, Offset, 3, |
| 777 | AtomicOrdering::LAST>; |
| 778 | |
| 779 | template <unsigned Offset> |
| 780 | using BinOpBitfieldElement = |
| 781 | typename Bitfield::Element<BinOp, Offset, 4, BinOp::LAST_BINOP>; |
| 782 | |
| 783 | public: |
| 784 | AtomicRMWInst(BinOp Operation, Value *Ptr, Value *Val, Align Alignment, |
| 785 | AtomicOrdering Ordering, SyncScope::ID SSID, |
| 786 | Instruction *InsertBefore = nullptr); |
| 787 | AtomicRMWInst(BinOp Operation, Value *Ptr, Value *Val, Align Alignment, |
| 788 | AtomicOrdering Ordering, SyncScope::ID SSID, |
| 789 | BasicBlock *InsertAtEnd); |
| 790 | |
| 791 | // allocate space for exactly two operands |
| 792 | void *operator new(size_t S) { return User::operator new(S, 2); } |
| 793 | void operator delete(void *Ptr) { User::operator delete(Ptr); } |
| 794 | |
| 795 | using VolatileField = BoolBitfieldElementT<0>; |
| 796 | using AtomicOrderingField = |
| 797 | AtomicOrderingBitfieldElementT<VolatileField::NextBit>; |
| 798 | using OperationField = BinOpBitfieldElement<AtomicOrderingField::NextBit>; |
| 799 | using AlignmentField = AlignmentBitfieldElementT<OperationField::NextBit>; |
| 800 | static_assert(Bitfield::areContiguous<VolatileField, AtomicOrderingField, |
| 801 | OperationField, AlignmentField>(), |
| 802 | "Bitfields must be contiguous"); |
| 803 | |
| 804 | BinOp getOperation() const { return getSubclassData<OperationField>(); } |
| 805 | |
| 806 | static StringRef getOperationName(BinOp Op); |
| 807 | |
| 808 | static bool isFPOperation(BinOp Op) { |
| 809 | switch (Op) { |
| 810 | case AtomicRMWInst::FAdd: |
| 811 | case AtomicRMWInst::FSub: |
| 812 | return true; |
| 813 | default: |
| 814 | return false; |
| 815 | } |
| 816 | } |
| 817 | |
| 818 | void setOperation(BinOp Operation) { |
| 819 | setSubclassData<OperationField>(Operation); |
| 820 | } |
| 821 | |
| 822 | /// Return the alignment of the memory that is being allocated by the |
| 823 | /// instruction. |
| 824 | Align getAlign() const { |
| 825 | return Align(1ULL << getSubclassData<AlignmentField>()); |
| 826 | } |
| 827 | |
| 828 | void setAlignment(Align Align) { |
| 829 | setSubclassData<AlignmentField>(Log2(Align)); |
| 830 | } |
| 831 | |
| 832 | /// Return true if this is a RMW on a volatile memory location. |
| 833 | /// |
| 834 | bool isVolatile() const { return getSubclassData<VolatileField>(); } |
| 835 | |
| 836 | /// Specify whether this is a volatile RMW or not. |
| 837 | /// |
| 838 | void setVolatile(bool V) { setSubclassData<VolatileField>(V); } |
| 839 | |
| 840 | /// Transparently provide more efficient getOperand methods. |
| 841 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 842 | |
| 843 | /// Returns the ordering constraint of this rmw instruction. |
| 844 | AtomicOrdering getOrdering() const { |
| 845 | return getSubclassData<AtomicOrderingField>(); |
| 846 | } |
| 847 | |
| 848 | /// Sets the ordering constraint of this rmw instruction. |
| 849 | void setOrdering(AtomicOrdering Ordering) { |
| 850 | assert(Ordering != AtomicOrdering::NotAtomic &&((void)0) |
| 851 | "atomicrmw instructions can only be atomic.")((void)0); |
| 852 | setSubclassData<AtomicOrderingField>(Ordering); |
| 853 | } |
| 854 | |
| 855 | /// Returns the synchronization scope ID of this rmw instruction. |
| 856 | SyncScope::ID getSyncScopeID() const { |
| 857 | return SSID; |
| 858 | } |
| 859 | |
| 860 | /// Sets the synchronization scope ID of this rmw instruction. |
| 861 | void setSyncScopeID(SyncScope::ID SSID) { |
| 862 | this->SSID = SSID; |
| 863 | } |
| 864 | |
| 865 | Value *getPointerOperand() { return getOperand(0); } |
| 866 | const Value *getPointerOperand() const { return getOperand(0); } |
| 867 | static unsigned getPointerOperandIndex() { return 0U; } |
| 868 | |
| 869 | Value *getValOperand() { return getOperand(1); } |
| 870 | const Value *getValOperand() const { return getOperand(1); } |
| 871 | |
| 872 | /// Returns the address space of the pointer operand. |
| 873 | unsigned getPointerAddressSpace() const { |
| 874 | return getPointerOperand()->getType()->getPointerAddressSpace(); |
| 875 | } |
| 876 | |
| 877 | bool isFloatingPointOperation() const { |
| 878 | return isFPOperation(getOperation()); |
| 879 | } |
| 880 | |
| 881 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 882 | static bool classof(const Instruction *I) { |
| 883 | return I->getOpcode() == Instruction::AtomicRMW; |
| 884 | } |
| 885 | static bool classof(const Value *V) { |
| 886 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 887 | } |
| 888 | |
| 889 | private: |
| 890 | void Init(BinOp Operation, Value *Ptr, Value *Val, Align Align, |
| 891 | AtomicOrdering Ordering, SyncScope::ID SSID); |
| 892 | |
| 893 | // Shadow Instruction::setInstructionSubclassData with a private forwarding |
| 894 | // method so that subclasses cannot accidentally use it. |
| 895 | template <typename Bitfield> |
| 896 | void setSubclassData(typename Bitfield::Type Value) { |
| 897 | Instruction::setSubclassData<Bitfield>(Value); |
| 898 | } |
| 899 | |
| 900 | /// The synchronization scope ID of this rmw instruction. Not quite enough |
| 901 | /// room in SubClassData for everything, so synchronization scope ID gets its |
| 902 | /// own field. |
| 903 | SyncScope::ID SSID; |
| 904 | }; |
| 905 | |
| 906 | template <> |
| 907 | struct OperandTraits<AtomicRMWInst> |
| 908 | : public FixedNumOperandTraits<AtomicRMWInst,2> { |
| 909 | }; |
| 910 | |
| 911 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(AtomicRMWInst, Value)AtomicRMWInst::op_iterator AtomicRMWInst::op_begin() { return OperandTraits<AtomicRMWInst>::op_begin(this); } AtomicRMWInst ::const_op_iterator AtomicRMWInst::op_begin() const { return OperandTraits <AtomicRMWInst>::op_begin(const_cast<AtomicRMWInst*> (this)); } AtomicRMWInst::op_iterator AtomicRMWInst::op_end() { return OperandTraits<AtomicRMWInst>::op_end(this); } AtomicRMWInst::const_op_iterator AtomicRMWInst::op_end() const { return OperandTraits<AtomicRMWInst>::op_end(const_cast <AtomicRMWInst*>(this)); } Value *AtomicRMWInst::getOperand (unsigned i_nocapture) const { ((void)0); return cast_or_null <Value>( OperandTraits<AtomicRMWInst>::op_begin(const_cast <AtomicRMWInst*>(this))[i_nocapture].get()); } void AtomicRMWInst ::setOperand(unsigned i_nocapture, Value *Val_nocapture) { (( void)0); OperandTraits<AtomicRMWInst>::op_begin(this)[i_nocapture ] = Val_nocapture; } unsigned AtomicRMWInst::getNumOperands() const { return OperandTraits<AtomicRMWInst>::operands( this); } template <int Idx_nocapture> Use &AtomicRMWInst ::Op() { return this->OpFrom<Idx_nocapture>(this); } template <int Idx_nocapture> const Use &AtomicRMWInst ::Op() const { return this->OpFrom<Idx_nocapture>(this ); } |
| 912 | |
| 913 | //===----------------------------------------------------------------------===// |
| 914 | // GetElementPtrInst Class |
| 915 | //===----------------------------------------------------------------------===// |
| 916 | |
| 917 | // checkGEPType - Simple wrapper function to give a better assertion failure |
| 918 | // message on bad indexes for a gep instruction. |
| 919 | // |
| 920 | inline Type *checkGEPType(Type *Ty) { |
| 921 | assert(Ty && "Invalid GetElementPtrInst indices for type!")((void)0); |
| 922 | return Ty; |
| 923 | } |
| 924 | |
| 925 | /// an instruction for type-safe pointer arithmetic to |
| 926 | /// access elements of arrays and structs |
| 927 | /// |
| 928 | class GetElementPtrInst : public Instruction { |
| 929 | Type *SourceElementType; |
| 930 | Type *ResultElementType; |
| 931 | |
| 932 | GetElementPtrInst(const GetElementPtrInst &GEPI); |
| 933 | |
| 934 | /// Constructors - Create a getelementptr instruction with a base pointer an |
| 935 | /// list of indices. The first ctor can optionally insert before an existing |
| 936 | /// instruction, the second appends the new instruction to the specified |
| 937 | /// BasicBlock. |
| 938 | inline GetElementPtrInst(Type *PointeeType, Value *Ptr, |
| 939 | ArrayRef<Value *> IdxList, unsigned Values, |
| 940 | const Twine &NameStr, Instruction *InsertBefore); |
| 941 | inline GetElementPtrInst(Type *PointeeType, Value *Ptr, |
| 942 | ArrayRef<Value *> IdxList, unsigned Values, |
| 943 | const Twine &NameStr, BasicBlock *InsertAtEnd); |
| 944 | |
| 945 | void init(Value *Ptr, ArrayRef<Value *> IdxList, const Twine &NameStr); |
| 946 | |
| 947 | protected: |
| 948 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 949 | friend class Instruction; |
| 950 | |
| 951 | GetElementPtrInst *cloneImpl() const; |
| 952 | |
| 953 | public: |
| 954 | static GetElementPtrInst *Create(Type *PointeeType, Value *Ptr, |
| 955 | ArrayRef<Value *> IdxList, |
| 956 | const Twine &NameStr = "", |
| 957 | Instruction *InsertBefore = nullptr) { |
| 958 | unsigned Values = 1 + unsigned(IdxList.size()); |
| 959 | assert(PointeeType && "Must specify element type")((void)0); |
| 960 | assert(cast<PointerType>(Ptr->getType()->getScalarType())((void)0) |
| 961 | ->isOpaqueOrPointeeTypeMatches(PointeeType))((void)0); |
| 962 | return new (Values) GetElementPtrInst(PointeeType, Ptr, IdxList, Values, |
| 963 | NameStr, InsertBefore); |
| 964 | } |
| 965 | |
| 966 | static GetElementPtrInst *Create(Type *PointeeType, Value *Ptr, |
| 967 | ArrayRef<Value *> IdxList, |
| 968 | const Twine &NameStr, |
| 969 | BasicBlock *InsertAtEnd) { |
| 970 | unsigned Values = 1 + unsigned(IdxList.size()); |
| 971 | assert(PointeeType && "Must specify element type")((void)0); |
| 972 | assert(cast<PointerType>(Ptr->getType()->getScalarType())((void)0) |
| 973 | ->isOpaqueOrPointeeTypeMatches(PointeeType))((void)0); |
| 974 | return new (Values) GetElementPtrInst(PointeeType, Ptr, IdxList, Values, |
| 975 | NameStr, InsertAtEnd); |
| 976 | } |
| 977 | |
| 978 | LLVM_ATTRIBUTE_DEPRECATED(static GetElementPtrInst *CreateInBounds([[deprecated("Use the version with explicit element type instead" )]] static GetElementPtrInst *CreateInBounds( Value *Ptr, ArrayRef <Value *> IdxList, const Twine &NameStr = "", Instruction *InsertBefore = nullptr) |
| 979 | Value *Ptr, ArrayRef<Value *> IdxList, const Twine &NameStr = "",[[deprecated("Use the version with explicit element type instead" )]] static GetElementPtrInst *CreateInBounds( Value *Ptr, ArrayRef <Value *> IdxList, const Twine &NameStr = "", Instruction *InsertBefore = nullptr) |
| 980 | Instruction *InsertBefore = nullptr),[[deprecated("Use the version with explicit element type instead" )]] static GetElementPtrInst *CreateInBounds( Value *Ptr, ArrayRef <Value *> IdxList, const Twine &NameStr = "", Instruction *InsertBefore = nullptr) |
| 981 | "Use the version with explicit element type instead")[[deprecated("Use the version with explicit element type instead" )]] static GetElementPtrInst *CreateInBounds( Value *Ptr, ArrayRef <Value *> IdxList, const Twine &NameStr = "", Instruction *InsertBefore = nullptr) { |
| 982 | return CreateInBounds( |
| 983 | Ptr->getType()->getScalarType()->getPointerElementType(), Ptr, IdxList, |
| 984 | NameStr, InsertBefore); |
| 985 | } |
| 986 | |
| 987 | /// Create an "inbounds" getelementptr. See the documentation for the |
| 988 | /// "inbounds" flag in LangRef.html for details. |
| 989 | static GetElementPtrInst * |
| 990 | CreateInBounds(Type *PointeeType, Value *Ptr, ArrayRef<Value *> IdxList, |
| 991 | const Twine &NameStr = "", |
| 992 | Instruction *InsertBefore = nullptr) { |
| 993 | GetElementPtrInst *GEP = |
| 994 | Create(PointeeType, Ptr, IdxList, NameStr, InsertBefore); |
| 995 | GEP->setIsInBounds(true); |
| 996 | return GEP; |
| 997 | } |
| 998 | |
| 999 | LLVM_ATTRIBUTE_DEPRECATED(static GetElementPtrInst *CreateInBounds([[deprecated("Use the version with explicit element type instead" )]] static GetElementPtrInst *CreateInBounds( Value *Ptr, ArrayRef <Value *> IdxList, const Twine &NameStr, BasicBlock *InsertAtEnd) |
| 1000 | Value *Ptr, ArrayRef<Value *> IdxList, const Twine &NameStr,[[deprecated("Use the version with explicit element type instead" )]] static GetElementPtrInst *CreateInBounds( Value *Ptr, ArrayRef <Value *> IdxList, const Twine &NameStr, BasicBlock *InsertAtEnd) |
| 1001 | BasicBlock *InsertAtEnd),[[deprecated("Use the version with explicit element type instead" )]] static GetElementPtrInst *CreateInBounds( Value *Ptr, ArrayRef <Value *> IdxList, const Twine &NameStr, BasicBlock *InsertAtEnd) |
| 1002 | "Use the version with explicit element type instead")[[deprecated("Use the version with explicit element type instead" )]] static GetElementPtrInst *CreateInBounds( Value *Ptr, ArrayRef <Value *> IdxList, const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 1003 | return CreateInBounds( |
| 1004 | Ptr->getType()->getScalarType()->getPointerElementType(), Ptr, IdxList, |
| 1005 | NameStr, InsertAtEnd); |
| 1006 | } |
| 1007 | |
| 1008 | static GetElementPtrInst *CreateInBounds(Type *PointeeType, Value *Ptr, |
| 1009 | ArrayRef<Value *> IdxList, |
| 1010 | const Twine &NameStr, |
| 1011 | BasicBlock *InsertAtEnd) { |
| 1012 | GetElementPtrInst *GEP = |
| 1013 | Create(PointeeType, Ptr, IdxList, NameStr, InsertAtEnd); |
| 1014 | GEP->setIsInBounds(true); |
| 1015 | return GEP; |
| 1016 | } |
| 1017 | |
| 1018 | /// Transparently provide more efficient getOperand methods. |
| 1019 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 1020 | |
| 1021 | Type *getSourceElementType() const { return SourceElementType; } |
| 1022 | |
| 1023 | void setSourceElementType(Type *Ty) { SourceElementType = Ty; } |
| 1024 | void setResultElementType(Type *Ty) { ResultElementType = Ty; } |
| 1025 | |
| 1026 | Type *getResultElementType() const { |
| 1027 | assert(cast<PointerType>(getType()->getScalarType())((void)0) |
| 1028 | ->isOpaqueOrPointeeTypeMatches(ResultElementType))((void)0); |
| 1029 | return ResultElementType; |
| 1030 | } |
| 1031 | |
| 1032 | /// Returns the address space of this instruction's pointer type. |
| 1033 | unsigned getAddressSpace() const { |
| 1034 | // Note that this is always the same as the pointer operand's address space |
| 1035 | // and that is cheaper to compute, so cheat here. |
| 1036 | return getPointerAddressSpace(); |
| 1037 | } |
| 1038 | |
| 1039 | /// Returns the result type of a getelementptr with the given source |
| 1040 | /// element type and indexes. |
| 1041 | /// |
| 1042 | /// Null is returned if the indices are invalid for the specified |
| 1043 | /// source element type. |
| 1044 | static Type *getIndexedType(Type *Ty, ArrayRef<Value *> IdxList); |
| 1045 | static Type *getIndexedType(Type *Ty, ArrayRef<Constant *> IdxList); |
| 1046 | static Type *getIndexedType(Type *Ty, ArrayRef<uint64_t> IdxList); |
| 1047 | |
| 1048 | /// Return the type of the element at the given index of an indexable |
| 1049 | /// type. This is equivalent to "getIndexedType(Agg, {Zero, Idx})". |
| 1050 | /// |
| 1051 | /// Returns null if the type can't be indexed, or the given index is not |
| 1052 | /// legal for the given type. |
| 1053 | static Type *getTypeAtIndex(Type *Ty, Value *Idx); |
| 1054 | static Type *getTypeAtIndex(Type *Ty, uint64_t Idx); |
| 1055 | |
| 1056 | inline op_iterator idx_begin() { return op_begin()+1; } |
| 1057 | inline const_op_iterator idx_begin() const { return op_begin()+1; } |
| 1058 | inline op_iterator idx_end() { return op_end(); } |
| 1059 | inline const_op_iterator idx_end() const { return op_end(); } |
| 1060 | |
| 1061 | inline iterator_range<op_iterator> indices() { |
| 1062 | return make_range(idx_begin(), idx_end()); |
| 1063 | } |
| 1064 | |
| 1065 | inline iterator_range<const_op_iterator> indices() const { |
| 1066 | return make_range(idx_begin(), idx_end()); |
| 1067 | } |
| 1068 | |
| 1069 | Value *getPointerOperand() { |
| 1070 | return getOperand(0); |
| 1071 | } |
| 1072 | const Value *getPointerOperand() const { |
| 1073 | return getOperand(0); |
| 1074 | } |
| 1075 | static unsigned getPointerOperandIndex() { |
| 1076 | return 0U; // get index for modifying correct operand. |
| 1077 | } |
| 1078 | |
| 1079 | /// Method to return the pointer operand as a |
| 1080 | /// PointerType. |
| 1081 | Type *getPointerOperandType() const { |
| 1082 | return getPointerOperand()->getType(); |
| 1083 | } |
| 1084 | |
| 1085 | /// Returns the address space of the pointer operand. |
| 1086 | unsigned getPointerAddressSpace() const { |
| 1087 | return getPointerOperandType()->getPointerAddressSpace(); |
| 1088 | } |
| 1089 | |
| 1090 | /// Returns the pointer type returned by the GEP |
| 1091 | /// instruction, which may be a vector of pointers. |
| 1092 | static Type *getGEPReturnType(Type *ElTy, Value *Ptr, |
| 1093 | ArrayRef<Value *> IdxList) { |
| 1094 | PointerType *OrigPtrTy = cast<PointerType>(Ptr->getType()->getScalarType()); |
| 1095 | unsigned AddrSpace = OrigPtrTy->getAddressSpace(); |
| 1096 | Type *ResultElemTy = checkGEPType(getIndexedType(ElTy, IdxList)); |
| 1097 | Type *PtrTy = OrigPtrTy->isOpaque() |
| 1098 | ? PointerType::get(OrigPtrTy->getContext(), AddrSpace) |
| 1099 | : PointerType::get(ResultElemTy, AddrSpace); |
| 1100 | // Vector GEP |
| 1101 | if (auto *PtrVTy = dyn_cast<VectorType>(Ptr->getType())) { |
| 1102 | ElementCount EltCount = PtrVTy->getElementCount(); |
| 1103 | return VectorType::get(PtrTy, EltCount); |
| 1104 | } |
| 1105 | for (Value *Index : IdxList) |
| 1106 | if (auto *IndexVTy = dyn_cast<VectorType>(Index->getType())) { |
| 1107 | ElementCount EltCount = IndexVTy->getElementCount(); |
| 1108 | return VectorType::get(PtrTy, EltCount); |
| 1109 | } |
| 1110 | // Scalar GEP |
| 1111 | return PtrTy; |
| 1112 | } |
| 1113 | |
| 1114 | unsigned getNumIndices() const { // Note: always non-negative |
| 1115 | return getNumOperands() - 1; |
| 1116 | } |
| 1117 | |
| 1118 | bool hasIndices() const { |
| 1119 | return getNumOperands() > 1; |
| 1120 | } |
| 1121 | |
| 1122 | /// Return true if all of the indices of this GEP are |
| 1123 | /// zeros. If so, the result pointer and the first operand have the same |
| 1124 | /// value, just potentially different types. |
| 1125 | bool hasAllZeroIndices() const; |
| 1126 | |
| 1127 | /// Return true if all of the indices of this GEP are |
| 1128 | /// constant integers. If so, the result pointer and the first operand have |
| 1129 | /// a constant offset between them. |
| 1130 | bool hasAllConstantIndices() const; |
| 1131 | |
| 1132 | /// Set or clear the inbounds flag on this GEP instruction. |
| 1133 | /// See LangRef.html for the meaning of inbounds on a getelementptr. |
| 1134 | void setIsInBounds(bool b = true); |
| 1135 | |
| 1136 | /// Determine whether the GEP has the inbounds flag. |
| 1137 | bool isInBounds() const; |
| 1138 | |
| 1139 | /// Accumulate the constant address offset of this GEP if possible. |
| 1140 | /// |
| 1141 | /// This routine accepts an APInt into which it will accumulate the constant |
| 1142 | /// offset of this GEP if the GEP is in fact constant. If the GEP is not |
| 1143 | /// all-constant, it returns false and the value of the offset APInt is |
| 1144 | /// undefined (it is *not* preserved!). The APInt passed into this routine |
| 1145 | /// must be at least as wide as the IntPtr type for the address space of |
| 1146 | /// the base GEP pointer. |
| 1147 | bool accumulateConstantOffset(const DataLayout &DL, APInt &Offset) const; |
| 1148 | bool collectOffset(const DataLayout &DL, unsigned BitWidth, |
| 1149 | MapVector<Value *, APInt> &VariableOffsets, |
| 1150 | APInt &ConstantOffset) const; |
| 1151 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 1152 | static bool classof(const Instruction *I) { |
| 1153 | return (I->getOpcode() == Instruction::GetElementPtr); |
| 1154 | } |
| 1155 | static bool classof(const Value *V) { |
| 1156 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 1157 | } |
| 1158 | }; |
| 1159 | |
| 1160 | template <> |
| 1161 | struct OperandTraits<GetElementPtrInst> : |
| 1162 | public VariadicOperandTraits<GetElementPtrInst, 1> { |
| 1163 | }; |
| 1164 | |
| 1165 | GetElementPtrInst::GetElementPtrInst(Type *PointeeType, Value *Ptr, |
| 1166 | ArrayRef<Value *> IdxList, unsigned Values, |
| 1167 | const Twine &NameStr, |
| 1168 | Instruction *InsertBefore) |
| 1169 | : Instruction(getGEPReturnType(PointeeType, Ptr, IdxList), GetElementPtr, |
| 1170 | OperandTraits<GetElementPtrInst>::op_end(this) - Values, |
| 1171 | Values, InsertBefore), |
| 1172 | SourceElementType(PointeeType), |
| 1173 | ResultElementType(getIndexedType(PointeeType, IdxList)) { |
| 1174 | assert(cast<PointerType>(getType()->getScalarType())((void)0) |
| 1175 | ->isOpaqueOrPointeeTypeMatches(ResultElementType))((void)0); |
| 1176 | init(Ptr, IdxList, NameStr); |
| 1177 | } |
| 1178 | |
| 1179 | GetElementPtrInst::GetElementPtrInst(Type *PointeeType, Value *Ptr, |
| 1180 | ArrayRef<Value *> IdxList, unsigned Values, |
| 1181 | const Twine &NameStr, |
| 1182 | BasicBlock *InsertAtEnd) |
| 1183 | : Instruction(getGEPReturnType(PointeeType, Ptr, IdxList), GetElementPtr, |
| 1184 | OperandTraits<GetElementPtrInst>::op_end(this) - Values, |
| 1185 | Values, InsertAtEnd), |
| 1186 | SourceElementType(PointeeType), |
| 1187 | ResultElementType(getIndexedType(PointeeType, IdxList)) { |
| 1188 | assert(cast<PointerType>(getType()->getScalarType())((void)0) |
| 1189 | ->isOpaqueOrPointeeTypeMatches(ResultElementType))((void)0); |
| 1190 | init(Ptr, IdxList, NameStr); |
| 1191 | } |
| 1192 | |
| 1193 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(GetElementPtrInst, Value)GetElementPtrInst::op_iterator GetElementPtrInst::op_begin() { return OperandTraits<GetElementPtrInst>::op_begin(this ); } GetElementPtrInst::const_op_iterator GetElementPtrInst:: op_begin() const { return OperandTraits<GetElementPtrInst> ::op_begin(const_cast<GetElementPtrInst*>(this)); } GetElementPtrInst ::op_iterator GetElementPtrInst::op_end() { return OperandTraits <GetElementPtrInst>::op_end(this); } GetElementPtrInst:: const_op_iterator GetElementPtrInst::op_end() const { return OperandTraits <GetElementPtrInst>::op_end(const_cast<GetElementPtrInst *>(this)); } Value *GetElementPtrInst::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null<Value >( OperandTraits<GetElementPtrInst>::op_begin(const_cast <GetElementPtrInst*>(this))[i_nocapture].get()); } void GetElementPtrInst::setOperand(unsigned i_nocapture, Value *Val_nocapture ) { ((void)0); OperandTraits<GetElementPtrInst>::op_begin (this)[i_nocapture] = Val_nocapture; } unsigned GetElementPtrInst ::getNumOperands() const { return OperandTraits<GetElementPtrInst >::operands(this); } template <int Idx_nocapture> Use &GetElementPtrInst::Op() { return this->OpFrom<Idx_nocapture >(this); } template <int Idx_nocapture> const Use & GetElementPtrInst::Op() const { return this->OpFrom<Idx_nocapture >(this); } |
| 1194 | |
| 1195 | //===----------------------------------------------------------------------===// |
| 1196 | // ICmpInst Class |
| 1197 | //===----------------------------------------------------------------------===// |
| 1198 | |
| 1199 | /// This instruction compares its operands according to the predicate given |
| 1200 | /// to the constructor. It only operates on integers or pointers. The operands |
| 1201 | /// must be identical types. |
| 1202 | /// Represent an integer comparison operator. |
| 1203 | class ICmpInst: public CmpInst { |
| 1204 | void AssertOK() { |
| 1205 | assert(isIntPredicate() &&((void)0) |
| 1206 | "Invalid ICmp predicate value")((void)0); |
| 1207 | assert(getOperand(0)->getType() == getOperand(1)->getType() &&((void)0) |
| 1208 | "Both operands to ICmp instruction are not of the same type!")((void)0); |
| 1209 | // Check that the operands are the right type |
| 1210 | assert((getOperand(0)->getType()->isIntOrIntVectorTy() ||((void)0) |
| 1211 | getOperand(0)->getType()->isPtrOrPtrVectorTy()) &&((void)0) |
| 1212 | "Invalid operand types for ICmp instruction")((void)0); |
| 1213 | } |
| 1214 | |
| 1215 | protected: |
| 1216 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 1217 | friend class Instruction; |
| 1218 | |
| 1219 | /// Clone an identical ICmpInst |
| 1220 | ICmpInst *cloneImpl() const; |
| 1221 | |
| 1222 | public: |
| 1223 | /// Constructor with insert-before-instruction semantics. |
| 1224 | ICmpInst( |
| 1225 | Instruction *InsertBefore, ///< Where to insert |
| 1226 | Predicate pred, ///< The predicate to use for the comparison |
| 1227 | Value *LHS, ///< The left-hand-side of the expression |
| 1228 | Value *RHS, ///< The right-hand-side of the expression |
| 1229 | const Twine &NameStr = "" ///< Name of the instruction |
| 1230 | ) : CmpInst(makeCmpResultType(LHS->getType()), |
| 1231 | Instruction::ICmp, pred, LHS, RHS, NameStr, |
| 1232 | InsertBefore) { |
| 1233 | #ifndef NDEBUG1 |
| 1234 | AssertOK(); |
| 1235 | #endif |
| 1236 | } |
| 1237 | |
| 1238 | /// Constructor with insert-at-end semantics. |
| 1239 | ICmpInst( |
| 1240 | BasicBlock &InsertAtEnd, ///< Block to insert into. |
| 1241 | Predicate pred, ///< The predicate to use for the comparison |
| 1242 | Value *LHS, ///< The left-hand-side of the expression |
| 1243 | Value *RHS, ///< The right-hand-side of the expression |
| 1244 | const Twine &NameStr = "" ///< Name of the instruction |
| 1245 | ) : CmpInst(makeCmpResultType(LHS->getType()), |
| 1246 | Instruction::ICmp, pred, LHS, RHS, NameStr, |
| 1247 | &InsertAtEnd) { |
| 1248 | #ifndef NDEBUG1 |
| 1249 | AssertOK(); |
| 1250 | #endif |
| 1251 | } |
| 1252 | |
| 1253 | /// Constructor with no-insertion semantics |
| 1254 | ICmpInst( |
| 1255 | Predicate pred, ///< The predicate to use for the comparison |
| 1256 | Value *LHS, ///< The left-hand-side of the expression |
| 1257 | Value *RHS, ///< The right-hand-side of the expression |
| 1258 | const Twine &NameStr = "" ///< Name of the instruction |
| 1259 | ) : CmpInst(makeCmpResultType(LHS->getType()), |
| 1260 | Instruction::ICmp, pred, LHS, RHS, NameStr) { |
| 1261 | #ifndef NDEBUG1 |
| 1262 | AssertOK(); |
| 1263 | #endif |
| 1264 | } |
| 1265 | |
| 1266 | /// For example, EQ->EQ, SLE->SLE, UGT->SGT, etc. |
| 1267 | /// @returns the predicate that would be the result if the operand were |
| 1268 | /// regarded as signed. |
| 1269 | /// Return the signed version of the predicate |
| 1270 | Predicate getSignedPredicate() const { |
| 1271 | return getSignedPredicate(getPredicate()); |
| 1272 | } |
| 1273 | |
| 1274 | /// This is a static version that you can use without an instruction. |
| 1275 | /// Return the signed version of the predicate. |
| 1276 | static Predicate getSignedPredicate(Predicate pred); |
| 1277 | |
| 1278 | /// For example, EQ->EQ, SLE->ULE, UGT->UGT, etc. |
| 1279 | /// @returns the predicate that would be the result if the operand were |
| 1280 | /// regarded as unsigned. |
| 1281 | /// Return the unsigned version of the predicate |
| 1282 | Predicate getUnsignedPredicate() const { |
| 1283 | return getUnsignedPredicate(getPredicate()); |
| 1284 | } |
| 1285 | |
| 1286 | /// This is a static version that you can use without an instruction. |
| 1287 | /// Return the unsigned version of the predicate. |
| 1288 | static Predicate getUnsignedPredicate(Predicate pred); |
| 1289 | |
| 1290 | /// Return true if this predicate is either EQ or NE. This also |
| 1291 | /// tests for commutativity. |
| 1292 | static bool isEquality(Predicate P) { |
| 1293 | return P == ICMP_EQ || P == ICMP_NE; |
| 1294 | } |
| 1295 | |
| 1296 | /// Return true if this predicate is either EQ or NE. This also |
| 1297 | /// tests for commutativity. |
| 1298 | bool isEquality() const { |
| 1299 | return isEquality(getPredicate()); |
| 1300 | } |
| 1301 | |
| 1302 | /// @returns true if the predicate of this ICmpInst is commutative |
| 1303 | /// Determine if this relation is commutative. |
| 1304 | bool isCommutative() const { return isEquality(); } |
| 1305 | |
| 1306 | /// Return true if the predicate is relational (not EQ or NE). |
| 1307 | /// |
| 1308 | bool isRelational() const { |
| 1309 | return !isEquality(); |
| 1310 | } |
| 1311 | |
| 1312 | /// Return true if the predicate is relational (not EQ or NE). |
| 1313 | /// |
| 1314 | static bool isRelational(Predicate P) { |
| 1315 | return !isEquality(P); |
| 1316 | } |
| 1317 | |
| 1318 | /// Return true if the predicate is SGT or UGT. |
| 1319 | /// |
| 1320 | static bool isGT(Predicate P) { |
| 1321 | return P == ICMP_SGT || P == ICMP_UGT; |
| 1322 | } |
| 1323 | |
| 1324 | /// Return true if the predicate is SLT or ULT. |
| 1325 | /// |
| 1326 | static bool isLT(Predicate P) { |
| 1327 | return P == ICMP_SLT || P == ICMP_ULT; |
| 1328 | } |
| 1329 | |
| 1330 | /// Return true if the predicate is SGE or UGE. |
| 1331 | /// |
| 1332 | static bool isGE(Predicate P) { |
| 1333 | return P == ICMP_SGE || P == ICMP_UGE; |
| 1334 | } |
| 1335 | |
| 1336 | /// Return true if the predicate is SLE or ULE. |
| 1337 | /// |
| 1338 | static bool isLE(Predicate P) { |
| 1339 | return P == ICMP_SLE || P == ICMP_ULE; |
| 1340 | } |
| 1341 | |
| 1342 | /// Exchange the two operands to this instruction in such a way that it does |
| 1343 | /// not modify the semantics of the instruction. The predicate value may be |
| 1344 | /// changed to retain the same result if the predicate is order dependent |
| 1345 | /// (e.g. ult). |
| 1346 | /// Swap operands and adjust predicate. |
| 1347 | void swapOperands() { |
| 1348 | setPredicate(getSwappedPredicate()); |
| 1349 | Op<0>().swap(Op<1>()); |
| 1350 | } |
| 1351 | |
| 1352 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 1353 | static bool classof(const Instruction *I) { |
| 1354 | return I->getOpcode() == Instruction::ICmp; |
| 1355 | } |
| 1356 | static bool classof(const Value *V) { |
| 1357 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 1358 | } |
| 1359 | }; |
| 1360 | |
| 1361 | //===----------------------------------------------------------------------===// |
| 1362 | // FCmpInst Class |
| 1363 | //===----------------------------------------------------------------------===// |
| 1364 | |
| 1365 | /// This instruction compares its operands according to the predicate given |
| 1366 | /// to the constructor. It only operates on floating point values or packed |
| 1367 | /// vectors of floating point values. The operands must be identical types. |
| 1368 | /// Represents a floating point comparison operator. |
| 1369 | class FCmpInst: public CmpInst { |
| 1370 | void AssertOK() { |
| 1371 | assert(isFPPredicate() && "Invalid FCmp predicate value")((void)0); |
| 1372 | assert(getOperand(0)->getType() == getOperand(1)->getType() &&((void)0) |
| 1373 | "Both operands to FCmp instruction are not of the same type!")((void)0); |
| 1374 | // Check that the operands are the right type |
| 1375 | assert(getOperand(0)->getType()->isFPOrFPVectorTy() &&((void)0) |
| 1376 | "Invalid operand types for FCmp instruction")((void)0); |
| 1377 | } |
| 1378 | |
| 1379 | protected: |
| 1380 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 1381 | friend class Instruction; |
| 1382 | |
| 1383 | /// Clone an identical FCmpInst |
| 1384 | FCmpInst *cloneImpl() const; |
| 1385 | |
| 1386 | public: |
| 1387 | /// Constructor with insert-before-instruction semantics. |
| 1388 | FCmpInst( |
| 1389 | Instruction *InsertBefore, ///< Where to insert |
| 1390 | Predicate pred, ///< The predicate to use for the comparison |
| 1391 | Value *LHS, ///< The left-hand-side of the expression |
| 1392 | Value *RHS, ///< The right-hand-side of the expression |
| 1393 | const Twine &NameStr = "" ///< Name of the instruction |
| 1394 | ) : CmpInst(makeCmpResultType(LHS->getType()), |
| 1395 | Instruction::FCmp, pred, LHS, RHS, NameStr, |
| 1396 | InsertBefore) { |
| 1397 | AssertOK(); |
| 1398 | } |
| 1399 | |
| 1400 | /// Constructor with insert-at-end semantics. |
| 1401 | FCmpInst( |
| 1402 | BasicBlock &InsertAtEnd, ///< Block to insert into. |
| 1403 | Predicate pred, ///< The predicate to use for the comparison |
| 1404 | Value *LHS, ///< The left-hand-side of the expression |
| 1405 | Value *RHS, ///< The right-hand-side of the expression |
| 1406 | const Twine &NameStr = "" ///< Name of the instruction |
| 1407 | ) : CmpInst(makeCmpResultType(LHS->getType()), |
| 1408 | Instruction::FCmp, pred, LHS, RHS, NameStr, |
| 1409 | &InsertAtEnd) { |
| 1410 | AssertOK(); |
| 1411 | } |
| 1412 | |
| 1413 | /// Constructor with no-insertion semantics |
| 1414 | FCmpInst( |
| 1415 | Predicate Pred, ///< The predicate to use for the comparison |
| 1416 | Value *LHS, ///< The left-hand-side of the expression |
| 1417 | Value *RHS, ///< The right-hand-side of the expression |
| 1418 | const Twine &NameStr = "", ///< Name of the instruction |
| 1419 | Instruction *FlagsSource = nullptr |
| 1420 | ) : CmpInst(makeCmpResultType(LHS->getType()), Instruction::FCmp, Pred, LHS, |
| 1421 | RHS, NameStr, nullptr, FlagsSource) { |
| 1422 | AssertOK(); |
| 1423 | } |
| 1424 | |
| 1425 | /// @returns true if the predicate of this instruction is EQ or NE. |
| 1426 | /// Determine if this is an equality predicate. |
| 1427 | static bool isEquality(Predicate Pred) { |
| 1428 | return Pred == FCMP_OEQ || Pred == FCMP_ONE || Pred == FCMP_UEQ || |
| 1429 | Pred == FCMP_UNE; |
| 1430 | } |
| 1431 | |
| 1432 | /// @returns true if the predicate of this instruction is EQ or NE. |
| 1433 | /// Determine if this is an equality predicate. |
| 1434 | bool isEquality() const { return isEquality(getPredicate()); } |
| 1435 | |
| 1436 | /// @returns true if the predicate of this instruction is commutative. |
| 1437 | /// Determine if this is a commutative predicate. |
| 1438 | bool isCommutative() const { |
| 1439 | return isEquality() || |
| 1440 | getPredicate() == FCMP_FALSE || |
| 1441 | getPredicate() == FCMP_TRUE || |
| 1442 | getPredicate() == FCMP_ORD || |
| 1443 | getPredicate() == FCMP_UNO; |
| 1444 | } |
| 1445 | |
| 1446 | /// @returns true if the predicate is relational (not EQ or NE). |
| 1447 | /// Determine if this a relational predicate. |
| 1448 | bool isRelational() const { return !isEquality(); } |
| 1449 | |
| 1450 | /// Exchange the two operands to this instruction in such a way that it does |
| 1451 | /// not modify the semantics of the instruction. The predicate value may be |
| 1452 | /// changed to retain the same result if the predicate is order dependent |
| 1453 | /// (e.g. ult). |
| 1454 | /// Swap operands and adjust predicate. |
| 1455 | void swapOperands() { |
| 1456 | setPredicate(getSwappedPredicate()); |
| 1457 | Op<0>().swap(Op<1>()); |
| 1458 | } |
| 1459 | |
| 1460 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 1461 | static bool classof(const Instruction *I) { |
| 1462 | return I->getOpcode() == Instruction::FCmp; |
| 1463 | } |
| 1464 | static bool classof(const Value *V) { |
| 1465 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 1466 | } |
| 1467 | }; |
| 1468 | |
| 1469 | //===----------------------------------------------------------------------===// |
| 1470 | /// This class represents a function call, abstracting a target |
| 1471 | /// machine's calling convention. This class uses low bit of the SubClassData |
| 1472 | /// field to indicate whether or not this is a tail call. The rest of the bits |
| 1473 | /// hold the calling convention of the call. |
| 1474 | /// |
| 1475 | class CallInst : public CallBase { |
| 1476 | CallInst(const CallInst &CI); |
| 1477 | |
| 1478 | /// Construct a CallInst given a range of arguments. |
| 1479 | /// Construct a CallInst from a range of arguments |
| 1480 | inline CallInst(FunctionType *Ty, Value *Func, ArrayRef<Value *> Args, |
| 1481 | ArrayRef<OperandBundleDef> Bundles, const Twine &NameStr, |
| 1482 | Instruction *InsertBefore); |
| 1483 | |
| 1484 | inline CallInst(FunctionType *Ty, Value *Func, ArrayRef<Value *> Args, |
| 1485 | const Twine &NameStr, Instruction *InsertBefore) |
| 1486 | : CallInst(Ty, Func, Args, None, NameStr, InsertBefore) {} |
| 1487 | |
| 1488 | /// Construct a CallInst given a range of arguments. |
| 1489 | /// Construct a CallInst from a range of arguments |
| 1490 | inline CallInst(FunctionType *Ty, Value *Func, ArrayRef<Value *> Args, |
| 1491 | ArrayRef<OperandBundleDef> Bundles, const Twine &NameStr, |
| 1492 | BasicBlock *InsertAtEnd); |
| 1493 | |
| 1494 | explicit CallInst(FunctionType *Ty, Value *F, const Twine &NameStr, |
| 1495 | Instruction *InsertBefore); |
| 1496 | |
| 1497 | CallInst(FunctionType *ty, Value *F, const Twine &NameStr, |
| 1498 | BasicBlock *InsertAtEnd); |
| 1499 | |
| 1500 | void init(FunctionType *FTy, Value *Func, ArrayRef<Value *> Args, |
| 1501 | ArrayRef<OperandBundleDef> Bundles, const Twine &NameStr); |
| 1502 | void init(FunctionType *FTy, Value *Func, const Twine &NameStr); |
| 1503 | |
| 1504 | /// Compute the number of operands to allocate. |
| 1505 | static int ComputeNumOperands(int NumArgs, int NumBundleInputs = 0) { |
| 1506 | // We need one operand for the called function, plus the input operand |
| 1507 | // counts provided. |
| 1508 | return 1 + NumArgs + NumBundleInputs; |
| 1509 | } |
| 1510 | |
| 1511 | protected: |
| 1512 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 1513 | friend class Instruction; |
| 1514 | |
| 1515 | CallInst *cloneImpl() const; |
| 1516 | |
| 1517 | public: |
| 1518 | static CallInst *Create(FunctionType *Ty, Value *F, const Twine &NameStr = "", |
| 1519 | Instruction *InsertBefore = nullptr) { |
| 1520 | return new (ComputeNumOperands(0)) CallInst(Ty, F, NameStr, InsertBefore); |
| 1521 | } |
| 1522 | |
| 1523 | static CallInst *Create(FunctionType *Ty, Value *Func, ArrayRef<Value *> Args, |
| 1524 | const Twine &NameStr, |
| 1525 | Instruction *InsertBefore = nullptr) { |
| 1526 | return new (ComputeNumOperands(Args.size())) |
| 1527 | CallInst(Ty, Func, Args, None, NameStr, InsertBefore); |
| 1528 | } |
| 1529 | |
| 1530 | static CallInst *Create(FunctionType *Ty, Value *Func, ArrayRef<Value *> Args, |
| 1531 | ArrayRef<OperandBundleDef> Bundles = None, |
| 1532 | const Twine &NameStr = "", |
| 1533 | Instruction *InsertBefore = nullptr) { |
| 1534 | const int NumOperands = |
| 1535 | ComputeNumOperands(Args.size(), CountBundleInputs(Bundles)); |
| 1536 | const unsigned DescriptorBytes = Bundles.size() * sizeof(BundleOpInfo); |
| 1537 | |
| 1538 | return new (NumOperands, DescriptorBytes) |
| 1539 | CallInst(Ty, Func, Args, Bundles, NameStr, InsertBefore); |
| 1540 | } |
| 1541 | |
| 1542 | static CallInst *Create(FunctionType *Ty, Value *F, const Twine &NameStr, |
| 1543 | BasicBlock *InsertAtEnd) { |
| 1544 | return new (ComputeNumOperands(0)) CallInst(Ty, F, NameStr, InsertAtEnd); |
| 1545 | } |
| 1546 | |
| 1547 | static CallInst *Create(FunctionType *Ty, Value *Func, ArrayRef<Value *> Args, |
| 1548 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 1549 | return new (ComputeNumOperands(Args.size())) |
| 1550 | CallInst(Ty, Func, Args, None, NameStr, InsertAtEnd); |
| 1551 | } |
| 1552 | |
| 1553 | static CallInst *Create(FunctionType *Ty, Value *Func, ArrayRef<Value *> Args, |
| 1554 | ArrayRef<OperandBundleDef> Bundles, |
| 1555 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 1556 | const int NumOperands = |
| 1557 | ComputeNumOperands(Args.size(), CountBundleInputs(Bundles)); |
| 1558 | const unsigned DescriptorBytes = Bundles.size() * sizeof(BundleOpInfo); |
| 1559 | |
| 1560 | return new (NumOperands, DescriptorBytes) |
| 1561 | CallInst(Ty, Func, Args, Bundles, NameStr, InsertAtEnd); |
| 1562 | } |
| 1563 | |
| 1564 | static CallInst *Create(FunctionCallee Func, const Twine &NameStr = "", |
| 1565 | Instruction *InsertBefore = nullptr) { |
| 1566 | return Create(Func.getFunctionType(), Func.getCallee(), NameStr, |
| 1567 | InsertBefore); |
| 1568 | } |
| 1569 | |
| 1570 | static CallInst *Create(FunctionCallee Func, ArrayRef<Value *> Args, |
| 1571 | ArrayRef<OperandBundleDef> Bundles = None, |
| 1572 | const Twine &NameStr = "", |
| 1573 | Instruction *InsertBefore = nullptr) { |
| 1574 | return Create(Func.getFunctionType(), Func.getCallee(), Args, Bundles, |
| 1575 | NameStr, InsertBefore); |
| 1576 | } |
| 1577 | |
| 1578 | static CallInst *Create(FunctionCallee Func, ArrayRef<Value *> Args, |
| 1579 | const Twine &NameStr, |
| 1580 | Instruction *InsertBefore = nullptr) { |
| 1581 | return Create(Func.getFunctionType(), Func.getCallee(), Args, NameStr, |
| 1582 | InsertBefore); |
| 1583 | } |
| 1584 | |
| 1585 | static CallInst *Create(FunctionCallee Func, const Twine &NameStr, |
| 1586 | BasicBlock *InsertAtEnd) { |
| 1587 | return Create(Func.getFunctionType(), Func.getCallee(), NameStr, |
| 1588 | InsertAtEnd); |
| 1589 | } |
| 1590 | |
| 1591 | static CallInst *Create(FunctionCallee Func, ArrayRef<Value *> Args, |
| 1592 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 1593 | return Create(Func.getFunctionType(), Func.getCallee(), Args, NameStr, |
| 1594 | InsertAtEnd); |
| 1595 | } |
| 1596 | |
| 1597 | static CallInst *Create(FunctionCallee Func, ArrayRef<Value *> Args, |
| 1598 | ArrayRef<OperandBundleDef> Bundles, |
| 1599 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 1600 | return Create(Func.getFunctionType(), Func.getCallee(), Args, Bundles, |
| 1601 | NameStr, InsertAtEnd); |
| 1602 | } |
| 1603 | |
| 1604 | /// Create a clone of \p CI with a different set of operand bundles and |
| 1605 | /// insert it before \p InsertPt. |
| 1606 | /// |
| 1607 | /// The returned call instruction is identical \p CI in every way except that |
| 1608 | /// the operand bundles for the new instruction are set to the operand bundles |
| 1609 | /// in \p Bundles. |
| 1610 | static CallInst *Create(CallInst *CI, ArrayRef<OperandBundleDef> Bundles, |
| 1611 | Instruction *InsertPt = nullptr); |
| 1612 | |
| 1613 | /// Generate the IR for a call to malloc: |
| 1614 | /// 1. Compute the malloc call's argument as the specified type's size, |
| 1615 | /// possibly multiplied by the array size if the array size is not |
| 1616 | /// constant 1. |
| 1617 | /// 2. Call malloc with that argument. |
| 1618 | /// 3. Bitcast the result of the malloc call to the specified type. |
| 1619 | static Instruction *CreateMalloc(Instruction *InsertBefore, Type *IntPtrTy, |
| 1620 | Type *AllocTy, Value *AllocSize, |
| 1621 | Value *ArraySize = nullptr, |
| 1622 | Function *MallocF = nullptr, |
| 1623 | const Twine &Name = ""); |
| 1624 | static Instruction *CreateMalloc(BasicBlock *InsertAtEnd, Type *IntPtrTy, |
| 1625 | Type *AllocTy, Value *AllocSize, |
| 1626 | Value *ArraySize = nullptr, |
| 1627 | Function *MallocF = nullptr, |
| 1628 | const Twine &Name = ""); |
| 1629 | static Instruction *CreateMalloc(Instruction *InsertBefore, Type *IntPtrTy, |
| 1630 | Type *AllocTy, Value *AllocSize, |
| 1631 | Value *ArraySize = nullptr, |
| 1632 | ArrayRef<OperandBundleDef> Bundles = None, |
| 1633 | Function *MallocF = nullptr, |
| 1634 | const Twine &Name = ""); |
| 1635 | static Instruction *CreateMalloc(BasicBlock *InsertAtEnd, Type *IntPtrTy, |
| 1636 | Type *AllocTy, Value *AllocSize, |
| 1637 | Value *ArraySize = nullptr, |
| 1638 | ArrayRef<OperandBundleDef> Bundles = None, |
| 1639 | Function *MallocF = nullptr, |
| 1640 | const Twine &Name = ""); |
| 1641 | /// Generate the IR for a call to the builtin free function. |
| 1642 | static Instruction *CreateFree(Value *Source, Instruction *InsertBefore); |
| 1643 | static Instruction *CreateFree(Value *Source, BasicBlock *InsertAtEnd); |
| 1644 | static Instruction *CreateFree(Value *Source, |
| 1645 | ArrayRef<OperandBundleDef> Bundles, |
| 1646 | Instruction *InsertBefore); |
| 1647 | static Instruction *CreateFree(Value *Source, |
| 1648 | ArrayRef<OperandBundleDef> Bundles, |
| 1649 | BasicBlock *InsertAtEnd); |
| 1650 | |
| 1651 | // Note that 'musttail' implies 'tail'. |
| 1652 | enum TailCallKind : unsigned { |
| 1653 | TCK_None = 0, |
| 1654 | TCK_Tail = 1, |
| 1655 | TCK_MustTail = 2, |
| 1656 | TCK_NoTail = 3, |
| 1657 | TCK_LAST = TCK_NoTail |
| 1658 | }; |
| 1659 | |
| 1660 | using TailCallKindField = Bitfield::Element<TailCallKind, 0, 2, TCK_LAST>; |
| 1661 | static_assert( |
| 1662 | Bitfield::areContiguous<TailCallKindField, CallBase::CallingConvField>(), |
| 1663 | "Bitfields must be contiguous"); |
| 1664 | |
| 1665 | TailCallKind getTailCallKind() const { |
| 1666 | return getSubclassData<TailCallKindField>(); |
| 1667 | } |
| 1668 | |
| 1669 | bool isTailCall() const { |
| 1670 | TailCallKind Kind = getTailCallKind(); |
| 1671 | return Kind == TCK_Tail || Kind == TCK_MustTail; |
| 1672 | } |
| 1673 | |
| 1674 | bool isMustTailCall() const { return getTailCallKind() == TCK_MustTail; } |
| 1675 | |
| 1676 | bool isNoTailCall() const { return getTailCallKind() == TCK_NoTail; } |
| 1677 | |
| 1678 | void setTailCallKind(TailCallKind TCK) { |
| 1679 | setSubclassData<TailCallKindField>(TCK); |
| 1680 | } |
| 1681 | |
| 1682 | void setTailCall(bool IsTc = true) { |
| 1683 | setTailCallKind(IsTc ? TCK_Tail : TCK_None); |
| 1684 | } |
| 1685 | |
| 1686 | /// Return true if the call can return twice |
| 1687 | bool canReturnTwice() const { return hasFnAttr(Attribute::ReturnsTwice); } |
| 1688 | void setCanReturnTwice() { |
| 1689 | addAttribute(AttributeList::FunctionIndex, Attribute::ReturnsTwice); |
| 1690 | } |
| 1691 | |
| 1692 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 1693 | static bool classof(const Instruction *I) { |
| 1694 | return I->getOpcode() == Instruction::Call; |
| 1695 | } |
| 1696 | static bool classof(const Value *V) { |
| 1697 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 1698 | } |
| 1699 | |
| 1700 | /// Updates profile metadata by scaling it by \p S / \p T. |
| 1701 | void updateProfWeight(uint64_t S, uint64_t T); |
| 1702 | |
| 1703 | private: |
| 1704 | // Shadow Instruction::setInstructionSubclassData with a private forwarding |
| 1705 | // method so that subclasses cannot accidentally use it. |
| 1706 | template <typename Bitfield> |
| 1707 | void setSubclassData(typename Bitfield::Type Value) { |
| 1708 | Instruction::setSubclassData<Bitfield>(Value); |
| 1709 | } |
| 1710 | }; |
| 1711 | |
| 1712 | CallInst::CallInst(FunctionType *Ty, Value *Func, ArrayRef<Value *> Args, |
| 1713 | ArrayRef<OperandBundleDef> Bundles, const Twine &NameStr, |
| 1714 | BasicBlock *InsertAtEnd) |
| 1715 | : CallBase(Ty->getReturnType(), Instruction::Call, |
| 1716 | OperandTraits<CallBase>::op_end(this) - |
| 1717 | (Args.size() + CountBundleInputs(Bundles) + 1), |
| 1718 | unsigned(Args.size() + CountBundleInputs(Bundles) + 1), |
| 1719 | InsertAtEnd) { |
| 1720 | init(Ty, Func, Args, Bundles, NameStr); |
| 1721 | } |
| 1722 | |
| 1723 | CallInst::CallInst(FunctionType *Ty, Value *Func, ArrayRef<Value *> Args, |
| 1724 | ArrayRef<OperandBundleDef> Bundles, const Twine &NameStr, |
| 1725 | Instruction *InsertBefore) |
| 1726 | : CallBase(Ty->getReturnType(), Instruction::Call, |
| 1727 | OperandTraits<CallBase>::op_end(this) - |
| 1728 | (Args.size() + CountBundleInputs(Bundles) + 1), |
| 1729 | unsigned(Args.size() + CountBundleInputs(Bundles) + 1), |
| 1730 | InsertBefore) { |
| 1731 | init(Ty, Func, Args, Bundles, NameStr); |
| 1732 | } |
| 1733 | |
| 1734 | //===----------------------------------------------------------------------===// |
| 1735 | // SelectInst Class |
| 1736 | //===----------------------------------------------------------------------===// |
| 1737 | |
| 1738 | /// This class represents the LLVM 'select' instruction. |
| 1739 | /// |
| 1740 | class SelectInst : public Instruction { |
| 1741 | SelectInst(Value *C, Value *S1, Value *S2, const Twine &NameStr, |
| 1742 | Instruction *InsertBefore) |
| 1743 | : Instruction(S1->getType(), Instruction::Select, |
| 1744 | &Op<0>(), 3, InsertBefore) { |
| 1745 | init(C, S1, S2); |
| 1746 | setName(NameStr); |
| 1747 | } |
| 1748 | |
| 1749 | SelectInst(Value *C, Value *S1, Value *S2, const Twine &NameStr, |
| 1750 | BasicBlock *InsertAtEnd) |
| 1751 | : Instruction(S1->getType(), Instruction::Select, |
| 1752 | &Op<0>(), 3, InsertAtEnd) { |
| 1753 | init(C, S1, S2); |
| 1754 | setName(NameStr); |
| 1755 | } |
| 1756 | |
| 1757 | void init(Value *C, Value *S1, Value *S2) { |
| 1758 | assert(!areInvalidOperands(C, S1, S2) && "Invalid operands for select")((void)0); |
| 1759 | Op<0>() = C; |
| 1760 | Op<1>() = S1; |
| 1761 | Op<2>() = S2; |
| 1762 | } |
| 1763 | |
| 1764 | protected: |
| 1765 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 1766 | friend class Instruction; |
| 1767 | |
| 1768 | SelectInst *cloneImpl() const; |
| 1769 | |
| 1770 | public: |
| 1771 | static SelectInst *Create(Value *C, Value *S1, Value *S2, |
| 1772 | const Twine &NameStr = "", |
| 1773 | Instruction *InsertBefore = nullptr, |
| 1774 | Instruction *MDFrom = nullptr) { |
| 1775 | SelectInst *Sel = new(3) SelectInst(C, S1, S2, NameStr, InsertBefore); |
| 1776 | if (MDFrom) |
| 1777 | Sel->copyMetadata(*MDFrom); |
| 1778 | return Sel; |
| 1779 | } |
| 1780 | |
| 1781 | static SelectInst *Create(Value *C, Value *S1, Value *S2, |
| 1782 | const Twine &NameStr, |
| 1783 | BasicBlock *InsertAtEnd) { |
| 1784 | return new(3) SelectInst(C, S1, S2, NameStr, InsertAtEnd); |
| 1785 | } |
| 1786 | |
| 1787 | const Value *getCondition() const { return Op<0>(); } |
| 1788 | const Value *getTrueValue() const { return Op<1>(); } |
| 1789 | const Value *getFalseValue() const { return Op<2>(); } |
| 1790 | Value *getCondition() { return Op<0>(); } |
| 1791 | Value *getTrueValue() { return Op<1>(); } |
| 1792 | Value *getFalseValue() { return Op<2>(); } |
| 1793 | |
| 1794 | void setCondition(Value *V) { Op<0>() = V; } |
| 1795 | void setTrueValue(Value *V) { Op<1>() = V; } |
| 1796 | void setFalseValue(Value *V) { Op<2>() = V; } |
| 1797 | |
| 1798 | /// Swap the true and false values of the select instruction. |
| 1799 | /// This doesn't swap prof metadata. |
| 1800 | void swapValues() { Op<1>().swap(Op<2>()); } |
| 1801 | |
| 1802 | /// Return a string if the specified operands are invalid |
| 1803 | /// for a select operation, otherwise return null. |
| 1804 | static const char *areInvalidOperands(Value *Cond, Value *True, Value *False); |
| 1805 | |
| 1806 | /// Transparently provide more efficient getOperand methods. |
| 1807 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 1808 | |
| 1809 | OtherOps getOpcode() const { |
| 1810 | return static_cast<OtherOps>(Instruction::getOpcode()); |
| 1811 | } |
| 1812 | |
| 1813 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 1814 | static bool classof(const Instruction *I) { |
| 1815 | return I->getOpcode() == Instruction::Select; |
| 1816 | } |
| 1817 | static bool classof(const Value *V) { |
| 1818 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 1819 | } |
| 1820 | }; |
| 1821 | |
| 1822 | template <> |
| 1823 | struct OperandTraits<SelectInst> : public FixedNumOperandTraits<SelectInst, 3> { |
| 1824 | }; |
| 1825 | |
| 1826 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(SelectInst, Value)SelectInst::op_iterator SelectInst::op_begin() { return OperandTraits <SelectInst>::op_begin(this); } SelectInst::const_op_iterator SelectInst::op_begin() const { return OperandTraits<SelectInst >::op_begin(const_cast<SelectInst*>(this)); } SelectInst ::op_iterator SelectInst::op_end() { return OperandTraits< SelectInst>::op_end(this); } SelectInst::const_op_iterator SelectInst::op_end() const { return OperandTraits<SelectInst >::op_end(const_cast<SelectInst*>(this)); } Value *SelectInst ::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null <Value>( OperandTraits<SelectInst>::op_begin(const_cast <SelectInst*>(this))[i_nocapture].get()); } void SelectInst ::setOperand(unsigned i_nocapture, Value *Val_nocapture) { (( void)0); OperandTraits<SelectInst>::op_begin(this)[i_nocapture ] = Val_nocapture; } unsigned SelectInst::getNumOperands() const { return OperandTraits<SelectInst>::operands(this); } template <int Idx_nocapture> Use &SelectInst::Op() { return this->OpFrom<Idx_nocapture>(this); } template <int Idx_nocapture> const Use &SelectInst::Op() const { return this->OpFrom<Idx_nocapture>(this); } |
| 1827 | |
| 1828 | //===----------------------------------------------------------------------===// |
| 1829 | // VAArgInst Class |
| 1830 | //===----------------------------------------------------------------------===// |
| 1831 | |
| 1832 | /// This class represents the va_arg llvm instruction, which returns |
| 1833 | /// an argument of the specified type given a va_list and increments that list |
| 1834 | /// |
| 1835 | class VAArgInst : public UnaryInstruction { |
| 1836 | protected: |
| 1837 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 1838 | friend class Instruction; |
| 1839 | |
| 1840 | VAArgInst *cloneImpl() const; |
| 1841 | |
| 1842 | public: |
| 1843 | VAArgInst(Value *List, Type *Ty, const Twine &NameStr = "", |
| 1844 | Instruction *InsertBefore = nullptr) |
| 1845 | : UnaryInstruction(Ty, VAArg, List, InsertBefore) { |
| 1846 | setName(NameStr); |
| 1847 | } |
| 1848 | |
| 1849 | VAArgInst(Value *List, Type *Ty, const Twine &NameStr, |
| 1850 | BasicBlock *InsertAtEnd) |
| 1851 | : UnaryInstruction(Ty, VAArg, List, InsertAtEnd) { |
| 1852 | setName(NameStr); |
| 1853 | } |
| 1854 | |
| 1855 | Value *getPointerOperand() { return getOperand(0); } |
| 1856 | const Value *getPointerOperand() const { return getOperand(0); } |
| 1857 | static unsigned getPointerOperandIndex() { return 0U; } |
| 1858 | |
| 1859 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 1860 | static bool classof(const Instruction *I) { |
| 1861 | return I->getOpcode() == VAArg; |
| 1862 | } |
| 1863 | static bool classof(const Value *V) { |
| 1864 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 1865 | } |
| 1866 | }; |
| 1867 | |
| 1868 | //===----------------------------------------------------------------------===// |
| 1869 | // ExtractElementInst Class |
| 1870 | //===----------------------------------------------------------------------===// |
| 1871 | |
| 1872 | /// This instruction extracts a single (scalar) |
| 1873 | /// element from a VectorType value |
| 1874 | /// |
| 1875 | class ExtractElementInst : public Instruction { |
| 1876 | ExtractElementInst(Value *Vec, Value *Idx, const Twine &NameStr = "", |
| 1877 | Instruction *InsertBefore = nullptr); |
| 1878 | ExtractElementInst(Value *Vec, Value *Idx, const Twine &NameStr, |
| 1879 | BasicBlock *InsertAtEnd); |
| 1880 | |
| 1881 | protected: |
| 1882 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 1883 | friend class Instruction; |
| 1884 | |
| 1885 | ExtractElementInst *cloneImpl() const; |
| 1886 | |
| 1887 | public: |
| 1888 | static ExtractElementInst *Create(Value *Vec, Value *Idx, |
| 1889 | const Twine &NameStr = "", |
| 1890 | Instruction *InsertBefore = nullptr) { |
| 1891 | return new(2) ExtractElementInst(Vec, Idx, NameStr, InsertBefore); |
| 1892 | } |
| 1893 | |
| 1894 | static ExtractElementInst *Create(Value *Vec, Value *Idx, |
| 1895 | const Twine &NameStr, |
| 1896 | BasicBlock *InsertAtEnd) { |
| 1897 | return new(2) ExtractElementInst(Vec, Idx, NameStr, InsertAtEnd); |
| 1898 | } |
| 1899 | |
| 1900 | /// Return true if an extractelement instruction can be |
| 1901 | /// formed with the specified operands. |
| 1902 | static bool isValidOperands(const Value *Vec, const Value *Idx); |
| 1903 | |
| 1904 | Value *getVectorOperand() { return Op<0>(); } |
| 1905 | Value *getIndexOperand() { return Op<1>(); } |
| 1906 | const Value *getVectorOperand() const { return Op<0>(); } |
| 1907 | const Value *getIndexOperand() const { return Op<1>(); } |
| 1908 | |
| 1909 | VectorType *getVectorOperandType() const { |
| 1910 | return cast<VectorType>(getVectorOperand()->getType()); |
| 1911 | } |
| 1912 | |
| 1913 | /// Transparently provide more efficient getOperand methods. |
| 1914 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 1915 | |
| 1916 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 1917 | static bool classof(const Instruction *I) { |
| 1918 | return I->getOpcode() == Instruction::ExtractElement; |
| 1919 | } |
| 1920 | static bool classof(const Value *V) { |
| 1921 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 1922 | } |
| 1923 | }; |
| 1924 | |
| 1925 | template <> |
| 1926 | struct OperandTraits<ExtractElementInst> : |
| 1927 | public FixedNumOperandTraits<ExtractElementInst, 2> { |
| 1928 | }; |
| 1929 | |
| 1930 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ExtractElementInst, Value)ExtractElementInst::op_iterator ExtractElementInst::op_begin( ) { return OperandTraits<ExtractElementInst>::op_begin( this); } ExtractElementInst::const_op_iterator ExtractElementInst ::op_begin() const { return OperandTraits<ExtractElementInst >::op_begin(const_cast<ExtractElementInst*>(this)); } ExtractElementInst::op_iterator ExtractElementInst::op_end() { return OperandTraits<ExtractElementInst>::op_end(this ); } ExtractElementInst::const_op_iterator ExtractElementInst ::op_end() const { return OperandTraits<ExtractElementInst >::op_end(const_cast<ExtractElementInst*>(this)); } Value *ExtractElementInst::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null<Value>( OperandTraits< ExtractElementInst>::op_begin(const_cast<ExtractElementInst *>(this))[i_nocapture].get()); } void ExtractElementInst:: setOperand(unsigned i_nocapture, Value *Val_nocapture) { ((void )0); OperandTraits<ExtractElementInst>::op_begin(this)[ i_nocapture] = Val_nocapture; } unsigned ExtractElementInst:: getNumOperands() const { return OperandTraits<ExtractElementInst >::operands(this); } template <int Idx_nocapture> Use &ExtractElementInst::Op() { return this->OpFrom<Idx_nocapture >(this); } template <int Idx_nocapture> const Use & ExtractElementInst::Op() const { return this->OpFrom<Idx_nocapture >(this); } |
| 1931 | |
| 1932 | //===----------------------------------------------------------------------===// |
| 1933 | // InsertElementInst Class |
| 1934 | //===----------------------------------------------------------------------===// |
| 1935 | |
| 1936 | /// This instruction inserts a single (scalar) |
| 1937 | /// element into a VectorType value |
| 1938 | /// |
| 1939 | class InsertElementInst : public Instruction { |
| 1940 | InsertElementInst(Value *Vec, Value *NewElt, Value *Idx, |
| 1941 | const Twine &NameStr = "", |
| 1942 | Instruction *InsertBefore = nullptr); |
| 1943 | InsertElementInst(Value *Vec, Value *NewElt, Value *Idx, const Twine &NameStr, |
| 1944 | BasicBlock *InsertAtEnd); |
| 1945 | |
| 1946 | protected: |
| 1947 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 1948 | friend class Instruction; |
| 1949 | |
| 1950 | InsertElementInst *cloneImpl() const; |
| 1951 | |
| 1952 | public: |
| 1953 | static InsertElementInst *Create(Value *Vec, Value *NewElt, Value *Idx, |
| 1954 | const Twine &NameStr = "", |
| 1955 | Instruction *InsertBefore = nullptr) { |
| 1956 | return new(3) InsertElementInst(Vec, NewElt, Idx, NameStr, InsertBefore); |
| 1957 | } |
| 1958 | |
| 1959 | static InsertElementInst *Create(Value *Vec, Value *NewElt, Value *Idx, |
| 1960 | const Twine &NameStr, |
| 1961 | BasicBlock *InsertAtEnd) { |
| 1962 | return new(3) InsertElementInst(Vec, NewElt, Idx, NameStr, InsertAtEnd); |
| 1963 | } |
| 1964 | |
| 1965 | /// Return true if an insertelement instruction can be |
| 1966 | /// formed with the specified operands. |
| 1967 | static bool isValidOperands(const Value *Vec, const Value *NewElt, |
| 1968 | const Value *Idx); |
| 1969 | |
| 1970 | /// Overload to return most specific vector type. |
| 1971 | /// |
| 1972 | VectorType *getType() const { |
| 1973 | return cast<VectorType>(Instruction::getType()); |
| 1974 | } |
| 1975 | |
| 1976 | /// Transparently provide more efficient getOperand methods. |
| 1977 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 1978 | |
| 1979 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 1980 | static bool classof(const Instruction *I) { |
| 1981 | return I->getOpcode() == Instruction::InsertElement; |
| 1982 | } |
| 1983 | static bool classof(const Value *V) { |
| 1984 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 1985 | } |
| 1986 | }; |
| 1987 | |
| 1988 | template <> |
| 1989 | struct OperandTraits<InsertElementInst> : |
| 1990 | public FixedNumOperandTraits<InsertElementInst, 3> { |
| 1991 | }; |
| 1992 | |
| 1993 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InsertElementInst, Value)InsertElementInst::op_iterator InsertElementInst::op_begin() { return OperandTraits<InsertElementInst>::op_begin(this ); } InsertElementInst::const_op_iterator InsertElementInst:: op_begin() const { return OperandTraits<InsertElementInst> ::op_begin(const_cast<InsertElementInst*>(this)); } InsertElementInst ::op_iterator InsertElementInst::op_end() { return OperandTraits <InsertElementInst>::op_end(this); } InsertElementInst:: const_op_iterator InsertElementInst::op_end() const { return OperandTraits <InsertElementInst>::op_end(const_cast<InsertElementInst *>(this)); } Value *InsertElementInst::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null<Value >( OperandTraits<InsertElementInst>::op_begin(const_cast <InsertElementInst*>(this))[i_nocapture].get()); } void InsertElementInst::setOperand(unsigned i_nocapture, Value *Val_nocapture ) { ((void)0); OperandTraits<InsertElementInst>::op_begin (this)[i_nocapture] = Val_nocapture; } unsigned InsertElementInst ::getNumOperands() const { return OperandTraits<InsertElementInst >::operands(this); } template <int Idx_nocapture> Use &InsertElementInst::Op() { return this->OpFrom<Idx_nocapture >(this); } template <int Idx_nocapture> const Use & InsertElementInst::Op() const { return this->OpFrom<Idx_nocapture >(this); } |
| 1994 | |
| 1995 | //===----------------------------------------------------------------------===// |
| 1996 | // ShuffleVectorInst Class |
| 1997 | //===----------------------------------------------------------------------===// |
| 1998 | |
| 1999 | constexpr int UndefMaskElem = -1; |
| 2000 | |
| 2001 | /// This instruction constructs a fixed permutation of two |
| 2002 | /// input vectors. |
| 2003 | /// |
| 2004 | /// For each element of the result vector, the shuffle mask selects an element |
| 2005 | /// from one of the input vectors to copy to the result. Non-negative elements |
| 2006 | /// in the mask represent an index into the concatenated pair of input vectors. |
| 2007 | /// UndefMaskElem (-1) specifies that the result element is undefined. |
| 2008 | /// |
| 2009 | /// For scalable vectors, all the elements of the mask must be 0 or -1. This |
| 2010 | /// requirement may be relaxed in the future. |
| 2011 | class ShuffleVectorInst : public Instruction { |
| 2012 | SmallVector<int, 4> ShuffleMask; |
| 2013 | Constant *ShuffleMaskForBitcode; |
| 2014 | |
| 2015 | protected: |
| 2016 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 2017 | friend class Instruction; |
| 2018 | |
| 2019 | ShuffleVectorInst *cloneImpl() const; |
| 2020 | |
| 2021 | public: |
| 2022 | ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, |
| 2023 | const Twine &NameStr = "", |
| 2024 | Instruction *InsertBefor = nullptr); |
| 2025 | ShuffleVectorInst(Value *V1, Value *V2, Value *Mask, |
| 2026 | const Twine &NameStr, BasicBlock *InsertAtEnd); |
| 2027 | ShuffleVectorInst(Value *V1, Value *V2, ArrayRef<int> Mask, |
| 2028 | const Twine &NameStr = "", |
| 2029 | Instruction *InsertBefor = nullptr); |
| 2030 | ShuffleVectorInst(Value *V1, Value *V2, ArrayRef<int> Mask, |
| 2031 | const Twine &NameStr, BasicBlock *InsertAtEnd); |
| 2032 | |
| 2033 | void *operator new(size_t S) { return User::operator new(S, 2); } |
| 2034 | void operator delete(void *Ptr) { return User::operator delete(Ptr); } |
| 2035 | |
| 2036 | /// Swap the operands and adjust the mask to preserve the semantics |
| 2037 | /// of the instruction. |
| 2038 | void commute(); |
| 2039 | |
| 2040 | /// Return true if a shufflevector instruction can be |
| 2041 | /// formed with the specified operands. |
| 2042 | static bool isValidOperands(const Value *V1, const Value *V2, |
| 2043 | const Value *Mask); |
| 2044 | static bool isValidOperands(const Value *V1, const Value *V2, |
| 2045 | ArrayRef<int> Mask); |
| 2046 | |
| 2047 | /// Overload to return most specific vector type. |
| 2048 | /// |
| 2049 | VectorType *getType() const { |
| 2050 | return cast<VectorType>(Instruction::getType()); |
| 2051 | } |
| 2052 | |
| 2053 | /// Transparently provide more efficient getOperand methods. |
| 2054 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 2055 | |
| 2056 | /// Return the shuffle mask value of this instruction for the given element |
| 2057 | /// index. Return UndefMaskElem if the element is undef. |
| 2058 | int getMaskValue(unsigned Elt) const { return ShuffleMask[Elt]; } |
| 2059 | |
| 2060 | /// Convert the input shuffle mask operand to a vector of integers. Undefined |
| 2061 | /// elements of the mask are returned as UndefMaskElem. |
| 2062 | static void getShuffleMask(const Constant *Mask, |
| 2063 | SmallVectorImpl<int> &Result); |
| 2064 | |
| 2065 | /// Return the mask for this instruction as a vector of integers. Undefined |
| 2066 | /// elements of the mask are returned as UndefMaskElem. |
| 2067 | void getShuffleMask(SmallVectorImpl<int> &Result) const { |
| 2068 | Result.assign(ShuffleMask.begin(), ShuffleMask.end()); |
| 2069 | } |
| 2070 | |
| 2071 | /// Return the mask for this instruction, for use in bitcode. |
| 2072 | /// |
| 2073 | /// TODO: This is temporary until we decide a new bitcode encoding for |
| 2074 | /// shufflevector. |
| 2075 | Constant *getShuffleMaskForBitcode() const { return ShuffleMaskForBitcode; } |
| 2076 | |
| 2077 | static Constant *convertShuffleMaskForBitcode(ArrayRef<int> Mask, |
| 2078 | Type *ResultTy); |
| 2079 | |
| 2080 | void setShuffleMask(ArrayRef<int> Mask); |
| 2081 | |
| 2082 | ArrayRef<int> getShuffleMask() const { return ShuffleMask; } |
| 2083 | |
| 2084 | /// Return true if this shuffle returns a vector with a different number of |
| 2085 | /// elements than its source vectors. |
| 2086 | /// Examples: shufflevector <4 x n> A, <4 x n> B, <1,2,3> |
| 2087 | /// shufflevector <4 x n> A, <4 x n> B, <1,2,3,4,5> |
| 2088 | bool changesLength() const { |
| 2089 | unsigned NumSourceElts = cast<VectorType>(Op<0>()->getType()) |
| 2090 | ->getElementCount() |
| 2091 | .getKnownMinValue(); |
| 2092 | unsigned NumMaskElts = ShuffleMask.size(); |
| 2093 | return NumSourceElts != NumMaskElts; |
| 2094 | } |
| 2095 | |
| 2096 | /// Return true if this shuffle returns a vector with a greater number of |
| 2097 | /// elements than its source vectors. |
| 2098 | /// Example: shufflevector <2 x n> A, <2 x n> B, <1,2,3> |
| 2099 | bool increasesLength() const { |
| 2100 | unsigned NumSourceElts = cast<VectorType>(Op<0>()->getType()) |
| 2101 | ->getElementCount() |
| 2102 | .getKnownMinValue(); |
| 2103 | unsigned NumMaskElts = ShuffleMask.size(); |
| 2104 | return NumSourceElts < NumMaskElts; |
| 2105 | } |
| 2106 | |
| 2107 | /// Return true if this shuffle mask chooses elements from exactly one source |
| 2108 | /// vector. |
| 2109 | /// Example: <7,5,undef,7> |
| 2110 | /// This assumes that vector operands are the same length as the mask. |
| 2111 | static bool isSingleSourceMask(ArrayRef<int> Mask); |
| 2112 | static bool isSingleSourceMask(const Constant *Mask) { |
| 2113 | assert(Mask->getType()->isVectorTy() && "Shuffle needs vector constant.")((void)0); |
| 2114 | SmallVector<int, 16> MaskAsInts; |
| 2115 | getShuffleMask(Mask, MaskAsInts); |
| 2116 | return isSingleSourceMask(MaskAsInts); |
| 2117 | } |
| 2118 | |
| 2119 | /// Return true if this shuffle chooses elements from exactly one source |
| 2120 | /// vector without changing the length of that vector. |
| 2121 | /// Example: shufflevector <4 x n> A, <4 x n> B, <3,0,undef,3> |
| 2122 | /// TODO: Optionally allow length-changing shuffles. |
| 2123 | bool isSingleSource() const { |
| 2124 | return !changesLength() && isSingleSourceMask(ShuffleMask); |
| 2125 | } |
| 2126 | |
| 2127 | /// Return true if this shuffle mask chooses elements from exactly one source |
| 2128 | /// vector without lane crossings. A shuffle using this mask is not |
| 2129 | /// necessarily a no-op because it may change the number of elements from its |
| 2130 | /// input vectors or it may provide demanded bits knowledge via undef lanes. |
| 2131 | /// Example: <undef,undef,2,3> |
| 2132 | static bool isIdentityMask(ArrayRef<int> Mask); |
| 2133 | static bool isIdentityMask(const Constant *Mask) { |
| 2134 | assert(Mask->getType()->isVectorTy() && "Shuffle needs vector constant.")((void)0); |
| 2135 | SmallVector<int, 16> MaskAsInts; |
| 2136 | getShuffleMask(Mask, MaskAsInts); |
| 2137 | return isIdentityMask(MaskAsInts); |
| 2138 | } |
| 2139 | |
| 2140 | /// Return true if this shuffle chooses elements from exactly one source |
| 2141 | /// vector without lane crossings and does not change the number of elements |
| 2142 | /// from its input vectors. |
| 2143 | /// Example: shufflevector <4 x n> A, <4 x n> B, <4,undef,6,undef> |
| 2144 | bool isIdentity() const { |
| 2145 | return !changesLength() && isIdentityMask(ShuffleMask); |
| 2146 | } |
| 2147 | |
| 2148 | /// Return true if this shuffle lengthens exactly one source vector with |
| 2149 | /// undefs in the high elements. |
| 2150 | bool isIdentityWithPadding() const; |
| 2151 | |
| 2152 | /// Return true if this shuffle extracts the first N elements of exactly one |
| 2153 | /// source vector. |
| 2154 | bool isIdentityWithExtract() const; |
| 2155 | |
| 2156 | /// Return true if this shuffle concatenates its 2 source vectors. This |
| 2157 | /// returns false if either input is undefined. In that case, the shuffle is |
| 2158 | /// is better classified as an identity with padding operation. |
| 2159 | bool isConcat() const; |
| 2160 | |
| 2161 | /// Return true if this shuffle mask chooses elements from its source vectors |
| 2162 | /// without lane crossings. A shuffle using this mask would be |
| 2163 | /// equivalent to a vector select with a constant condition operand. |
| 2164 | /// Example: <4,1,6,undef> |
| 2165 | /// This returns false if the mask does not choose from both input vectors. |
| 2166 | /// In that case, the shuffle is better classified as an identity shuffle. |
| 2167 | /// This assumes that vector operands are the same length as the mask |
| 2168 | /// (a length-changing shuffle can never be equivalent to a vector select). |
| 2169 | static bool isSelectMask(ArrayRef<int> Mask); |
| 2170 | static bool isSelectMask(const Constant *Mask) { |
| 2171 | assert(Mask->getType()->isVectorTy() && "Shuffle needs vector constant.")((void)0); |
| 2172 | SmallVector<int, 16> MaskAsInts; |
| 2173 | getShuffleMask(Mask, MaskAsInts); |
| 2174 | return isSelectMask(MaskAsInts); |
| 2175 | } |
| 2176 | |
| 2177 | /// Return true if this shuffle chooses elements from its source vectors |
| 2178 | /// without lane crossings and all operands have the same number of elements. |
| 2179 | /// In other words, this shuffle is equivalent to a vector select with a |
| 2180 | /// constant condition operand. |
| 2181 | /// Example: shufflevector <4 x n> A, <4 x n> B, <undef,1,6,3> |
| 2182 | /// This returns false if the mask does not choose from both input vectors. |
| 2183 | /// In that case, the shuffle is better classified as an identity shuffle. |
| 2184 | /// TODO: Optionally allow length-changing shuffles. |
| 2185 | bool isSelect() const { |
| 2186 | return !changesLength() && isSelectMask(ShuffleMask); |
| 2187 | } |
| 2188 | |
| 2189 | /// Return true if this shuffle mask swaps the order of elements from exactly |
| 2190 | /// one source vector. |
| 2191 | /// Example: <7,6,undef,4> |
| 2192 | /// This assumes that vector operands are the same length as the mask. |
| 2193 | static bool isReverseMask(ArrayRef<int> Mask); |
| 2194 | static bool isReverseMask(const Constant *Mask) { |
| 2195 | assert(Mask->getType()->isVectorTy() && "Shuffle needs vector constant.")((void)0); |
| 2196 | SmallVector<int, 16> MaskAsInts; |
| 2197 | getShuffleMask(Mask, MaskAsInts); |
| 2198 | return isReverseMask(MaskAsInts); |
| 2199 | } |
| 2200 | |
| 2201 | /// Return true if this shuffle swaps the order of elements from exactly |
| 2202 | /// one source vector. |
| 2203 | /// Example: shufflevector <4 x n> A, <4 x n> B, <3,undef,1,undef> |
| 2204 | /// TODO: Optionally allow length-changing shuffles. |
| 2205 | bool isReverse() const { |
| 2206 | return !changesLength() && isReverseMask(ShuffleMask); |
| 2207 | } |
| 2208 | |
| 2209 | /// Return true if this shuffle mask chooses all elements with the same value |
| 2210 | /// as the first element of exactly one source vector. |
| 2211 | /// Example: <4,undef,undef,4> |
| 2212 | /// This assumes that vector operands are the same length as the mask. |
| 2213 | static bool isZeroEltSplatMask(ArrayRef<int> Mask); |
| 2214 | static bool isZeroEltSplatMask(const Constant *Mask) { |
| 2215 | assert(Mask->getType()->isVectorTy() && "Shuffle needs vector constant.")((void)0); |
| 2216 | SmallVector<int, 16> MaskAsInts; |
| 2217 | getShuffleMask(Mask, MaskAsInts); |
| 2218 | return isZeroEltSplatMask(MaskAsInts); |
| 2219 | } |
| 2220 | |
| 2221 | /// Return true if all elements of this shuffle are the same value as the |
| 2222 | /// first element of exactly one source vector without changing the length |
| 2223 | /// of that vector. |
| 2224 | /// Example: shufflevector <4 x n> A, <4 x n> B, <undef,0,undef,0> |
| 2225 | /// TODO: Optionally allow length-changing shuffles. |
| 2226 | /// TODO: Optionally allow splats from other elements. |
| 2227 | bool isZeroEltSplat() const { |
| 2228 | return !changesLength() && isZeroEltSplatMask(ShuffleMask); |
| 2229 | } |
| 2230 | |
| 2231 | /// Return true if this shuffle mask is a transpose mask. |
| 2232 | /// Transpose vector masks transpose a 2xn matrix. They read corresponding |
| 2233 | /// even- or odd-numbered vector elements from two n-dimensional source |
| 2234 | /// vectors and write each result into consecutive elements of an |
| 2235 | /// n-dimensional destination vector. Two shuffles are necessary to complete |
| 2236 | /// the transpose, one for the even elements and another for the odd elements. |
| 2237 | /// This description closely follows how the TRN1 and TRN2 AArch64 |
| 2238 | /// instructions operate. |
| 2239 | /// |
| 2240 | /// For example, a simple 2x2 matrix can be transposed with: |
| 2241 | /// |
| 2242 | /// ; Original matrix |
| 2243 | /// m0 = < a, b > |
| 2244 | /// m1 = < c, d > |
| 2245 | /// |
| 2246 | /// ; Transposed matrix |
| 2247 | /// t0 = < a, c > = shufflevector m0, m1, < 0, 2 > |
| 2248 | /// t1 = < b, d > = shufflevector m0, m1, < 1, 3 > |
| 2249 | /// |
| 2250 | /// For matrices having greater than n columns, the resulting nx2 transposed |
| 2251 | /// matrix is stored in two result vectors such that one vector contains |
| 2252 | /// interleaved elements from all the even-numbered rows and the other vector |
| 2253 | /// contains interleaved elements from all the odd-numbered rows. For example, |
| 2254 | /// a 2x4 matrix can be transposed with: |
| 2255 | /// |
| 2256 | /// ; Original matrix |
| 2257 | /// m0 = < a, b, c, d > |
| 2258 | /// m1 = < e, f, g, h > |
| 2259 | /// |
| 2260 | /// ; Transposed matrix |
| 2261 | /// t0 = < a, e, c, g > = shufflevector m0, m1 < 0, 4, 2, 6 > |
| 2262 | /// t1 = < b, f, d, h > = shufflevector m0, m1 < 1, 5, 3, 7 > |
| 2263 | static bool isTransposeMask(ArrayRef<int> Mask); |
| 2264 | static bool isTransposeMask(const Constant *Mask) { |
| 2265 | assert(Mask->getType()->isVectorTy() && "Shuffle needs vector constant.")((void)0); |
| 2266 | SmallVector<int, 16> MaskAsInts; |
| 2267 | getShuffleMask(Mask, MaskAsInts); |
| 2268 | return isTransposeMask(MaskAsInts); |
| 2269 | } |
| 2270 | |
| 2271 | /// Return true if this shuffle transposes the elements of its inputs without |
| 2272 | /// changing the length of the vectors. This operation may also be known as a |
| 2273 | /// merge or interleave. See the description for isTransposeMask() for the |
| 2274 | /// exact specification. |
| 2275 | /// Example: shufflevector <4 x n> A, <4 x n> B, <0,4,2,6> |
| 2276 | bool isTranspose() const { |
| 2277 | return !changesLength() && isTransposeMask(ShuffleMask); |
| 2278 | } |
| 2279 | |
| 2280 | /// Return true if this shuffle mask is an extract subvector mask. |
| 2281 | /// A valid extract subvector mask returns a smaller vector from a single |
| 2282 | /// source operand. The base extraction index is returned as well. |
| 2283 | static bool isExtractSubvectorMask(ArrayRef<int> Mask, int NumSrcElts, |
| 2284 | int &Index); |
| 2285 | static bool isExtractSubvectorMask(const Constant *Mask, int NumSrcElts, |
| 2286 | int &Index) { |
| 2287 | assert(Mask->getType()->isVectorTy() && "Shuffle needs vector constant.")((void)0); |
| 2288 | // Not possible to express a shuffle mask for a scalable vector for this |
| 2289 | // case. |
| 2290 | if (isa<ScalableVectorType>(Mask->getType())) |
| 2291 | return false; |
| 2292 | SmallVector<int, 16> MaskAsInts; |
| 2293 | getShuffleMask(Mask, MaskAsInts); |
| 2294 | return isExtractSubvectorMask(MaskAsInts, NumSrcElts, Index); |
| 2295 | } |
| 2296 | |
| 2297 | /// Return true if this shuffle mask is an extract subvector mask. |
| 2298 | bool isExtractSubvectorMask(int &Index) const { |
| 2299 | // Not possible to express a shuffle mask for a scalable vector for this |
| 2300 | // case. |
| 2301 | if (isa<ScalableVectorType>(getType())) |
| 2302 | return false; |
| 2303 | |
| 2304 | int NumSrcElts = |
| 2305 | cast<FixedVectorType>(Op<0>()->getType())->getNumElements(); |
| 2306 | return isExtractSubvectorMask(ShuffleMask, NumSrcElts, Index); |
| 2307 | } |
| 2308 | |
| 2309 | /// Change values in a shuffle permute mask assuming the two vector operands |
| 2310 | /// of length InVecNumElts have swapped position. |
| 2311 | static void commuteShuffleMask(MutableArrayRef<int> Mask, |
| 2312 | unsigned InVecNumElts) { |
| 2313 | for (int &Idx : Mask) { |
| 2314 | if (Idx == -1) |
| 2315 | continue; |
| 2316 | Idx = Idx < (int)InVecNumElts ? Idx + InVecNumElts : Idx - InVecNumElts; |
| 2317 | assert(Idx >= 0 && Idx < (int)InVecNumElts * 2 &&((void)0) |
| 2318 | "shufflevector mask index out of range")((void)0); |
| 2319 | } |
| 2320 | } |
| 2321 | |
| 2322 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 2323 | static bool classof(const Instruction *I) { |
| 2324 | return I->getOpcode() == Instruction::ShuffleVector; |
| 2325 | } |
| 2326 | static bool classof(const Value *V) { |
| 2327 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 2328 | } |
| 2329 | }; |
| 2330 | |
| 2331 | template <> |
| 2332 | struct OperandTraits<ShuffleVectorInst> |
| 2333 | : public FixedNumOperandTraits<ShuffleVectorInst, 2> {}; |
| 2334 | |
| 2335 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ShuffleVectorInst, Value)ShuffleVectorInst::op_iterator ShuffleVectorInst::op_begin() { return OperandTraits<ShuffleVectorInst>::op_begin(this ); } ShuffleVectorInst::const_op_iterator ShuffleVectorInst:: op_begin() const { return OperandTraits<ShuffleVectorInst> ::op_begin(const_cast<ShuffleVectorInst*>(this)); } ShuffleVectorInst ::op_iterator ShuffleVectorInst::op_end() { return OperandTraits <ShuffleVectorInst>::op_end(this); } ShuffleVectorInst:: const_op_iterator ShuffleVectorInst::op_end() const { return OperandTraits <ShuffleVectorInst>::op_end(const_cast<ShuffleVectorInst *>(this)); } Value *ShuffleVectorInst::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null<Value >( OperandTraits<ShuffleVectorInst>::op_begin(const_cast <ShuffleVectorInst*>(this))[i_nocapture].get()); } void ShuffleVectorInst::setOperand(unsigned i_nocapture, Value *Val_nocapture ) { ((void)0); OperandTraits<ShuffleVectorInst>::op_begin (this)[i_nocapture] = Val_nocapture; } unsigned ShuffleVectorInst ::getNumOperands() const { return OperandTraits<ShuffleVectorInst >::operands(this); } template <int Idx_nocapture> Use &ShuffleVectorInst::Op() { return this->OpFrom<Idx_nocapture >(this); } template <int Idx_nocapture> const Use & ShuffleVectorInst::Op() const { return this->OpFrom<Idx_nocapture >(this); } |
| 2336 | |
| 2337 | //===----------------------------------------------------------------------===// |
| 2338 | // ExtractValueInst Class |
| 2339 | //===----------------------------------------------------------------------===// |
| 2340 | |
| 2341 | /// This instruction extracts a struct member or array |
| 2342 | /// element value from an aggregate value. |
| 2343 | /// |
| 2344 | class ExtractValueInst : public UnaryInstruction { |
| 2345 | SmallVector<unsigned, 4> Indices; |
| 2346 | |
| 2347 | ExtractValueInst(const ExtractValueInst &EVI); |
| 2348 | |
| 2349 | /// Constructors - Create a extractvalue instruction with a base aggregate |
| 2350 | /// value and a list of indices. The first ctor can optionally insert before |
| 2351 | /// an existing instruction, the second appends the new instruction to the |
| 2352 | /// specified BasicBlock. |
| 2353 | inline ExtractValueInst(Value *Agg, |
| 2354 | ArrayRef<unsigned> Idxs, |
| 2355 | const Twine &NameStr, |
| 2356 | Instruction *InsertBefore); |
| 2357 | inline ExtractValueInst(Value *Agg, |
| 2358 | ArrayRef<unsigned> Idxs, |
| 2359 | const Twine &NameStr, BasicBlock *InsertAtEnd); |
| 2360 | |
| 2361 | void init(ArrayRef<unsigned> Idxs, const Twine &NameStr); |
| 2362 | |
| 2363 | protected: |
| 2364 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 2365 | friend class Instruction; |
| 2366 | |
| 2367 | ExtractValueInst *cloneImpl() const; |
| 2368 | |
| 2369 | public: |
| 2370 | static ExtractValueInst *Create(Value *Agg, |
| 2371 | ArrayRef<unsigned> Idxs, |
| 2372 | const Twine &NameStr = "", |
| 2373 | Instruction *InsertBefore = nullptr) { |
| 2374 | return new |
| 2375 | ExtractValueInst(Agg, Idxs, NameStr, InsertBefore); |
| 2376 | } |
| 2377 | |
| 2378 | static ExtractValueInst *Create(Value *Agg, |
| 2379 | ArrayRef<unsigned> Idxs, |
| 2380 | const Twine &NameStr, |
| 2381 | BasicBlock *InsertAtEnd) { |
| 2382 | return new ExtractValueInst(Agg, Idxs, NameStr, InsertAtEnd); |
| 2383 | } |
| 2384 | |
| 2385 | /// Returns the type of the element that would be extracted |
| 2386 | /// with an extractvalue instruction with the specified parameters. |
| 2387 | /// |
| 2388 | /// Null is returned if the indices are invalid for the specified type. |
| 2389 | static Type *getIndexedType(Type *Agg, ArrayRef<unsigned> Idxs); |
| 2390 | |
| 2391 | using idx_iterator = const unsigned*; |
| 2392 | |
| 2393 | inline idx_iterator idx_begin() const { return Indices.begin(); } |
| 2394 | inline idx_iterator idx_end() const { return Indices.end(); } |
| 2395 | inline iterator_range<idx_iterator> indices() const { |
| 2396 | return make_range(idx_begin(), idx_end()); |
| 2397 | } |
| 2398 | |
| 2399 | Value *getAggregateOperand() { |
| 2400 | return getOperand(0); |
| 2401 | } |
| 2402 | const Value *getAggregateOperand() const { |
| 2403 | return getOperand(0); |
| 2404 | } |
| 2405 | static unsigned getAggregateOperandIndex() { |
| 2406 | return 0U; // get index for modifying correct operand |
| 2407 | } |
| 2408 | |
| 2409 | ArrayRef<unsigned> getIndices() const { |
| 2410 | return Indices; |
| 2411 | } |
| 2412 | |
| 2413 | unsigned getNumIndices() const { |
| 2414 | return (unsigned)Indices.size(); |
| 2415 | } |
| 2416 | |
| 2417 | bool hasIndices() const { |
| 2418 | return true; |
| 2419 | } |
| 2420 | |
| 2421 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 2422 | static bool classof(const Instruction *I) { |
| 2423 | return I->getOpcode() == Instruction::ExtractValue; |
| 2424 | } |
| 2425 | static bool classof(const Value *V) { |
| 2426 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 2427 | } |
| 2428 | }; |
| 2429 | |
| 2430 | ExtractValueInst::ExtractValueInst(Value *Agg, |
| 2431 | ArrayRef<unsigned> Idxs, |
| 2432 | const Twine &NameStr, |
| 2433 | Instruction *InsertBefore) |
| 2434 | : UnaryInstruction(checkGEPType(getIndexedType(Agg->getType(), Idxs)), |
| 2435 | ExtractValue, Agg, InsertBefore) { |
| 2436 | init(Idxs, NameStr); |
| 2437 | } |
| 2438 | |
| 2439 | ExtractValueInst::ExtractValueInst(Value *Agg, |
| 2440 | ArrayRef<unsigned> Idxs, |
| 2441 | const Twine &NameStr, |
| 2442 | BasicBlock *InsertAtEnd) |
| 2443 | : UnaryInstruction(checkGEPType(getIndexedType(Agg->getType(), Idxs)), |
| 2444 | ExtractValue, Agg, InsertAtEnd) { |
| 2445 | init(Idxs, NameStr); |
| 2446 | } |
| 2447 | |
| 2448 | //===----------------------------------------------------------------------===// |
| 2449 | // InsertValueInst Class |
| 2450 | //===----------------------------------------------------------------------===// |
| 2451 | |
| 2452 | /// This instruction inserts a struct field of array element |
| 2453 | /// value into an aggregate value. |
| 2454 | /// |
| 2455 | class InsertValueInst : public Instruction { |
| 2456 | SmallVector<unsigned, 4> Indices; |
| 2457 | |
| 2458 | InsertValueInst(const InsertValueInst &IVI); |
| 2459 | |
| 2460 | /// Constructors - Create a insertvalue instruction with a base aggregate |
| 2461 | /// value, a value to insert, and a list of indices. The first ctor can |
| 2462 | /// optionally insert before an existing instruction, the second appends |
| 2463 | /// the new instruction to the specified BasicBlock. |
| 2464 | inline InsertValueInst(Value *Agg, Value *Val, |
| 2465 | ArrayRef<unsigned> Idxs, |
| 2466 | const Twine &NameStr, |
| 2467 | Instruction *InsertBefore); |
| 2468 | inline InsertValueInst(Value *Agg, Value *Val, |
| 2469 | ArrayRef<unsigned> Idxs, |
| 2470 | const Twine &NameStr, BasicBlock *InsertAtEnd); |
| 2471 | |
| 2472 | /// Constructors - These two constructors are convenience methods because one |
| 2473 | /// and two index insertvalue instructions are so common. |
| 2474 | InsertValueInst(Value *Agg, Value *Val, unsigned Idx, |
| 2475 | const Twine &NameStr = "", |
| 2476 | Instruction *InsertBefore = nullptr); |
| 2477 | InsertValueInst(Value *Agg, Value *Val, unsigned Idx, const Twine &NameStr, |
| 2478 | BasicBlock *InsertAtEnd); |
| 2479 | |
| 2480 | void init(Value *Agg, Value *Val, ArrayRef<unsigned> Idxs, |
| 2481 | const Twine &NameStr); |
| 2482 | |
| 2483 | protected: |
| 2484 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 2485 | friend class Instruction; |
| 2486 | |
| 2487 | InsertValueInst *cloneImpl() const; |
| 2488 | |
| 2489 | public: |
| 2490 | // allocate space for exactly two operands |
| 2491 | void *operator new(size_t S) { return User::operator new(S, 2); } |
| 2492 | void operator delete(void *Ptr) { User::operator delete(Ptr); } |
| 2493 | |
| 2494 | static InsertValueInst *Create(Value *Agg, Value *Val, |
| 2495 | ArrayRef<unsigned> Idxs, |
| 2496 | const Twine &NameStr = "", |
| 2497 | Instruction *InsertBefore = nullptr) { |
| 2498 | return new InsertValueInst(Agg, Val, Idxs, NameStr, InsertBefore); |
| 2499 | } |
| 2500 | |
| 2501 | static InsertValueInst *Create(Value *Agg, Value *Val, |
| 2502 | ArrayRef<unsigned> Idxs, |
| 2503 | const Twine &NameStr, |
| 2504 | BasicBlock *InsertAtEnd) { |
| 2505 | return new InsertValueInst(Agg, Val, Idxs, NameStr, InsertAtEnd); |
| 2506 | } |
| 2507 | |
| 2508 | /// Transparently provide more efficient getOperand methods. |
| 2509 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 2510 | |
| 2511 | using idx_iterator = const unsigned*; |
| 2512 | |
| 2513 | inline idx_iterator idx_begin() const { return Indices.begin(); } |
| 2514 | inline idx_iterator idx_end() const { return Indices.end(); } |
| 2515 | inline iterator_range<idx_iterator> indices() const { |
| 2516 | return make_range(idx_begin(), idx_end()); |
| 2517 | } |
| 2518 | |
| 2519 | Value *getAggregateOperand() { |
| 2520 | return getOperand(0); |
| 2521 | } |
| 2522 | const Value *getAggregateOperand() const { |
| 2523 | return getOperand(0); |
| 2524 | } |
| 2525 | static unsigned getAggregateOperandIndex() { |
| 2526 | return 0U; // get index for modifying correct operand |
| 2527 | } |
| 2528 | |
| 2529 | Value *getInsertedValueOperand() { |
| 2530 | return getOperand(1); |
| 2531 | } |
| 2532 | const Value *getInsertedValueOperand() const { |
| 2533 | return getOperand(1); |
| 2534 | } |
| 2535 | static unsigned getInsertedValueOperandIndex() { |
| 2536 | return 1U; // get index for modifying correct operand |
| 2537 | } |
| 2538 | |
| 2539 | ArrayRef<unsigned> getIndices() const { |
| 2540 | return Indices; |
| 2541 | } |
| 2542 | |
| 2543 | unsigned getNumIndices() const { |
| 2544 | return (unsigned)Indices.size(); |
| 2545 | } |
| 2546 | |
| 2547 | bool hasIndices() const { |
| 2548 | return true; |
| 2549 | } |
| 2550 | |
| 2551 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 2552 | static bool classof(const Instruction *I) { |
| 2553 | return I->getOpcode() == Instruction::InsertValue; |
| 2554 | } |
| 2555 | static bool classof(const Value *V) { |
| 2556 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 2557 | } |
| 2558 | }; |
| 2559 | |
| 2560 | template <> |
| 2561 | struct OperandTraits<InsertValueInst> : |
| 2562 | public FixedNumOperandTraits<InsertValueInst, 2> { |
| 2563 | }; |
| 2564 | |
| 2565 | InsertValueInst::InsertValueInst(Value *Agg, |
| 2566 | Value *Val, |
| 2567 | ArrayRef<unsigned> Idxs, |
| 2568 | const Twine &NameStr, |
| 2569 | Instruction *InsertBefore) |
| 2570 | : Instruction(Agg->getType(), InsertValue, |
| 2571 | OperandTraits<InsertValueInst>::op_begin(this), |
| 2572 | 2, InsertBefore) { |
| 2573 | init(Agg, Val, Idxs, NameStr); |
| 2574 | } |
| 2575 | |
| 2576 | InsertValueInst::InsertValueInst(Value *Agg, |
| 2577 | Value *Val, |
| 2578 | ArrayRef<unsigned> Idxs, |
| 2579 | const Twine &NameStr, |
| 2580 | BasicBlock *InsertAtEnd) |
| 2581 | : Instruction(Agg->getType(), InsertValue, |
| 2582 | OperandTraits<InsertValueInst>::op_begin(this), |
| 2583 | 2, InsertAtEnd) { |
| 2584 | init(Agg, Val, Idxs, NameStr); |
| 2585 | } |
| 2586 | |
| 2587 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(InsertValueInst, Value)InsertValueInst::op_iterator InsertValueInst::op_begin() { return OperandTraits<InsertValueInst>::op_begin(this); } InsertValueInst ::const_op_iterator InsertValueInst::op_begin() const { return OperandTraits<InsertValueInst>::op_begin(const_cast< InsertValueInst*>(this)); } InsertValueInst::op_iterator InsertValueInst ::op_end() { return OperandTraits<InsertValueInst>::op_end (this); } InsertValueInst::const_op_iterator InsertValueInst:: op_end() const { return OperandTraits<InsertValueInst>:: op_end(const_cast<InsertValueInst*>(this)); } Value *InsertValueInst ::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null <Value>( OperandTraits<InsertValueInst>::op_begin (const_cast<InsertValueInst*>(this))[i_nocapture].get() ); } void InsertValueInst::setOperand(unsigned i_nocapture, Value *Val_nocapture) { ((void)0); OperandTraits<InsertValueInst >::op_begin(this)[i_nocapture] = Val_nocapture; } unsigned InsertValueInst::getNumOperands() const { return OperandTraits <InsertValueInst>::operands(this); } template <int Idx_nocapture > Use &InsertValueInst::Op() { return this->OpFrom< Idx_nocapture>(this); } template <int Idx_nocapture> const Use &InsertValueInst::Op() const { return this-> OpFrom<Idx_nocapture>(this); } |
| 2588 | |
| 2589 | //===----------------------------------------------------------------------===// |
| 2590 | // PHINode Class |
| 2591 | //===----------------------------------------------------------------------===// |
| 2592 | |
| 2593 | // PHINode - The PHINode class is used to represent the magical mystical PHI |
| 2594 | // node, that can not exist in nature, but can be synthesized in a computer |
| 2595 | // scientist's overactive imagination. |
| 2596 | // |
| 2597 | class PHINode : public Instruction { |
| 2598 | /// The number of operands actually allocated. NumOperands is |
| 2599 | /// the number actually in use. |
| 2600 | unsigned ReservedSpace; |
| 2601 | |
| 2602 | PHINode(const PHINode &PN); |
| 2603 | |
| 2604 | explicit PHINode(Type *Ty, unsigned NumReservedValues, |
| 2605 | const Twine &NameStr = "", |
| 2606 | Instruction *InsertBefore = nullptr) |
| 2607 | : Instruction(Ty, Instruction::PHI, nullptr, 0, InsertBefore), |
| 2608 | ReservedSpace(NumReservedValues) { |
| 2609 | assert(!Ty->isTokenTy() && "PHI nodes cannot have token type!")((void)0); |
| 2610 | setName(NameStr); |
| 2611 | allocHungoffUses(ReservedSpace); |
| 2612 | } |
| 2613 | |
| 2614 | PHINode(Type *Ty, unsigned NumReservedValues, const Twine &NameStr, |
| 2615 | BasicBlock *InsertAtEnd) |
| 2616 | : Instruction(Ty, Instruction::PHI, nullptr, 0, InsertAtEnd), |
| 2617 | ReservedSpace(NumReservedValues) { |
| 2618 | assert(!Ty->isTokenTy() && "PHI nodes cannot have token type!")((void)0); |
| 2619 | setName(NameStr); |
| 2620 | allocHungoffUses(ReservedSpace); |
| 2621 | } |
| 2622 | |
| 2623 | protected: |
| 2624 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 2625 | friend class Instruction; |
| 2626 | |
| 2627 | PHINode *cloneImpl() const; |
| 2628 | |
| 2629 | // allocHungoffUses - this is more complicated than the generic |
| 2630 | // User::allocHungoffUses, because we have to allocate Uses for the incoming |
| 2631 | // values and pointers to the incoming blocks, all in one allocation. |
| 2632 | void allocHungoffUses(unsigned N) { |
| 2633 | User::allocHungoffUses(N, /* IsPhi */ true); |
| 2634 | } |
| 2635 | |
| 2636 | public: |
| 2637 | /// Constructors - NumReservedValues is a hint for the number of incoming |
| 2638 | /// edges that this phi node will have (use 0 if you really have no idea). |
| 2639 | static PHINode *Create(Type *Ty, unsigned NumReservedValues, |
| 2640 | const Twine &NameStr = "", |
| 2641 | Instruction *InsertBefore = nullptr) { |
| 2642 | return new PHINode(Ty, NumReservedValues, NameStr, InsertBefore); |
| 2643 | } |
| 2644 | |
| 2645 | static PHINode *Create(Type *Ty, unsigned NumReservedValues, |
| 2646 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 2647 | return new PHINode(Ty, NumReservedValues, NameStr, InsertAtEnd); |
| 2648 | } |
| 2649 | |
| 2650 | /// Provide fast operand accessors |
| 2651 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 2652 | |
| 2653 | // Block iterator interface. This provides access to the list of incoming |
| 2654 | // basic blocks, which parallels the list of incoming values. |
| 2655 | |
| 2656 | using block_iterator = BasicBlock **; |
| 2657 | using const_block_iterator = BasicBlock * const *; |
| 2658 | |
| 2659 | block_iterator block_begin() { |
| 2660 | return reinterpret_cast<block_iterator>(op_begin() + ReservedSpace); |
| 2661 | } |
| 2662 | |
| 2663 | const_block_iterator block_begin() const { |
| 2664 | return reinterpret_cast<const_block_iterator>(op_begin() + ReservedSpace); |
| 2665 | } |
| 2666 | |
| 2667 | block_iterator block_end() { |
| 2668 | return block_begin() + getNumOperands(); |
| 2669 | } |
| 2670 | |
| 2671 | const_block_iterator block_end() const { |
| 2672 | return block_begin() + getNumOperands(); |
| 2673 | } |
| 2674 | |
| 2675 | iterator_range<block_iterator> blocks() { |
| 2676 | return make_range(block_begin(), block_end()); |
| 2677 | } |
| 2678 | |
| 2679 | iterator_range<const_block_iterator> blocks() const { |
| 2680 | return make_range(block_begin(), block_end()); |
| 2681 | } |
| 2682 | |
| 2683 | op_range incoming_values() { return operands(); } |
| 2684 | |
| 2685 | const_op_range incoming_values() const { return operands(); } |
| 2686 | |
| 2687 | /// Return the number of incoming edges |
| 2688 | /// |
| 2689 | unsigned getNumIncomingValues() const { return getNumOperands(); } |
| 2690 | |
| 2691 | /// Return incoming value number x |
| 2692 | /// |
| 2693 | Value *getIncomingValue(unsigned i) const { |
| 2694 | return getOperand(i); |
| 2695 | } |
| 2696 | void setIncomingValue(unsigned i, Value *V) { |
| 2697 | assert(V && "PHI node got a null value!")((void)0); |
| 2698 | assert(getType() == V->getType() &&((void)0) |
| 2699 | "All operands to PHI node must be the same type as the PHI node!")((void)0); |
| 2700 | setOperand(i, V); |
| 2701 | } |
| 2702 | |
| 2703 | static unsigned getOperandNumForIncomingValue(unsigned i) { |
| 2704 | return i; |
| 2705 | } |
| 2706 | |
| 2707 | static unsigned getIncomingValueNumForOperand(unsigned i) { |
| 2708 | return i; |
| 2709 | } |
| 2710 | |
| 2711 | /// Return incoming basic block number @p i. |
| 2712 | /// |
| 2713 | BasicBlock *getIncomingBlock(unsigned i) const { |
| 2714 | return block_begin()[i]; |
| 2715 | } |
| 2716 | |
| 2717 | /// Return incoming basic block corresponding |
| 2718 | /// to an operand of the PHI. |
| 2719 | /// |
| 2720 | BasicBlock *getIncomingBlock(const Use &U) const { |
| 2721 | assert(this == U.getUser() && "Iterator doesn't point to PHI's Uses?")((void)0); |
| 2722 | return getIncomingBlock(unsigned(&U - op_begin())); |
| 2723 | } |
| 2724 | |
| 2725 | /// Return incoming basic block corresponding |
| 2726 | /// to value use iterator. |
| 2727 | /// |
| 2728 | BasicBlock *getIncomingBlock(Value::const_user_iterator I) const { |
| 2729 | return getIncomingBlock(I.getUse()); |
| 2730 | } |
| 2731 | |
| 2732 | void setIncomingBlock(unsigned i, BasicBlock *BB) { |
| 2733 | assert(BB && "PHI node got a null basic block!")((void)0); |
| 2734 | block_begin()[i] = BB; |
| 2735 | } |
| 2736 | |
| 2737 | /// Replace every incoming basic block \p Old to basic block \p New. |
| 2738 | void replaceIncomingBlockWith(const BasicBlock *Old, BasicBlock *New) { |
| 2739 | assert(New && Old && "PHI node got a null basic block!")((void)0); |
| 2740 | for (unsigned Op = 0, NumOps = getNumOperands(); Op != NumOps; ++Op) |
| 2741 | if (getIncomingBlock(Op) == Old) |
| 2742 | setIncomingBlock(Op, New); |
| 2743 | } |
| 2744 | |
| 2745 | /// Add an incoming value to the end of the PHI list |
| 2746 | /// |
| 2747 | void addIncoming(Value *V, BasicBlock *BB) { |
| 2748 | if (getNumOperands() == ReservedSpace) |
| 2749 | growOperands(); // Get more space! |
| 2750 | // Initialize some new operands. |
| 2751 | setNumHungOffUseOperands(getNumOperands() + 1); |
| 2752 | setIncomingValue(getNumOperands() - 1, V); |
| 2753 | setIncomingBlock(getNumOperands() - 1, BB); |
| 2754 | } |
| 2755 | |
| 2756 | /// Remove an incoming value. This is useful if a |
| 2757 | /// predecessor basic block is deleted. The value removed is returned. |
| 2758 | /// |
| 2759 | /// If the last incoming value for a PHI node is removed (and DeletePHIIfEmpty |
| 2760 | /// is true), the PHI node is destroyed and any uses of it are replaced with |
| 2761 | /// dummy values. The only time there should be zero incoming values to a PHI |
| 2762 | /// node is when the block is dead, so this strategy is sound. |
| 2763 | /// |
| 2764 | Value *removeIncomingValue(unsigned Idx, bool DeletePHIIfEmpty = true); |
| 2765 | |
| 2766 | Value *removeIncomingValue(const BasicBlock *BB, bool DeletePHIIfEmpty=true) { |
| 2767 | int Idx = getBasicBlockIndex(BB); |
| 2768 | assert(Idx >= 0 && "Invalid basic block argument to remove!")((void)0); |
| 2769 | return removeIncomingValue(Idx, DeletePHIIfEmpty); |
| 2770 | } |
| 2771 | |
| 2772 | /// Return the first index of the specified basic |
| 2773 | /// block in the value list for this PHI. Returns -1 if no instance. |
| 2774 | /// |
| 2775 | int getBasicBlockIndex(const BasicBlock *BB) const { |
| 2776 | for (unsigned i = 0, e = getNumOperands(); i != e; ++i) |
| 2777 | if (block_begin()[i] == BB) |
| 2778 | return i; |
| 2779 | return -1; |
| 2780 | } |
| 2781 | |
| 2782 | Value *getIncomingValueForBlock(const BasicBlock *BB) const { |
| 2783 | int Idx = getBasicBlockIndex(BB); |
| 2784 | assert(Idx >= 0 && "Invalid basic block argument!")((void)0); |
| 2785 | return getIncomingValue(Idx); |
| 2786 | } |
| 2787 | |
| 2788 | /// Set every incoming value(s) for block \p BB to \p V. |
| 2789 | void setIncomingValueForBlock(const BasicBlock *BB, Value *V) { |
| 2790 | assert(BB && "PHI node got a null basic block!")((void)0); |
| 2791 | bool Found = false; |
| 2792 | for (unsigned Op = 0, NumOps = getNumOperands(); Op != NumOps; ++Op) |
| 2793 | if (getIncomingBlock(Op) == BB) { |
| 2794 | Found = true; |
| 2795 | setIncomingValue(Op, V); |
| 2796 | } |
| 2797 | (void)Found; |
| 2798 | assert(Found && "Invalid basic block argument to set!")((void)0); |
| 2799 | } |
| 2800 | |
| 2801 | /// If the specified PHI node always merges together the |
| 2802 | /// same value, return the value, otherwise return null. |
| 2803 | Value *hasConstantValue() const; |
| 2804 | |
| 2805 | /// Whether the specified PHI node always merges |
| 2806 | /// together the same value, assuming undefs are equal to a unique |
| 2807 | /// non-undef value. |
| 2808 | bool hasConstantOrUndefValue() const; |
| 2809 | |
| 2810 | /// If the PHI node is complete which means all of its parent's predecessors |
| 2811 | /// have incoming value in this PHI, return true, otherwise return false. |
| 2812 | bool isComplete() const { |
| 2813 | return llvm::all_of(predecessors(getParent()), |
| 2814 | [this](const BasicBlock *Pred) { |
| 2815 | return getBasicBlockIndex(Pred) >= 0; |
| 2816 | }); |
| 2817 | } |
| 2818 | |
| 2819 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 2820 | static bool classof(const Instruction *I) { |
| 2821 | return I->getOpcode() == Instruction::PHI; |
| 2822 | } |
| 2823 | static bool classof(const Value *V) { |
| 2824 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 2825 | } |
| 2826 | |
| 2827 | private: |
| 2828 | void growOperands(); |
| 2829 | }; |
| 2830 | |
| 2831 | template <> |
| 2832 | struct OperandTraits<PHINode> : public HungoffOperandTraits<2> { |
| 2833 | }; |
| 2834 | |
| 2835 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(PHINode, Value)PHINode::op_iterator PHINode::op_begin() { return OperandTraits <PHINode>::op_begin(this); } PHINode::const_op_iterator PHINode::op_begin() const { return OperandTraits<PHINode> ::op_begin(const_cast<PHINode*>(this)); } PHINode::op_iterator PHINode::op_end() { return OperandTraits<PHINode>::op_end (this); } PHINode::const_op_iterator PHINode::op_end() const { return OperandTraits<PHINode>::op_end(const_cast<PHINode *>(this)); } Value *PHINode::getOperand(unsigned i_nocapture ) const { ((void)0); return cast_or_null<Value>( OperandTraits <PHINode>::op_begin(const_cast<PHINode*>(this))[i_nocapture ].get()); } void PHINode::setOperand(unsigned i_nocapture, Value *Val_nocapture) { ((void)0); OperandTraits<PHINode>::op_begin (this)[i_nocapture] = Val_nocapture; } unsigned PHINode::getNumOperands () const { return OperandTraits<PHINode>::operands(this ); } template <int Idx_nocapture> Use &PHINode::Op( ) { return this->OpFrom<Idx_nocapture>(this); } template <int Idx_nocapture> const Use &PHINode::Op() const { return this->OpFrom<Idx_nocapture>(this); } |
| 2836 | |
| 2837 | //===----------------------------------------------------------------------===// |
| 2838 | // LandingPadInst Class |
| 2839 | //===----------------------------------------------------------------------===// |
| 2840 | |
| 2841 | //===--------------------------------------------------------------------------- |
| 2842 | /// The landingpad instruction holds all of the information |
| 2843 | /// necessary to generate correct exception handling. The landingpad instruction |
| 2844 | /// cannot be moved from the top of a landing pad block, which itself is |
| 2845 | /// accessible only from the 'unwind' edge of an invoke. This uses the |
| 2846 | /// SubclassData field in Value to store whether or not the landingpad is a |
| 2847 | /// cleanup. |
| 2848 | /// |
| 2849 | class LandingPadInst : public Instruction { |
| 2850 | using CleanupField = BoolBitfieldElementT<0>; |
| 2851 | |
| 2852 | /// The number of operands actually allocated. NumOperands is |
| 2853 | /// the number actually in use. |
| 2854 | unsigned ReservedSpace; |
| 2855 | |
| 2856 | LandingPadInst(const LandingPadInst &LP); |
| 2857 | |
| 2858 | public: |
| 2859 | enum ClauseType { Catch, Filter }; |
| 2860 | |
| 2861 | private: |
| 2862 | explicit LandingPadInst(Type *RetTy, unsigned NumReservedValues, |
| 2863 | const Twine &NameStr, Instruction *InsertBefore); |
| 2864 | explicit LandingPadInst(Type *RetTy, unsigned NumReservedValues, |
| 2865 | const Twine &NameStr, BasicBlock *InsertAtEnd); |
| 2866 | |
| 2867 | // Allocate space for exactly zero operands. |
| 2868 | void *operator new(size_t S) { return User::operator new(S); } |
| 2869 | |
| 2870 | void growOperands(unsigned Size); |
| 2871 | void init(unsigned NumReservedValues, const Twine &NameStr); |
| 2872 | |
| 2873 | protected: |
| 2874 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 2875 | friend class Instruction; |
| 2876 | |
| 2877 | LandingPadInst *cloneImpl() const; |
| 2878 | |
| 2879 | public: |
| 2880 | void operator delete(void *Ptr) { User::operator delete(Ptr); } |
| 2881 | |
| 2882 | /// Constructors - NumReservedClauses is a hint for the number of incoming |
| 2883 | /// clauses that this landingpad will have (use 0 if you really have no idea). |
| 2884 | static LandingPadInst *Create(Type *RetTy, unsigned NumReservedClauses, |
| 2885 | const Twine &NameStr = "", |
| 2886 | Instruction *InsertBefore = nullptr); |
| 2887 | static LandingPadInst *Create(Type *RetTy, unsigned NumReservedClauses, |
| 2888 | const Twine &NameStr, BasicBlock *InsertAtEnd); |
| 2889 | |
| 2890 | /// Provide fast operand accessors |
| 2891 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 2892 | |
| 2893 | /// Return 'true' if this landingpad instruction is a |
| 2894 | /// cleanup. I.e., it should be run when unwinding even if its landing pad |
| 2895 | /// doesn't catch the exception. |
| 2896 | bool isCleanup() const { return getSubclassData<CleanupField>(); } |
| 2897 | |
| 2898 | /// Indicate that this landingpad instruction is a cleanup. |
| 2899 | void setCleanup(bool V) { setSubclassData<CleanupField>(V); } |
| 2900 | |
| 2901 | /// Add a catch or filter clause to the landing pad. |
| 2902 | void addClause(Constant *ClauseVal); |
| 2903 | |
| 2904 | /// Get the value of the clause at index Idx. Use isCatch/isFilter to |
| 2905 | /// determine what type of clause this is. |
| 2906 | Constant *getClause(unsigned Idx) const { |
| 2907 | return cast<Constant>(getOperandList()[Idx]); |
| 2908 | } |
| 2909 | |
| 2910 | /// Return 'true' if the clause and index Idx is a catch clause. |
| 2911 | bool isCatch(unsigned Idx) const { |
| 2912 | return !isa<ArrayType>(getOperandList()[Idx]->getType()); |
| 2913 | } |
| 2914 | |
| 2915 | /// Return 'true' if the clause and index Idx is a filter clause. |
| 2916 | bool isFilter(unsigned Idx) const { |
| 2917 | return isa<ArrayType>(getOperandList()[Idx]->getType()); |
| 2918 | } |
| 2919 | |
| 2920 | /// Get the number of clauses for this landing pad. |
| 2921 | unsigned getNumClauses() const { return getNumOperands(); } |
| 2922 | |
| 2923 | /// Grow the size of the operand list to accommodate the new |
| 2924 | /// number of clauses. |
| 2925 | void reserveClauses(unsigned Size) { growOperands(Size); } |
| 2926 | |
| 2927 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 2928 | static bool classof(const Instruction *I) { |
| 2929 | return I->getOpcode() == Instruction::LandingPad; |
| 2930 | } |
| 2931 | static bool classof(const Value *V) { |
| 2932 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 2933 | } |
| 2934 | }; |
| 2935 | |
| 2936 | template <> |
| 2937 | struct OperandTraits<LandingPadInst> : public HungoffOperandTraits<1> { |
| 2938 | }; |
| 2939 | |
| 2940 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(LandingPadInst, Value)LandingPadInst::op_iterator LandingPadInst::op_begin() { return OperandTraits<LandingPadInst>::op_begin(this); } LandingPadInst ::const_op_iterator LandingPadInst::op_begin() const { return OperandTraits<LandingPadInst>::op_begin(const_cast< LandingPadInst*>(this)); } LandingPadInst::op_iterator LandingPadInst ::op_end() { return OperandTraits<LandingPadInst>::op_end (this); } LandingPadInst::const_op_iterator LandingPadInst::op_end () const { return OperandTraits<LandingPadInst>::op_end (const_cast<LandingPadInst*>(this)); } Value *LandingPadInst ::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null <Value>( OperandTraits<LandingPadInst>::op_begin( const_cast<LandingPadInst*>(this))[i_nocapture].get()); } void LandingPadInst::setOperand(unsigned i_nocapture, Value *Val_nocapture) { ((void)0); OperandTraits<LandingPadInst >::op_begin(this)[i_nocapture] = Val_nocapture; } unsigned LandingPadInst::getNumOperands() const { return OperandTraits <LandingPadInst>::operands(this); } template <int Idx_nocapture > Use &LandingPadInst::Op() { return this->OpFrom< Idx_nocapture>(this); } template <int Idx_nocapture> const Use &LandingPadInst::Op() const { return this-> OpFrom<Idx_nocapture>(this); } |
| 2941 | |
| 2942 | //===----------------------------------------------------------------------===// |
| 2943 | // ReturnInst Class |
| 2944 | //===----------------------------------------------------------------------===// |
| 2945 | |
| 2946 | //===--------------------------------------------------------------------------- |
| 2947 | /// Return a value (possibly void), from a function. Execution |
| 2948 | /// does not continue in this function any longer. |
| 2949 | /// |
| 2950 | class ReturnInst : public Instruction { |
| 2951 | ReturnInst(const ReturnInst &RI); |
| 2952 | |
| 2953 | private: |
| 2954 | // ReturnInst constructors: |
| 2955 | // ReturnInst() - 'ret void' instruction |
| 2956 | // ReturnInst( null) - 'ret void' instruction |
| 2957 | // ReturnInst(Value* X) - 'ret X' instruction |
| 2958 | // ReturnInst( null, Inst *I) - 'ret void' instruction, insert before I |
| 2959 | // ReturnInst(Value* X, Inst *I) - 'ret X' instruction, insert before I |
| 2960 | // ReturnInst( null, BB *B) - 'ret void' instruction, insert @ end of B |
| 2961 | // ReturnInst(Value* X, BB *B) - 'ret X' instruction, insert @ end of B |
| 2962 | // |
| 2963 | // NOTE: If the Value* passed is of type void then the constructor behaves as |
| 2964 | // if it was passed NULL. |
| 2965 | explicit ReturnInst(LLVMContext &C, Value *retVal = nullptr, |
| 2966 | Instruction *InsertBefore = nullptr); |
| 2967 | ReturnInst(LLVMContext &C, Value *retVal, BasicBlock *InsertAtEnd); |
| 2968 | explicit ReturnInst(LLVMContext &C, BasicBlock *InsertAtEnd); |
| 2969 | |
| 2970 | protected: |
| 2971 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 2972 | friend class Instruction; |
| 2973 | |
| 2974 | ReturnInst *cloneImpl() const; |
| 2975 | |
| 2976 | public: |
| 2977 | static ReturnInst* Create(LLVMContext &C, Value *retVal = nullptr, |
| 2978 | Instruction *InsertBefore = nullptr) { |
| 2979 | return new(!!retVal) ReturnInst(C, retVal, InsertBefore); |
| 2980 | } |
| 2981 | |
| 2982 | static ReturnInst* Create(LLVMContext &C, Value *retVal, |
| 2983 | BasicBlock *InsertAtEnd) { |
| 2984 | return new(!!retVal) ReturnInst(C, retVal, InsertAtEnd); |
| 2985 | } |
| 2986 | |
| 2987 | static ReturnInst* Create(LLVMContext &C, BasicBlock *InsertAtEnd) { |
| 2988 | return new(0) ReturnInst(C, InsertAtEnd); |
| 2989 | } |
| 2990 | |
| 2991 | /// Provide fast operand accessors |
| 2992 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 2993 | |
| 2994 | /// Convenience accessor. Returns null if there is no return value. |
| 2995 | Value *getReturnValue() const { |
| 2996 | return getNumOperands() != 0 ? getOperand(0) : nullptr; |
| 2997 | } |
| 2998 | |
| 2999 | unsigned getNumSuccessors() const { return 0; } |
| 3000 | |
| 3001 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 3002 | static bool classof(const Instruction *I) { |
| 3003 | return (I->getOpcode() == Instruction::Ret); |
| 3004 | } |
| 3005 | static bool classof(const Value *V) { |
| 3006 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 3007 | } |
| 3008 | |
| 3009 | private: |
| 3010 | BasicBlock *getSuccessor(unsigned idx) const { |
| 3011 | llvm_unreachable("ReturnInst has no successors!")__builtin_unreachable(); |
| 3012 | } |
| 3013 | |
| 3014 | void setSuccessor(unsigned idx, BasicBlock *B) { |
| 3015 | llvm_unreachable("ReturnInst has no successors!")__builtin_unreachable(); |
| 3016 | } |
| 3017 | }; |
| 3018 | |
| 3019 | template <> |
| 3020 | struct OperandTraits<ReturnInst> : public VariadicOperandTraits<ReturnInst> { |
| 3021 | }; |
| 3022 | |
| 3023 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ReturnInst, Value)ReturnInst::op_iterator ReturnInst::op_begin() { return OperandTraits <ReturnInst>::op_begin(this); } ReturnInst::const_op_iterator ReturnInst::op_begin() const { return OperandTraits<ReturnInst >::op_begin(const_cast<ReturnInst*>(this)); } ReturnInst ::op_iterator ReturnInst::op_end() { return OperandTraits< ReturnInst>::op_end(this); } ReturnInst::const_op_iterator ReturnInst::op_end() const { return OperandTraits<ReturnInst >::op_end(const_cast<ReturnInst*>(this)); } Value *ReturnInst ::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null <Value>( OperandTraits<ReturnInst>::op_begin(const_cast <ReturnInst*>(this))[i_nocapture].get()); } void ReturnInst ::setOperand(unsigned i_nocapture, Value *Val_nocapture) { (( void)0); OperandTraits<ReturnInst>::op_begin(this)[i_nocapture ] = Val_nocapture; } unsigned ReturnInst::getNumOperands() const { return OperandTraits<ReturnInst>::operands(this); } template <int Idx_nocapture> Use &ReturnInst::Op() { return this->OpFrom<Idx_nocapture>(this); } template <int Idx_nocapture> const Use &ReturnInst::Op() const { return this->OpFrom<Idx_nocapture>(this); } |
| 3024 | |
| 3025 | //===----------------------------------------------------------------------===// |
| 3026 | // BranchInst Class |
| 3027 | //===----------------------------------------------------------------------===// |
| 3028 | |
| 3029 | //===--------------------------------------------------------------------------- |
| 3030 | /// Conditional or Unconditional Branch instruction. |
| 3031 | /// |
| 3032 | class BranchInst : public Instruction { |
| 3033 | /// Ops list - Branches are strange. The operands are ordered: |
| 3034 | /// [Cond, FalseDest,] TrueDest. This makes some accessors faster because |
| 3035 | /// they don't have to check for cond/uncond branchness. These are mostly |
| 3036 | /// accessed relative from op_end(). |
| 3037 | BranchInst(const BranchInst &BI); |
| 3038 | // BranchInst constructors (where {B, T, F} are blocks, and C is a condition): |
| 3039 | // BranchInst(BB *B) - 'br B' |
| 3040 | // BranchInst(BB* T, BB *F, Value *C) - 'br C, T, F' |
| 3041 | // BranchInst(BB* B, Inst *I) - 'br B' insert before I |
| 3042 | // BranchInst(BB* T, BB *F, Value *C, Inst *I) - 'br C, T, F', insert before I |
| 3043 | // BranchInst(BB* B, BB *I) - 'br B' insert at end |
| 3044 | // BranchInst(BB* T, BB *F, Value *C, BB *I) - 'br C, T, F', insert at end |
| 3045 | explicit BranchInst(BasicBlock *IfTrue, Instruction *InsertBefore = nullptr); |
| 3046 | BranchInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond, |
| 3047 | Instruction *InsertBefore = nullptr); |
| 3048 | BranchInst(BasicBlock *IfTrue, BasicBlock *InsertAtEnd); |
| 3049 | BranchInst(BasicBlock *IfTrue, BasicBlock *IfFalse, Value *Cond, |
| 3050 | BasicBlock *InsertAtEnd); |
| 3051 | |
| 3052 | void AssertOK(); |
| 3053 | |
| 3054 | protected: |
| 3055 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 3056 | friend class Instruction; |
| 3057 | |
| 3058 | BranchInst *cloneImpl() const; |
| 3059 | |
| 3060 | public: |
| 3061 | /// Iterator type that casts an operand to a basic block. |
| 3062 | /// |
| 3063 | /// This only makes sense because the successors are stored as adjacent |
| 3064 | /// operands for branch instructions. |
| 3065 | struct succ_op_iterator |
| 3066 | : iterator_adaptor_base<succ_op_iterator, value_op_iterator, |
| 3067 | std::random_access_iterator_tag, BasicBlock *, |
| 3068 | ptrdiff_t, BasicBlock *, BasicBlock *> { |
| 3069 | explicit succ_op_iterator(value_op_iterator I) : iterator_adaptor_base(I) {} |
| 3070 | |
| 3071 | BasicBlock *operator*() const { return cast<BasicBlock>(*I); } |
| 3072 | BasicBlock *operator->() const { return operator*(); } |
| 3073 | }; |
| 3074 | |
| 3075 | /// The const version of `succ_op_iterator`. |
| 3076 | struct const_succ_op_iterator |
| 3077 | : iterator_adaptor_base<const_succ_op_iterator, const_value_op_iterator, |
| 3078 | std::random_access_iterator_tag, |
| 3079 | const BasicBlock *, ptrdiff_t, const BasicBlock *, |
| 3080 | const BasicBlock *> { |
| 3081 | explicit const_succ_op_iterator(const_value_op_iterator I) |
| 3082 | : iterator_adaptor_base(I) {} |
| 3083 | |
| 3084 | const BasicBlock *operator*() const { return cast<BasicBlock>(*I); } |
| 3085 | const BasicBlock *operator->() const { return operator*(); } |
| 3086 | }; |
| 3087 | |
| 3088 | static BranchInst *Create(BasicBlock *IfTrue, |
| 3089 | Instruction *InsertBefore = nullptr) { |
| 3090 | return new(1) BranchInst(IfTrue, InsertBefore); |
| 3091 | } |
| 3092 | |
| 3093 | static BranchInst *Create(BasicBlock *IfTrue, BasicBlock *IfFalse, |
| 3094 | Value *Cond, Instruction *InsertBefore = nullptr) { |
| 3095 | return new(3) BranchInst(IfTrue, IfFalse, Cond, InsertBefore); |
| 3096 | } |
| 3097 | |
| 3098 | static BranchInst *Create(BasicBlock *IfTrue, BasicBlock *InsertAtEnd) { |
| 3099 | return new(1) BranchInst(IfTrue, InsertAtEnd); |
| 3100 | } |
| 3101 | |
| 3102 | static BranchInst *Create(BasicBlock *IfTrue, BasicBlock *IfFalse, |
| 3103 | Value *Cond, BasicBlock *InsertAtEnd) { |
| 3104 | return new(3) BranchInst(IfTrue, IfFalse, Cond, InsertAtEnd); |
| 3105 | } |
| 3106 | |
| 3107 | /// Transparently provide more efficient getOperand methods. |
| 3108 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 3109 | |
| 3110 | bool isUnconditional() const { return getNumOperands() == 1; } |
| 3111 | bool isConditional() const { return getNumOperands() == 3; } |
| 3112 | |
| 3113 | Value *getCondition() const { |
| 3114 | assert(isConditional() && "Cannot get condition of an uncond branch!")((void)0); |
| 3115 | return Op<-3>(); |
| 3116 | } |
| 3117 | |
| 3118 | void setCondition(Value *V) { |
| 3119 | assert(isConditional() && "Cannot set condition of unconditional branch!")((void)0); |
| 3120 | Op<-3>() = V; |
| 3121 | } |
| 3122 | |
| 3123 | unsigned getNumSuccessors() const { return 1+isConditional(); } |
| 3124 | |
| 3125 | BasicBlock *getSuccessor(unsigned i) const { |
| 3126 | assert(i < getNumSuccessors() && "Successor # out of range for Branch!")((void)0); |
| 3127 | return cast_or_null<BasicBlock>((&Op<-1>() - i)->get()); |
| 3128 | } |
| 3129 | |
| 3130 | void setSuccessor(unsigned idx, BasicBlock *NewSucc) { |
| 3131 | assert(idx < getNumSuccessors() && "Successor # out of range for Branch!")((void)0); |
| 3132 | *(&Op<-1>() - idx) = NewSucc; |
| 3133 | } |
| 3134 | |
| 3135 | /// Swap the successors of this branch instruction. |
| 3136 | /// |
| 3137 | /// Swaps the successors of the branch instruction. This also swaps any |
| 3138 | /// branch weight metadata associated with the instruction so that it |
| 3139 | /// continues to map correctly to each operand. |
| 3140 | void swapSuccessors(); |
| 3141 | |
| 3142 | iterator_range<succ_op_iterator> successors() { |
| 3143 | return make_range( |
| 3144 | succ_op_iterator(std::next(value_op_begin(), isConditional() ? 1 : 0)), |
| 3145 | succ_op_iterator(value_op_end())); |
| 3146 | } |
| 3147 | |
| 3148 | iterator_range<const_succ_op_iterator> successors() const { |
| 3149 | return make_range(const_succ_op_iterator( |
| 3150 | std::next(value_op_begin(), isConditional() ? 1 : 0)), |
| 3151 | const_succ_op_iterator(value_op_end())); |
| 3152 | } |
| 3153 | |
| 3154 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 3155 | static bool classof(const Instruction *I) { |
| 3156 | return (I->getOpcode() == Instruction::Br); |
| 3157 | } |
| 3158 | static bool classof(const Value *V) { |
| 3159 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 3160 | } |
| 3161 | }; |
| 3162 | |
| 3163 | template <> |
| 3164 | struct OperandTraits<BranchInst> : public VariadicOperandTraits<BranchInst, 1> { |
| 3165 | }; |
| 3166 | |
| 3167 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(BranchInst, Value)BranchInst::op_iterator BranchInst::op_begin() { return OperandTraits <BranchInst>::op_begin(this); } BranchInst::const_op_iterator BranchInst::op_begin() const { return OperandTraits<BranchInst >::op_begin(const_cast<BranchInst*>(this)); } BranchInst ::op_iterator BranchInst::op_end() { return OperandTraits< BranchInst>::op_end(this); } BranchInst::const_op_iterator BranchInst::op_end() const { return OperandTraits<BranchInst >::op_end(const_cast<BranchInst*>(this)); } Value *BranchInst ::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null <Value>( OperandTraits<BranchInst>::op_begin(const_cast <BranchInst*>(this))[i_nocapture].get()); } void BranchInst ::setOperand(unsigned i_nocapture, Value *Val_nocapture) { (( void)0); OperandTraits<BranchInst>::op_begin(this)[i_nocapture ] = Val_nocapture; } unsigned BranchInst::getNumOperands() const { return OperandTraits<BranchInst>::operands(this); } template <int Idx_nocapture> Use &BranchInst::Op() { return this->OpFrom<Idx_nocapture>(this); } template <int Idx_nocapture> const Use &BranchInst::Op() const { return this->OpFrom<Idx_nocapture>(this); } |
| 3168 | |
| 3169 | //===----------------------------------------------------------------------===// |
| 3170 | // SwitchInst Class |
| 3171 | //===----------------------------------------------------------------------===// |
| 3172 | |
| 3173 | //===--------------------------------------------------------------------------- |
| 3174 | /// Multiway switch |
| 3175 | /// |
| 3176 | class SwitchInst : public Instruction { |
| 3177 | unsigned ReservedSpace; |
| 3178 | |
| 3179 | // Operand[0] = Value to switch on |
| 3180 | // Operand[1] = Default basic block destination |
| 3181 | // Operand[2n ] = Value to match |
| 3182 | // Operand[2n+1] = BasicBlock to go to on match |
| 3183 | SwitchInst(const SwitchInst &SI); |
| 3184 | |
| 3185 | /// Create a new switch instruction, specifying a value to switch on and a |
| 3186 | /// default destination. The number of additional cases can be specified here |
| 3187 | /// to make memory allocation more efficient. This constructor can also |
| 3188 | /// auto-insert before another instruction. |
| 3189 | SwitchInst(Value *Value, BasicBlock *Default, unsigned NumCases, |
| 3190 | Instruction *InsertBefore); |
| 3191 | |
| 3192 | /// Create a new switch instruction, specifying a value to switch on and a |
| 3193 | /// default destination. The number of additional cases can be specified here |
| 3194 | /// to make memory allocation more efficient. This constructor also |
| 3195 | /// auto-inserts at the end of the specified BasicBlock. |
| 3196 | SwitchInst(Value *Value, BasicBlock *Default, unsigned NumCases, |
| 3197 | BasicBlock *InsertAtEnd); |
| 3198 | |
| 3199 | // allocate space for exactly zero operands |
| 3200 | void *operator new(size_t S) { return User::operator new(S); } |
| 3201 | |
| 3202 | void init(Value *Value, BasicBlock *Default, unsigned NumReserved); |
| 3203 | void growOperands(); |
| 3204 | |
| 3205 | protected: |
| 3206 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 3207 | friend class Instruction; |
| 3208 | |
| 3209 | SwitchInst *cloneImpl() const; |
| 3210 | |
| 3211 | public: |
| 3212 | void operator delete(void *Ptr) { User::operator delete(Ptr); } |
| 3213 | |
| 3214 | // -2 |
| 3215 | static const unsigned DefaultPseudoIndex = static_cast<unsigned>(~0L-1); |
| 3216 | |
| 3217 | template <typename CaseHandleT> class CaseIteratorImpl; |
| 3218 | |
| 3219 | /// A handle to a particular switch case. It exposes a convenient interface |
| 3220 | /// to both the case value and the successor block. |
| 3221 | /// |
| 3222 | /// We define this as a template and instantiate it to form both a const and |
| 3223 | /// non-const handle. |
| 3224 | template <typename SwitchInstT, typename ConstantIntT, typename BasicBlockT> |
| 3225 | class CaseHandleImpl { |
| 3226 | // Directly befriend both const and non-const iterators. |
| 3227 | friend class SwitchInst::CaseIteratorImpl< |
| 3228 | CaseHandleImpl<SwitchInstT, ConstantIntT, BasicBlockT>>; |
| 3229 | |
| 3230 | protected: |
| 3231 | // Expose the switch type we're parameterized with to the iterator. |
| 3232 | using SwitchInstType = SwitchInstT; |
| 3233 | |
| 3234 | SwitchInstT *SI; |
| 3235 | ptrdiff_t Index; |
| 3236 | |
| 3237 | CaseHandleImpl() = default; |
| 3238 | CaseHandleImpl(SwitchInstT *SI, ptrdiff_t Index) : SI(SI), Index(Index) {} |
| 3239 | |
| 3240 | public: |
| 3241 | /// Resolves case value for current case. |
| 3242 | ConstantIntT *getCaseValue() const { |
| 3243 | assert((unsigned)Index < SI->getNumCases() &&((void)0) |
| 3244 | "Index out the number of cases.")((void)0); |
| 3245 | return reinterpret_cast<ConstantIntT *>(SI->getOperand(2 + Index * 2)); |
| 3246 | } |
| 3247 | |
| 3248 | /// Resolves successor for current case. |
| 3249 | BasicBlockT *getCaseSuccessor() const { |
| 3250 | assert(((unsigned)Index < SI->getNumCases() ||((void)0) |
| 3251 | (unsigned)Index == DefaultPseudoIndex) &&((void)0) |
| 3252 | "Index out the number of cases.")((void)0); |
| 3253 | return SI->getSuccessor(getSuccessorIndex()); |
| 3254 | } |
| 3255 | |
| 3256 | /// Returns number of current case. |
| 3257 | unsigned getCaseIndex() const { return Index; } |
| 3258 | |
| 3259 | /// Returns successor index for current case successor. |
| 3260 | unsigned getSuccessorIndex() const { |
| 3261 | assert(((unsigned)Index == DefaultPseudoIndex ||((void)0) |
| 3262 | (unsigned)Index < SI->getNumCases()) &&((void)0) |
| 3263 | "Index out the number of cases.")((void)0); |
| 3264 | return (unsigned)Index != DefaultPseudoIndex ? Index + 1 : 0; |
| 3265 | } |
| 3266 | |
| 3267 | bool operator==(const CaseHandleImpl &RHS) const { |
| 3268 | assert(SI == RHS.SI && "Incompatible operators.")((void)0); |
| 3269 | return Index == RHS.Index; |
| 3270 | } |
| 3271 | }; |
| 3272 | |
| 3273 | using ConstCaseHandle = |
| 3274 | CaseHandleImpl<const SwitchInst, const ConstantInt, const BasicBlock>; |
| 3275 | |
| 3276 | class CaseHandle |
| 3277 | : public CaseHandleImpl<SwitchInst, ConstantInt, BasicBlock> { |
| 3278 | friend class SwitchInst::CaseIteratorImpl<CaseHandle>; |
| 3279 | |
| 3280 | public: |
| 3281 | CaseHandle(SwitchInst *SI, ptrdiff_t Index) : CaseHandleImpl(SI, Index) {} |
| 3282 | |
| 3283 | /// Sets the new value for current case. |
| 3284 | void setValue(ConstantInt *V) { |
| 3285 | assert((unsigned)Index < SI->getNumCases() &&((void)0) |
| 3286 | "Index out the number of cases.")((void)0); |
| 3287 | SI->setOperand(2 + Index*2, reinterpret_cast<Value*>(V)); |
| 3288 | } |
| 3289 | |
| 3290 | /// Sets the new successor for current case. |
| 3291 | void setSuccessor(BasicBlock *S) { |
| 3292 | SI->setSuccessor(getSuccessorIndex(), S); |
| 3293 | } |
| 3294 | }; |
| 3295 | |
| 3296 | template <typename CaseHandleT> |
| 3297 | class CaseIteratorImpl |
| 3298 | : public iterator_facade_base<CaseIteratorImpl<CaseHandleT>, |
| 3299 | std::random_access_iterator_tag, |
| 3300 | CaseHandleT> { |
| 3301 | using SwitchInstT = typename CaseHandleT::SwitchInstType; |
| 3302 | |
| 3303 | CaseHandleT Case; |
| 3304 | |
| 3305 | public: |
| 3306 | /// Default constructed iterator is in an invalid state until assigned to |
| 3307 | /// a case for a particular switch. |
| 3308 | CaseIteratorImpl() = default; |
| 3309 | |
| 3310 | /// Initializes case iterator for given SwitchInst and for given |
| 3311 | /// case number. |
| 3312 | CaseIteratorImpl(SwitchInstT *SI, unsigned CaseNum) : Case(SI, CaseNum) {} |
| 3313 | |
| 3314 | /// Initializes case iterator for given SwitchInst and for given |
| 3315 | /// successor index. |
| 3316 | static CaseIteratorImpl fromSuccessorIndex(SwitchInstT *SI, |
| 3317 | unsigned SuccessorIndex) { |
| 3318 | assert(SuccessorIndex < SI->getNumSuccessors() &&((void)0) |
| 3319 | "Successor index # out of range!")((void)0); |
| 3320 | return SuccessorIndex != 0 ? CaseIteratorImpl(SI, SuccessorIndex - 1) |
| 3321 | : CaseIteratorImpl(SI, DefaultPseudoIndex); |
| 3322 | } |
| 3323 | |
| 3324 | /// Support converting to the const variant. This will be a no-op for const |
| 3325 | /// variant. |
| 3326 | operator CaseIteratorImpl<ConstCaseHandle>() const { |
| 3327 | return CaseIteratorImpl<ConstCaseHandle>(Case.SI, Case.Index); |
| 3328 | } |
| 3329 | |
| 3330 | CaseIteratorImpl &operator+=(ptrdiff_t N) { |
| 3331 | // Check index correctness after addition. |
| 3332 | // Note: Index == getNumCases() means end(). |
| 3333 | assert(Case.Index + N >= 0 &&((void)0) |
| 3334 | (unsigned)(Case.Index + N) <= Case.SI->getNumCases() &&((void)0) |
| 3335 | "Case.Index out the number of cases.")((void)0); |
| 3336 | Case.Index += N; |
| 3337 | return *this; |
| 3338 | } |
| 3339 | CaseIteratorImpl &operator-=(ptrdiff_t N) { |
| 3340 | // Check index correctness after subtraction. |
| 3341 | // Note: Case.Index == getNumCases() means end(). |
| 3342 | assert(Case.Index - N >= 0 &&((void)0) |
| 3343 | (unsigned)(Case.Index - N) <= Case.SI->getNumCases() &&((void)0) |
| 3344 | "Case.Index out the number of cases.")((void)0); |
| 3345 | Case.Index -= N; |
| 3346 | return *this; |
| 3347 | } |
| 3348 | ptrdiff_t operator-(const CaseIteratorImpl &RHS) const { |
| 3349 | assert(Case.SI == RHS.Case.SI && "Incompatible operators.")((void)0); |
| 3350 | return Case.Index - RHS.Case.Index; |
| 3351 | } |
| 3352 | bool operator==(const CaseIteratorImpl &RHS) const { |
| 3353 | return Case == RHS.Case; |
| 3354 | } |
| 3355 | bool operator<(const CaseIteratorImpl &RHS) const { |
| 3356 | assert(Case.SI == RHS.Case.SI && "Incompatible operators.")((void)0); |
| 3357 | return Case.Index < RHS.Case.Index; |
| 3358 | } |
| 3359 | CaseHandleT &operator*() { return Case; } |
| 3360 | const CaseHandleT &operator*() const { return Case; } |
| 3361 | }; |
| 3362 | |
| 3363 | using CaseIt = CaseIteratorImpl<CaseHandle>; |
| 3364 | using ConstCaseIt = CaseIteratorImpl<ConstCaseHandle>; |
| 3365 | |
| 3366 | static SwitchInst *Create(Value *Value, BasicBlock *Default, |
| 3367 | unsigned NumCases, |
| 3368 | Instruction *InsertBefore = nullptr) { |
| 3369 | return new SwitchInst(Value, Default, NumCases, InsertBefore); |
| 3370 | } |
| 3371 | |
| 3372 | static SwitchInst *Create(Value *Value, BasicBlock *Default, |
| 3373 | unsigned NumCases, BasicBlock *InsertAtEnd) { |
| 3374 | return new SwitchInst(Value, Default, NumCases, InsertAtEnd); |
| 3375 | } |
| 3376 | |
| 3377 | /// Provide fast operand accessors |
| 3378 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 3379 | |
| 3380 | // Accessor Methods for Switch stmt |
| 3381 | Value *getCondition() const { return getOperand(0); } |
| 3382 | void setCondition(Value *V) { setOperand(0, V); } |
| 3383 | |
| 3384 | BasicBlock *getDefaultDest() const { |
| 3385 | return cast<BasicBlock>(getOperand(1)); |
| 3386 | } |
| 3387 | |
| 3388 | void setDefaultDest(BasicBlock *DefaultCase) { |
| 3389 | setOperand(1, reinterpret_cast<Value*>(DefaultCase)); |
| 3390 | } |
| 3391 | |
| 3392 | /// Return the number of 'cases' in this switch instruction, excluding the |
| 3393 | /// default case. |
| 3394 | unsigned getNumCases() const { |
| 3395 | return getNumOperands()/2 - 1; |
| 3396 | } |
| 3397 | |
| 3398 | /// Returns a read/write iterator that points to the first case in the |
| 3399 | /// SwitchInst. |
| 3400 | CaseIt case_begin() { |
| 3401 | return CaseIt(this, 0); |
| 3402 | } |
| 3403 | |
| 3404 | /// Returns a read-only iterator that points to the first case in the |
| 3405 | /// SwitchInst. |
| 3406 | ConstCaseIt case_begin() const { |
| 3407 | return ConstCaseIt(this, 0); |
| 3408 | } |
| 3409 | |
| 3410 | /// Returns a read/write iterator that points one past the last in the |
| 3411 | /// SwitchInst. |
| 3412 | CaseIt case_end() { |
| 3413 | return CaseIt(this, getNumCases()); |
| 3414 | } |
| 3415 | |
| 3416 | /// Returns a read-only iterator that points one past the last in the |
| 3417 | /// SwitchInst. |
| 3418 | ConstCaseIt case_end() const { |
| 3419 | return ConstCaseIt(this, getNumCases()); |
| 3420 | } |
| 3421 | |
| 3422 | /// Iteration adapter for range-for loops. |
| 3423 | iterator_range<CaseIt> cases() { |
| 3424 | return make_range(case_begin(), case_end()); |
| 3425 | } |
| 3426 | |
| 3427 | /// Constant iteration adapter for range-for loops. |
| 3428 | iterator_range<ConstCaseIt> cases() const { |
| 3429 | return make_range(case_begin(), case_end()); |
| 3430 | } |
| 3431 | |
| 3432 | /// Returns an iterator that points to the default case. |
| 3433 | /// Note: this iterator allows to resolve successor only. Attempt |
| 3434 | /// to resolve case value causes an assertion. |
| 3435 | /// Also note, that increment and decrement also causes an assertion and |
| 3436 | /// makes iterator invalid. |
| 3437 | CaseIt case_default() { |
| 3438 | return CaseIt(this, DefaultPseudoIndex); |
| 3439 | } |
| 3440 | ConstCaseIt case_default() const { |
| 3441 | return ConstCaseIt(this, DefaultPseudoIndex); |
| 3442 | } |
| 3443 | |
| 3444 | /// Search all of the case values for the specified constant. If it is |
| 3445 | /// explicitly handled, return the case iterator of it, otherwise return |
| 3446 | /// default case iterator to indicate that it is handled by the default |
| 3447 | /// handler. |
| 3448 | CaseIt findCaseValue(const ConstantInt *C) { |
| 3449 | CaseIt I = llvm::find_if( |
| 3450 | cases(), [C](CaseHandle &Case) { return Case.getCaseValue() == C; }); |
| 3451 | if (I != case_end()) |
| 3452 | return I; |
| 3453 | |
| 3454 | return case_default(); |
| 3455 | } |
| 3456 | ConstCaseIt findCaseValue(const ConstantInt *C) const { |
| 3457 | ConstCaseIt I = llvm::find_if(cases(), [C](ConstCaseHandle &Case) { |
| 3458 | return Case.getCaseValue() == C; |
| 3459 | }); |
| 3460 | if (I != case_end()) |
| 3461 | return I; |
| 3462 | |
| 3463 | return case_default(); |
| 3464 | } |
| 3465 | |
| 3466 | /// Finds the unique case value for a given successor. Returns null if the |
| 3467 | /// successor is not found, not unique, or is the default case. |
| 3468 | ConstantInt *findCaseDest(BasicBlock *BB) { |
| 3469 | if (BB == getDefaultDest()) |
| 3470 | return nullptr; |
| 3471 | |
| 3472 | ConstantInt *CI = nullptr; |
| 3473 | for (auto Case : cases()) { |
| 3474 | if (Case.getCaseSuccessor() != BB) |
| 3475 | continue; |
| 3476 | |
| 3477 | if (CI) |
| 3478 | return nullptr; // Multiple cases lead to BB. |
| 3479 | |
| 3480 | CI = Case.getCaseValue(); |
| 3481 | } |
| 3482 | |
| 3483 | return CI; |
| 3484 | } |
| 3485 | |
| 3486 | /// Add an entry to the switch instruction. |
| 3487 | /// Note: |
| 3488 | /// This action invalidates case_end(). Old case_end() iterator will |
| 3489 | /// point to the added case. |
| 3490 | void addCase(ConstantInt *OnVal, BasicBlock *Dest); |
| 3491 | |
| 3492 | /// This method removes the specified case and its successor from the switch |
| 3493 | /// instruction. Note that this operation may reorder the remaining cases at |
| 3494 | /// index idx and above. |
| 3495 | /// Note: |
| 3496 | /// This action invalidates iterators for all cases following the one removed, |
| 3497 | /// including the case_end() iterator. It returns an iterator for the next |
| 3498 | /// case. |
| 3499 | CaseIt removeCase(CaseIt I); |
| 3500 | |
| 3501 | unsigned getNumSuccessors() const { return getNumOperands()/2; } |
| 3502 | BasicBlock *getSuccessor(unsigned idx) const { |
| 3503 | assert(idx < getNumSuccessors() &&"Successor idx out of range for switch!")((void)0); |
| 3504 | return cast<BasicBlock>(getOperand(idx*2+1)); |
| 3505 | } |
| 3506 | void setSuccessor(unsigned idx, BasicBlock *NewSucc) { |
| 3507 | assert(idx < getNumSuccessors() && "Successor # out of range for switch!")((void)0); |
| 3508 | setOperand(idx * 2 + 1, NewSucc); |
| 3509 | } |
| 3510 | |
| 3511 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 3512 | static bool classof(const Instruction *I) { |
| 3513 | return I->getOpcode() == Instruction::Switch; |
| 3514 | } |
| 3515 | static bool classof(const Value *V) { |
| 3516 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 3517 | } |
| 3518 | }; |
| 3519 | |
| 3520 | /// A wrapper class to simplify modification of SwitchInst cases along with |
| 3521 | /// their prof branch_weights metadata. |
| 3522 | class SwitchInstProfUpdateWrapper { |
| 3523 | SwitchInst &SI; |
| 3524 | Optional<SmallVector<uint32_t, 8> > Weights = None; |
| 3525 | bool Changed = false; |
| 3526 | |
| 3527 | protected: |
| 3528 | static MDNode *getProfBranchWeightsMD(const SwitchInst &SI); |
| 3529 | |
| 3530 | MDNode *buildProfBranchWeightsMD(); |
| 3531 | |
| 3532 | void init(); |
| 3533 | |
| 3534 | public: |
| 3535 | using CaseWeightOpt = Optional<uint32_t>; |
| 3536 | SwitchInst *operator->() { return &SI; } |
| 3537 | SwitchInst &operator*() { return SI; } |
| 3538 | operator SwitchInst *() { return &SI; } |
| 3539 | |
| 3540 | SwitchInstProfUpdateWrapper(SwitchInst &SI) : SI(SI) { init(); } |
| 3541 | |
| 3542 | ~SwitchInstProfUpdateWrapper() { |
| 3543 | if (Changed) |
| 3544 | SI.setMetadata(LLVMContext::MD_prof, buildProfBranchWeightsMD()); |
| 3545 | } |
| 3546 | |
| 3547 | /// Delegate the call to the underlying SwitchInst::removeCase() and remove |
| 3548 | /// correspondent branch weight. |
| 3549 | SwitchInst::CaseIt removeCase(SwitchInst::CaseIt I); |
| 3550 | |
| 3551 | /// Delegate the call to the underlying SwitchInst::addCase() and set the |
| 3552 | /// specified branch weight for the added case. |
| 3553 | void addCase(ConstantInt *OnVal, BasicBlock *Dest, CaseWeightOpt W); |
| 3554 | |
| 3555 | /// Delegate the call to the underlying SwitchInst::eraseFromParent() and mark |
| 3556 | /// this object to not touch the underlying SwitchInst in destructor. |
| 3557 | SymbolTableList<Instruction>::iterator eraseFromParent(); |
| 3558 | |
| 3559 | void setSuccessorWeight(unsigned idx, CaseWeightOpt W); |
| 3560 | CaseWeightOpt getSuccessorWeight(unsigned idx); |
| 3561 | |
| 3562 | static CaseWeightOpt getSuccessorWeight(const SwitchInst &SI, unsigned idx); |
| 3563 | }; |
| 3564 | |
| 3565 | template <> |
| 3566 | struct OperandTraits<SwitchInst> : public HungoffOperandTraits<2> { |
| 3567 | }; |
| 3568 | |
| 3569 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(SwitchInst, Value)SwitchInst::op_iterator SwitchInst::op_begin() { return OperandTraits <SwitchInst>::op_begin(this); } SwitchInst::const_op_iterator SwitchInst::op_begin() const { return OperandTraits<SwitchInst >::op_begin(const_cast<SwitchInst*>(this)); } SwitchInst ::op_iterator SwitchInst::op_end() { return OperandTraits< SwitchInst>::op_end(this); } SwitchInst::const_op_iterator SwitchInst::op_end() const { return OperandTraits<SwitchInst >::op_end(const_cast<SwitchInst*>(this)); } Value *SwitchInst ::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null <Value>( OperandTraits<SwitchInst>::op_begin(const_cast <SwitchInst*>(this))[i_nocapture].get()); } void SwitchInst ::setOperand(unsigned i_nocapture, Value *Val_nocapture) { (( void)0); OperandTraits<SwitchInst>::op_begin(this)[i_nocapture ] = Val_nocapture; } unsigned SwitchInst::getNumOperands() const { return OperandTraits<SwitchInst>::operands(this); } template <int Idx_nocapture> Use &SwitchInst::Op() { return this->OpFrom<Idx_nocapture>(this); } template <int Idx_nocapture> const Use &SwitchInst::Op() const { return this->OpFrom<Idx_nocapture>(this); } |
| 3570 | |
| 3571 | //===----------------------------------------------------------------------===// |
| 3572 | // IndirectBrInst Class |
| 3573 | //===----------------------------------------------------------------------===// |
| 3574 | |
| 3575 | //===--------------------------------------------------------------------------- |
| 3576 | /// Indirect Branch Instruction. |
| 3577 | /// |
| 3578 | class IndirectBrInst : public Instruction { |
| 3579 | unsigned ReservedSpace; |
| 3580 | |
| 3581 | // Operand[0] = Address to jump to |
| 3582 | // Operand[n+1] = n-th destination |
| 3583 | IndirectBrInst(const IndirectBrInst &IBI); |
| 3584 | |
| 3585 | /// Create a new indirectbr instruction, specifying an |
| 3586 | /// Address to jump to. The number of expected destinations can be specified |
| 3587 | /// here to make memory allocation more efficient. This constructor can also |
| 3588 | /// autoinsert before another instruction. |
| 3589 | IndirectBrInst(Value *Address, unsigned NumDests, Instruction *InsertBefore); |
| 3590 | |
| 3591 | /// Create a new indirectbr instruction, specifying an |
| 3592 | /// Address to jump to. The number of expected destinations can be specified |
| 3593 | /// here to make memory allocation more efficient. This constructor also |
| 3594 | /// autoinserts at the end of the specified BasicBlock. |
| 3595 | IndirectBrInst(Value *Address, unsigned NumDests, BasicBlock *InsertAtEnd); |
| 3596 | |
| 3597 | // allocate space for exactly zero operands |
| 3598 | void *operator new(size_t S) { return User::operator new(S); } |
| 3599 | |
| 3600 | void init(Value *Address, unsigned NumDests); |
| 3601 | void growOperands(); |
| 3602 | |
| 3603 | protected: |
| 3604 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 3605 | friend class Instruction; |
| 3606 | |
| 3607 | IndirectBrInst *cloneImpl() const; |
| 3608 | |
| 3609 | public: |
| 3610 | void operator delete(void *Ptr) { User::operator delete(Ptr); } |
| 3611 | |
| 3612 | /// Iterator type that casts an operand to a basic block. |
| 3613 | /// |
| 3614 | /// This only makes sense because the successors are stored as adjacent |
| 3615 | /// operands for indirectbr instructions. |
| 3616 | struct succ_op_iterator |
| 3617 | : iterator_adaptor_base<succ_op_iterator, value_op_iterator, |
| 3618 | std::random_access_iterator_tag, BasicBlock *, |
| 3619 | ptrdiff_t, BasicBlock *, BasicBlock *> { |
| 3620 | explicit succ_op_iterator(value_op_iterator I) : iterator_adaptor_base(I) {} |
| 3621 | |
| 3622 | BasicBlock *operator*() const { return cast<BasicBlock>(*I); } |
| 3623 | BasicBlock *operator->() const { return operator*(); } |
| 3624 | }; |
| 3625 | |
| 3626 | /// The const version of `succ_op_iterator`. |
| 3627 | struct const_succ_op_iterator |
| 3628 | : iterator_adaptor_base<const_succ_op_iterator, const_value_op_iterator, |
| 3629 | std::random_access_iterator_tag, |
| 3630 | const BasicBlock *, ptrdiff_t, const BasicBlock *, |
| 3631 | const BasicBlock *> { |
| 3632 | explicit const_succ_op_iterator(const_value_op_iterator I) |
| 3633 | : iterator_adaptor_base(I) {} |
| 3634 | |
| 3635 | const BasicBlock *operator*() const { return cast<BasicBlock>(*I); } |
| 3636 | const BasicBlock *operator->() const { return operator*(); } |
| 3637 | }; |
| 3638 | |
| 3639 | static IndirectBrInst *Create(Value *Address, unsigned NumDests, |
| 3640 | Instruction *InsertBefore = nullptr) { |
| 3641 | return new IndirectBrInst(Address, NumDests, InsertBefore); |
| 3642 | } |
| 3643 | |
| 3644 | static IndirectBrInst *Create(Value *Address, unsigned NumDests, |
| 3645 | BasicBlock *InsertAtEnd) { |
| 3646 | return new IndirectBrInst(Address, NumDests, InsertAtEnd); |
| 3647 | } |
| 3648 | |
| 3649 | /// Provide fast operand accessors. |
| 3650 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 3651 | |
| 3652 | // Accessor Methods for IndirectBrInst instruction. |
| 3653 | Value *getAddress() { return getOperand(0); } |
| 3654 | const Value *getAddress() const { return getOperand(0); } |
| 3655 | void setAddress(Value *V) { setOperand(0, V); } |
| 3656 | |
| 3657 | /// return the number of possible destinations in this |
| 3658 | /// indirectbr instruction. |
| 3659 | unsigned getNumDestinations() const { return getNumOperands()-1; } |
| 3660 | |
| 3661 | /// Return the specified destination. |
| 3662 | BasicBlock *getDestination(unsigned i) { return getSuccessor(i); } |
| 3663 | const BasicBlock *getDestination(unsigned i) const { return getSuccessor(i); } |
| 3664 | |
| 3665 | /// Add a destination. |
| 3666 | /// |
| 3667 | void addDestination(BasicBlock *Dest); |
| 3668 | |
| 3669 | /// This method removes the specified successor from the |
| 3670 | /// indirectbr instruction. |
| 3671 | void removeDestination(unsigned i); |
| 3672 | |
| 3673 | unsigned getNumSuccessors() const { return getNumOperands()-1; } |
| 3674 | BasicBlock *getSuccessor(unsigned i) const { |
| 3675 | return cast<BasicBlock>(getOperand(i+1)); |
| 3676 | } |
| 3677 | void setSuccessor(unsigned i, BasicBlock *NewSucc) { |
| 3678 | setOperand(i + 1, NewSucc); |
| 3679 | } |
| 3680 | |
| 3681 | iterator_range<succ_op_iterator> successors() { |
| 3682 | return make_range(succ_op_iterator(std::next(value_op_begin())), |
| 3683 | succ_op_iterator(value_op_end())); |
| 3684 | } |
| 3685 | |
| 3686 | iterator_range<const_succ_op_iterator> successors() const { |
| 3687 | return make_range(const_succ_op_iterator(std::next(value_op_begin())), |
| 3688 | const_succ_op_iterator(value_op_end())); |
| 3689 | } |
| 3690 | |
| 3691 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 3692 | static bool classof(const Instruction *I) { |
| 3693 | return I->getOpcode() == Instruction::IndirectBr; |
| 3694 | } |
| 3695 | static bool classof(const Value *V) { |
| 3696 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 3697 | } |
| 3698 | }; |
| 3699 | |
| 3700 | template <> |
| 3701 | struct OperandTraits<IndirectBrInst> : public HungoffOperandTraits<1> { |
| 3702 | }; |
| 3703 | |
| 3704 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(IndirectBrInst, Value)IndirectBrInst::op_iterator IndirectBrInst::op_begin() { return OperandTraits<IndirectBrInst>::op_begin(this); } IndirectBrInst ::const_op_iterator IndirectBrInst::op_begin() const { return OperandTraits<IndirectBrInst>::op_begin(const_cast< IndirectBrInst*>(this)); } IndirectBrInst::op_iterator IndirectBrInst ::op_end() { return OperandTraits<IndirectBrInst>::op_end (this); } IndirectBrInst::const_op_iterator IndirectBrInst::op_end () const { return OperandTraits<IndirectBrInst>::op_end (const_cast<IndirectBrInst*>(this)); } Value *IndirectBrInst ::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null <Value>( OperandTraits<IndirectBrInst>::op_begin( const_cast<IndirectBrInst*>(this))[i_nocapture].get()); } void IndirectBrInst::setOperand(unsigned i_nocapture, Value *Val_nocapture) { ((void)0); OperandTraits<IndirectBrInst >::op_begin(this)[i_nocapture] = Val_nocapture; } unsigned IndirectBrInst::getNumOperands() const { return OperandTraits <IndirectBrInst>::operands(this); } template <int Idx_nocapture > Use &IndirectBrInst::Op() { return this->OpFrom< Idx_nocapture>(this); } template <int Idx_nocapture> const Use &IndirectBrInst::Op() const { return this-> OpFrom<Idx_nocapture>(this); } |
| 3705 | |
| 3706 | //===----------------------------------------------------------------------===// |
| 3707 | // InvokeInst Class |
| 3708 | //===----------------------------------------------------------------------===// |
| 3709 | |
| 3710 | /// Invoke instruction. The SubclassData field is used to hold the |
| 3711 | /// calling convention of the call. |
| 3712 | /// |
| 3713 | class InvokeInst : public CallBase { |
| 3714 | /// The number of operands for this call beyond the called function, |
| 3715 | /// arguments, and operand bundles. |
| 3716 | static constexpr int NumExtraOperands = 2; |
| 3717 | |
| 3718 | /// The index from the end of the operand array to the normal destination. |
| 3719 | static constexpr int NormalDestOpEndIdx = -3; |
| 3720 | |
| 3721 | /// The index from the end of the operand array to the unwind destination. |
| 3722 | static constexpr int UnwindDestOpEndIdx = -2; |
| 3723 | |
| 3724 | InvokeInst(const InvokeInst &BI); |
| 3725 | |
| 3726 | /// Construct an InvokeInst given a range of arguments. |
| 3727 | /// |
| 3728 | /// Construct an InvokeInst from a range of arguments |
| 3729 | inline InvokeInst(FunctionType *Ty, Value *Func, BasicBlock *IfNormal, |
| 3730 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3731 | ArrayRef<OperandBundleDef> Bundles, int NumOperands, |
| 3732 | const Twine &NameStr, Instruction *InsertBefore); |
| 3733 | |
| 3734 | inline InvokeInst(FunctionType *Ty, Value *Func, BasicBlock *IfNormal, |
| 3735 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3736 | ArrayRef<OperandBundleDef> Bundles, int NumOperands, |
| 3737 | const Twine &NameStr, BasicBlock *InsertAtEnd); |
| 3738 | |
| 3739 | void init(FunctionType *Ty, Value *Func, BasicBlock *IfNormal, |
| 3740 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3741 | ArrayRef<OperandBundleDef> Bundles, const Twine &NameStr); |
| 3742 | |
| 3743 | /// Compute the number of operands to allocate. |
| 3744 | static int ComputeNumOperands(int NumArgs, int NumBundleInputs = 0) { |
| 3745 | // We need one operand for the called function, plus our extra operands and |
| 3746 | // the input operand counts provided. |
| 3747 | return 1 + NumExtraOperands + NumArgs + NumBundleInputs; |
| 3748 | } |
| 3749 | |
| 3750 | protected: |
| 3751 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 3752 | friend class Instruction; |
| 3753 | |
| 3754 | InvokeInst *cloneImpl() const; |
| 3755 | |
| 3756 | public: |
| 3757 | static InvokeInst *Create(FunctionType *Ty, Value *Func, BasicBlock *IfNormal, |
| 3758 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3759 | const Twine &NameStr, |
| 3760 | Instruction *InsertBefore = nullptr) { |
| 3761 | int NumOperands = ComputeNumOperands(Args.size()); |
| 3762 | return new (NumOperands) |
| 3763 | InvokeInst(Ty, Func, IfNormal, IfException, Args, None, NumOperands, |
| 3764 | NameStr, InsertBefore); |
| 3765 | } |
| 3766 | |
| 3767 | static InvokeInst *Create(FunctionType *Ty, Value *Func, BasicBlock *IfNormal, |
| 3768 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3769 | ArrayRef<OperandBundleDef> Bundles = None, |
| 3770 | const Twine &NameStr = "", |
| 3771 | Instruction *InsertBefore = nullptr) { |
| 3772 | int NumOperands = |
| 3773 | ComputeNumOperands(Args.size(), CountBundleInputs(Bundles)); |
| 3774 | unsigned DescriptorBytes = Bundles.size() * sizeof(BundleOpInfo); |
| 3775 | |
| 3776 | return new (NumOperands, DescriptorBytes) |
| 3777 | InvokeInst(Ty, Func, IfNormal, IfException, Args, Bundles, NumOperands, |
| 3778 | NameStr, InsertBefore); |
| 3779 | } |
| 3780 | |
| 3781 | static InvokeInst *Create(FunctionType *Ty, Value *Func, BasicBlock *IfNormal, |
| 3782 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3783 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 3784 | int NumOperands = ComputeNumOperands(Args.size()); |
| 3785 | return new (NumOperands) |
| 3786 | InvokeInst(Ty, Func, IfNormal, IfException, Args, None, NumOperands, |
| 3787 | NameStr, InsertAtEnd); |
| 3788 | } |
| 3789 | |
| 3790 | static InvokeInst *Create(FunctionType *Ty, Value *Func, BasicBlock *IfNormal, |
| 3791 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3792 | ArrayRef<OperandBundleDef> Bundles, |
| 3793 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 3794 | int NumOperands = |
| 3795 | ComputeNumOperands(Args.size(), CountBundleInputs(Bundles)); |
| 3796 | unsigned DescriptorBytes = Bundles.size() * sizeof(BundleOpInfo); |
| 3797 | |
| 3798 | return new (NumOperands, DescriptorBytes) |
| 3799 | InvokeInst(Ty, Func, IfNormal, IfException, Args, Bundles, NumOperands, |
| 3800 | NameStr, InsertAtEnd); |
| 3801 | } |
| 3802 | |
| 3803 | static InvokeInst *Create(FunctionCallee Func, BasicBlock *IfNormal, |
| 3804 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3805 | const Twine &NameStr, |
| 3806 | Instruction *InsertBefore = nullptr) { |
| 3807 | return Create(Func.getFunctionType(), Func.getCallee(), IfNormal, |
| 3808 | IfException, Args, None, NameStr, InsertBefore); |
| 3809 | } |
| 3810 | |
| 3811 | static InvokeInst *Create(FunctionCallee Func, BasicBlock *IfNormal, |
| 3812 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3813 | ArrayRef<OperandBundleDef> Bundles = None, |
| 3814 | const Twine &NameStr = "", |
| 3815 | Instruction *InsertBefore = nullptr) { |
| 3816 | return Create(Func.getFunctionType(), Func.getCallee(), IfNormal, |
| 3817 | IfException, Args, Bundles, NameStr, InsertBefore); |
| 3818 | } |
| 3819 | |
| 3820 | static InvokeInst *Create(FunctionCallee Func, BasicBlock *IfNormal, |
| 3821 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3822 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 3823 | return Create(Func.getFunctionType(), Func.getCallee(), IfNormal, |
| 3824 | IfException, Args, NameStr, InsertAtEnd); |
| 3825 | } |
| 3826 | |
| 3827 | static InvokeInst *Create(FunctionCallee Func, BasicBlock *IfNormal, |
| 3828 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3829 | ArrayRef<OperandBundleDef> Bundles, |
| 3830 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 3831 | return Create(Func.getFunctionType(), Func.getCallee(), IfNormal, |
| 3832 | IfException, Args, Bundles, NameStr, InsertAtEnd); |
| 3833 | } |
| 3834 | |
| 3835 | /// Create a clone of \p II with a different set of operand bundles and |
| 3836 | /// insert it before \p InsertPt. |
| 3837 | /// |
| 3838 | /// The returned invoke instruction is identical to \p II in every way except |
| 3839 | /// that the operand bundles for the new instruction are set to the operand |
| 3840 | /// bundles in \p Bundles. |
| 3841 | static InvokeInst *Create(InvokeInst *II, ArrayRef<OperandBundleDef> Bundles, |
| 3842 | Instruction *InsertPt = nullptr); |
| 3843 | |
| 3844 | // get*Dest - Return the destination basic blocks... |
| 3845 | BasicBlock *getNormalDest() const { |
| 3846 | return cast<BasicBlock>(Op<NormalDestOpEndIdx>()); |
| 3847 | } |
| 3848 | BasicBlock *getUnwindDest() const { |
| 3849 | return cast<BasicBlock>(Op<UnwindDestOpEndIdx>()); |
| 3850 | } |
| 3851 | void setNormalDest(BasicBlock *B) { |
| 3852 | Op<NormalDestOpEndIdx>() = reinterpret_cast<Value *>(B); |
| 3853 | } |
| 3854 | void setUnwindDest(BasicBlock *B) { |
| 3855 | Op<UnwindDestOpEndIdx>() = reinterpret_cast<Value *>(B); |
| 3856 | } |
| 3857 | |
| 3858 | /// Get the landingpad instruction from the landing pad |
| 3859 | /// block (the unwind destination). |
| 3860 | LandingPadInst *getLandingPadInst() const; |
| 3861 | |
| 3862 | BasicBlock *getSuccessor(unsigned i) const { |
| 3863 | assert(i < 2 && "Successor # out of range for invoke!")((void)0); |
| 3864 | return i == 0 ? getNormalDest() : getUnwindDest(); |
| 3865 | } |
| 3866 | |
| 3867 | void setSuccessor(unsigned i, BasicBlock *NewSucc) { |
| 3868 | assert(i < 2 && "Successor # out of range for invoke!")((void)0); |
| 3869 | if (i == 0) |
| 3870 | setNormalDest(NewSucc); |
| 3871 | else |
| 3872 | setUnwindDest(NewSucc); |
| 3873 | } |
| 3874 | |
| 3875 | unsigned getNumSuccessors() const { return 2; } |
| 3876 | |
| 3877 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 3878 | static bool classof(const Instruction *I) { |
| 3879 | return (I->getOpcode() == Instruction::Invoke); |
| 3880 | } |
| 3881 | static bool classof(const Value *V) { |
| 3882 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 3883 | } |
| 3884 | |
| 3885 | private: |
| 3886 | // Shadow Instruction::setInstructionSubclassData with a private forwarding |
| 3887 | // method so that subclasses cannot accidentally use it. |
| 3888 | template <typename Bitfield> |
| 3889 | void setSubclassData(typename Bitfield::Type Value) { |
| 3890 | Instruction::setSubclassData<Bitfield>(Value); |
| 3891 | } |
| 3892 | }; |
| 3893 | |
| 3894 | InvokeInst::InvokeInst(FunctionType *Ty, Value *Func, BasicBlock *IfNormal, |
| 3895 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3896 | ArrayRef<OperandBundleDef> Bundles, int NumOperands, |
| 3897 | const Twine &NameStr, Instruction *InsertBefore) |
| 3898 | : CallBase(Ty->getReturnType(), Instruction::Invoke, |
| 3899 | OperandTraits<CallBase>::op_end(this) - NumOperands, NumOperands, |
| 3900 | InsertBefore) { |
| 3901 | init(Ty, Func, IfNormal, IfException, Args, Bundles, NameStr); |
| 3902 | } |
| 3903 | |
| 3904 | InvokeInst::InvokeInst(FunctionType *Ty, Value *Func, BasicBlock *IfNormal, |
| 3905 | BasicBlock *IfException, ArrayRef<Value *> Args, |
| 3906 | ArrayRef<OperandBundleDef> Bundles, int NumOperands, |
| 3907 | const Twine &NameStr, BasicBlock *InsertAtEnd) |
| 3908 | : CallBase(Ty->getReturnType(), Instruction::Invoke, |
| 3909 | OperandTraits<CallBase>::op_end(this) - NumOperands, NumOperands, |
| 3910 | InsertAtEnd) { |
| 3911 | init(Ty, Func, IfNormal, IfException, Args, Bundles, NameStr); |
| 3912 | } |
| 3913 | |
| 3914 | //===----------------------------------------------------------------------===// |
| 3915 | // CallBrInst Class |
| 3916 | //===----------------------------------------------------------------------===// |
| 3917 | |
| 3918 | /// CallBr instruction, tracking function calls that may not return control but |
| 3919 | /// instead transfer it to a third location. The SubclassData field is used to |
| 3920 | /// hold the calling convention of the call. |
| 3921 | /// |
| 3922 | class CallBrInst : public CallBase { |
| 3923 | |
| 3924 | unsigned NumIndirectDests; |
| 3925 | |
| 3926 | CallBrInst(const CallBrInst &BI); |
| 3927 | |
| 3928 | /// Construct a CallBrInst given a range of arguments. |
| 3929 | /// |
| 3930 | /// Construct a CallBrInst from a range of arguments |
| 3931 | inline CallBrInst(FunctionType *Ty, Value *Func, BasicBlock *DefaultDest, |
| 3932 | ArrayRef<BasicBlock *> IndirectDests, |
| 3933 | ArrayRef<Value *> Args, |
| 3934 | ArrayRef<OperandBundleDef> Bundles, int NumOperands, |
| 3935 | const Twine &NameStr, Instruction *InsertBefore); |
| 3936 | |
| 3937 | inline CallBrInst(FunctionType *Ty, Value *Func, BasicBlock *DefaultDest, |
| 3938 | ArrayRef<BasicBlock *> IndirectDests, |
| 3939 | ArrayRef<Value *> Args, |
| 3940 | ArrayRef<OperandBundleDef> Bundles, int NumOperands, |
| 3941 | const Twine &NameStr, BasicBlock *InsertAtEnd); |
| 3942 | |
| 3943 | void init(FunctionType *FTy, Value *Func, BasicBlock *DefaultDest, |
| 3944 | ArrayRef<BasicBlock *> IndirectDests, ArrayRef<Value *> Args, |
| 3945 | ArrayRef<OperandBundleDef> Bundles, const Twine &NameStr); |
| 3946 | |
| 3947 | /// Should the Indirect Destinations change, scan + update the Arg list. |
| 3948 | void updateArgBlockAddresses(unsigned i, BasicBlock *B); |
| 3949 | |
| 3950 | /// Compute the number of operands to allocate. |
| 3951 | static int ComputeNumOperands(int NumArgs, int NumIndirectDests, |
| 3952 | int NumBundleInputs = 0) { |
| 3953 | // We need one operand for the called function, plus our extra operands and |
| 3954 | // the input operand counts provided. |
| 3955 | return 2 + NumIndirectDests + NumArgs + NumBundleInputs; |
| 3956 | } |
| 3957 | |
| 3958 | protected: |
| 3959 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 3960 | friend class Instruction; |
| 3961 | |
| 3962 | CallBrInst *cloneImpl() const; |
| 3963 | |
| 3964 | public: |
| 3965 | static CallBrInst *Create(FunctionType *Ty, Value *Func, |
| 3966 | BasicBlock *DefaultDest, |
| 3967 | ArrayRef<BasicBlock *> IndirectDests, |
| 3968 | ArrayRef<Value *> Args, const Twine &NameStr, |
| 3969 | Instruction *InsertBefore = nullptr) { |
| 3970 | int NumOperands = ComputeNumOperands(Args.size(), IndirectDests.size()); |
| 3971 | return new (NumOperands) |
| 3972 | CallBrInst(Ty, Func, DefaultDest, IndirectDests, Args, None, |
| 3973 | NumOperands, NameStr, InsertBefore); |
| 3974 | } |
| 3975 | |
| 3976 | static CallBrInst *Create(FunctionType *Ty, Value *Func, |
| 3977 | BasicBlock *DefaultDest, |
| 3978 | ArrayRef<BasicBlock *> IndirectDests, |
| 3979 | ArrayRef<Value *> Args, |
| 3980 | ArrayRef<OperandBundleDef> Bundles = None, |
| 3981 | const Twine &NameStr = "", |
| 3982 | Instruction *InsertBefore = nullptr) { |
| 3983 | int NumOperands = ComputeNumOperands(Args.size(), IndirectDests.size(), |
| 3984 | CountBundleInputs(Bundles)); |
| 3985 | unsigned DescriptorBytes = Bundles.size() * sizeof(BundleOpInfo); |
| 3986 | |
| 3987 | return new (NumOperands, DescriptorBytes) |
| 3988 | CallBrInst(Ty, Func, DefaultDest, IndirectDests, Args, Bundles, |
| 3989 | NumOperands, NameStr, InsertBefore); |
| 3990 | } |
| 3991 | |
| 3992 | static CallBrInst *Create(FunctionType *Ty, Value *Func, |
| 3993 | BasicBlock *DefaultDest, |
| 3994 | ArrayRef<BasicBlock *> IndirectDests, |
| 3995 | ArrayRef<Value *> Args, const Twine &NameStr, |
| 3996 | BasicBlock *InsertAtEnd) { |
| 3997 | int NumOperands = ComputeNumOperands(Args.size(), IndirectDests.size()); |
| 3998 | return new (NumOperands) |
| 3999 | CallBrInst(Ty, Func, DefaultDest, IndirectDests, Args, None, |
| 4000 | NumOperands, NameStr, InsertAtEnd); |
| 4001 | } |
| 4002 | |
| 4003 | static CallBrInst *Create(FunctionType *Ty, Value *Func, |
| 4004 | BasicBlock *DefaultDest, |
| 4005 | ArrayRef<BasicBlock *> IndirectDests, |
| 4006 | ArrayRef<Value *> Args, |
| 4007 | ArrayRef<OperandBundleDef> Bundles, |
| 4008 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 4009 | int NumOperands = ComputeNumOperands(Args.size(), IndirectDests.size(), |
| 4010 | CountBundleInputs(Bundles)); |
| 4011 | unsigned DescriptorBytes = Bundles.size() * sizeof(BundleOpInfo); |
| 4012 | |
| 4013 | return new (NumOperands, DescriptorBytes) |
| 4014 | CallBrInst(Ty, Func, DefaultDest, IndirectDests, Args, Bundles, |
| 4015 | NumOperands, NameStr, InsertAtEnd); |
| 4016 | } |
| 4017 | |
| 4018 | static CallBrInst *Create(FunctionCallee Func, BasicBlock *DefaultDest, |
| 4019 | ArrayRef<BasicBlock *> IndirectDests, |
| 4020 | ArrayRef<Value *> Args, const Twine &NameStr, |
| 4021 | Instruction *InsertBefore = nullptr) { |
| 4022 | return Create(Func.getFunctionType(), Func.getCallee(), DefaultDest, |
| 4023 | IndirectDests, Args, NameStr, InsertBefore); |
| 4024 | } |
| 4025 | |
| 4026 | static CallBrInst *Create(FunctionCallee Func, BasicBlock *DefaultDest, |
| 4027 | ArrayRef<BasicBlock *> IndirectDests, |
| 4028 | ArrayRef<Value *> Args, |
| 4029 | ArrayRef<OperandBundleDef> Bundles = None, |
| 4030 | const Twine &NameStr = "", |
| 4031 | Instruction *InsertBefore = nullptr) { |
| 4032 | return Create(Func.getFunctionType(), Func.getCallee(), DefaultDest, |
| 4033 | IndirectDests, Args, Bundles, NameStr, InsertBefore); |
| 4034 | } |
| 4035 | |
| 4036 | static CallBrInst *Create(FunctionCallee Func, BasicBlock *DefaultDest, |
| 4037 | ArrayRef<BasicBlock *> IndirectDests, |
| 4038 | ArrayRef<Value *> Args, const Twine &NameStr, |
| 4039 | BasicBlock *InsertAtEnd) { |
| 4040 | return Create(Func.getFunctionType(), Func.getCallee(), DefaultDest, |
| 4041 | IndirectDests, Args, NameStr, InsertAtEnd); |
| 4042 | } |
| 4043 | |
| 4044 | static CallBrInst *Create(FunctionCallee Func, |
| 4045 | BasicBlock *DefaultDest, |
| 4046 | ArrayRef<BasicBlock *> IndirectDests, |
| 4047 | ArrayRef<Value *> Args, |
| 4048 | ArrayRef<OperandBundleDef> Bundles, |
| 4049 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 4050 | return Create(Func.getFunctionType(), Func.getCallee(), DefaultDest, |
| 4051 | IndirectDests, Args, Bundles, NameStr, InsertAtEnd); |
| 4052 | } |
| 4053 | |
| 4054 | /// Create a clone of \p CBI with a different set of operand bundles and |
| 4055 | /// insert it before \p InsertPt. |
| 4056 | /// |
| 4057 | /// The returned callbr instruction is identical to \p CBI in every way |
| 4058 | /// except that the operand bundles for the new instruction are set to the |
| 4059 | /// operand bundles in \p Bundles. |
| 4060 | static CallBrInst *Create(CallBrInst *CBI, |
| 4061 | ArrayRef<OperandBundleDef> Bundles, |
| 4062 | Instruction *InsertPt = nullptr); |
| 4063 | |
| 4064 | /// Return the number of callbr indirect dest labels. |
| 4065 | /// |
| 4066 | unsigned getNumIndirectDests() const { return NumIndirectDests; } |
| 4067 | |
| 4068 | /// getIndirectDestLabel - Return the i-th indirect dest label. |
| 4069 | /// |
| 4070 | Value *getIndirectDestLabel(unsigned i) const { |
| 4071 | assert(i < getNumIndirectDests() && "Out of bounds!")((void)0); |
| 4072 | return getOperand(i + getNumArgOperands() + getNumTotalBundleOperands() + |
| 4073 | 1); |
| 4074 | } |
| 4075 | |
| 4076 | Value *getIndirectDestLabelUse(unsigned i) const { |
| 4077 | assert(i < getNumIndirectDests() && "Out of bounds!")((void)0); |
| 4078 | return getOperandUse(i + getNumArgOperands() + getNumTotalBundleOperands() + |
| 4079 | 1); |
| 4080 | } |
| 4081 | |
| 4082 | // Return the destination basic blocks... |
| 4083 | BasicBlock *getDefaultDest() const { |
| 4084 | return cast<BasicBlock>(*(&Op<-1>() - getNumIndirectDests() - 1)); |
| 4085 | } |
| 4086 | BasicBlock *getIndirectDest(unsigned i) const { |
| 4087 | return cast_or_null<BasicBlock>(*(&Op<-1>() - getNumIndirectDests() + i)); |
| 4088 | } |
| 4089 | SmallVector<BasicBlock *, 16> getIndirectDests() const { |
| 4090 | SmallVector<BasicBlock *, 16> IndirectDests; |
| 4091 | for (unsigned i = 0, e = getNumIndirectDests(); i < e; ++i) |
| 4092 | IndirectDests.push_back(getIndirectDest(i)); |
| 4093 | return IndirectDests; |
| 4094 | } |
| 4095 | void setDefaultDest(BasicBlock *B) { |
| 4096 | *(&Op<-1>() - getNumIndirectDests() - 1) = reinterpret_cast<Value *>(B); |
| 4097 | } |
| 4098 | void setIndirectDest(unsigned i, BasicBlock *B) { |
| 4099 | updateArgBlockAddresses(i, B); |
| 4100 | *(&Op<-1>() - getNumIndirectDests() + i) = reinterpret_cast<Value *>(B); |
| 4101 | } |
| 4102 | |
| 4103 | BasicBlock *getSuccessor(unsigned i) const { |
| 4104 | assert(i < getNumSuccessors() + 1 &&((void)0) |
| 4105 | "Successor # out of range for callbr!")((void)0); |
| 4106 | return i == 0 ? getDefaultDest() : getIndirectDest(i - 1); |
| 4107 | } |
| 4108 | |
| 4109 | void setSuccessor(unsigned i, BasicBlock *NewSucc) { |
| 4110 | assert(i < getNumIndirectDests() + 1 &&((void)0) |
| 4111 | "Successor # out of range for callbr!")((void)0); |
| 4112 | return i == 0 ? setDefaultDest(NewSucc) : setIndirectDest(i - 1, NewSucc); |
| 4113 | } |
| 4114 | |
| 4115 | unsigned getNumSuccessors() const { return getNumIndirectDests() + 1; } |
| 4116 | |
| 4117 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4118 | static bool classof(const Instruction *I) { |
| 4119 | return (I->getOpcode() == Instruction::CallBr); |
| 4120 | } |
| 4121 | static bool classof(const Value *V) { |
| 4122 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4123 | } |
| 4124 | |
| 4125 | private: |
| 4126 | // Shadow Instruction::setInstructionSubclassData with a private forwarding |
| 4127 | // method so that subclasses cannot accidentally use it. |
| 4128 | template <typename Bitfield> |
| 4129 | void setSubclassData(typename Bitfield::Type Value) { |
| 4130 | Instruction::setSubclassData<Bitfield>(Value); |
| 4131 | } |
| 4132 | }; |
| 4133 | |
| 4134 | CallBrInst::CallBrInst(FunctionType *Ty, Value *Func, BasicBlock *DefaultDest, |
| 4135 | ArrayRef<BasicBlock *> IndirectDests, |
| 4136 | ArrayRef<Value *> Args, |
| 4137 | ArrayRef<OperandBundleDef> Bundles, int NumOperands, |
| 4138 | const Twine &NameStr, Instruction *InsertBefore) |
| 4139 | : CallBase(Ty->getReturnType(), Instruction::CallBr, |
| 4140 | OperandTraits<CallBase>::op_end(this) - NumOperands, NumOperands, |
| 4141 | InsertBefore) { |
| 4142 | init(Ty, Func, DefaultDest, IndirectDests, Args, Bundles, NameStr); |
| 4143 | } |
| 4144 | |
| 4145 | CallBrInst::CallBrInst(FunctionType *Ty, Value *Func, BasicBlock *DefaultDest, |
| 4146 | ArrayRef<BasicBlock *> IndirectDests, |
| 4147 | ArrayRef<Value *> Args, |
| 4148 | ArrayRef<OperandBundleDef> Bundles, int NumOperands, |
| 4149 | const Twine &NameStr, BasicBlock *InsertAtEnd) |
| 4150 | : CallBase(Ty->getReturnType(), Instruction::CallBr, |
| 4151 | OperandTraits<CallBase>::op_end(this) - NumOperands, NumOperands, |
| 4152 | InsertAtEnd) { |
| 4153 | init(Ty, Func, DefaultDest, IndirectDests, Args, Bundles, NameStr); |
| 4154 | } |
| 4155 | |
| 4156 | //===----------------------------------------------------------------------===// |
| 4157 | // ResumeInst Class |
| 4158 | //===----------------------------------------------------------------------===// |
| 4159 | |
| 4160 | //===--------------------------------------------------------------------------- |
| 4161 | /// Resume the propagation of an exception. |
| 4162 | /// |
| 4163 | class ResumeInst : public Instruction { |
| 4164 | ResumeInst(const ResumeInst &RI); |
| 4165 | |
| 4166 | explicit ResumeInst(Value *Exn, Instruction *InsertBefore=nullptr); |
| 4167 | ResumeInst(Value *Exn, BasicBlock *InsertAtEnd); |
| 4168 | |
| 4169 | protected: |
| 4170 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4171 | friend class Instruction; |
| 4172 | |
| 4173 | ResumeInst *cloneImpl() const; |
| 4174 | |
| 4175 | public: |
| 4176 | static ResumeInst *Create(Value *Exn, Instruction *InsertBefore = nullptr) { |
| 4177 | return new(1) ResumeInst(Exn, InsertBefore); |
| 4178 | } |
| 4179 | |
| 4180 | static ResumeInst *Create(Value *Exn, BasicBlock *InsertAtEnd) { |
| 4181 | return new(1) ResumeInst(Exn, InsertAtEnd); |
| 4182 | } |
| 4183 | |
| 4184 | /// Provide fast operand accessors |
| 4185 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 4186 | |
| 4187 | /// Convenience accessor. |
| 4188 | Value *getValue() const { return Op<0>(); } |
| 4189 | |
| 4190 | unsigned getNumSuccessors() const { return 0; } |
| 4191 | |
| 4192 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4193 | static bool classof(const Instruction *I) { |
| 4194 | return I->getOpcode() == Instruction::Resume; |
| 4195 | } |
| 4196 | static bool classof(const Value *V) { |
| 4197 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4198 | } |
| 4199 | |
| 4200 | private: |
| 4201 | BasicBlock *getSuccessor(unsigned idx) const { |
| 4202 | llvm_unreachable("ResumeInst has no successors!")__builtin_unreachable(); |
| 4203 | } |
| 4204 | |
| 4205 | void setSuccessor(unsigned idx, BasicBlock *NewSucc) { |
| 4206 | llvm_unreachable("ResumeInst has no successors!")__builtin_unreachable(); |
| 4207 | } |
| 4208 | }; |
| 4209 | |
| 4210 | template <> |
| 4211 | struct OperandTraits<ResumeInst> : |
| 4212 | public FixedNumOperandTraits<ResumeInst, 1> { |
| 4213 | }; |
| 4214 | |
| 4215 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(ResumeInst, Value)ResumeInst::op_iterator ResumeInst::op_begin() { return OperandTraits <ResumeInst>::op_begin(this); } ResumeInst::const_op_iterator ResumeInst::op_begin() const { return OperandTraits<ResumeInst >::op_begin(const_cast<ResumeInst*>(this)); } ResumeInst ::op_iterator ResumeInst::op_end() { return OperandTraits< ResumeInst>::op_end(this); } ResumeInst::const_op_iterator ResumeInst::op_end() const { return OperandTraits<ResumeInst >::op_end(const_cast<ResumeInst*>(this)); } Value *ResumeInst ::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null <Value>( OperandTraits<ResumeInst>::op_begin(const_cast <ResumeInst*>(this))[i_nocapture].get()); } void ResumeInst ::setOperand(unsigned i_nocapture, Value *Val_nocapture) { (( void)0); OperandTraits<ResumeInst>::op_begin(this)[i_nocapture ] = Val_nocapture; } unsigned ResumeInst::getNumOperands() const { return OperandTraits<ResumeInst>::operands(this); } template <int Idx_nocapture> Use &ResumeInst::Op() { return this->OpFrom<Idx_nocapture>(this); } template <int Idx_nocapture> const Use &ResumeInst::Op() const { return this->OpFrom<Idx_nocapture>(this); } |
| 4216 | |
| 4217 | //===----------------------------------------------------------------------===// |
| 4218 | // CatchSwitchInst Class |
| 4219 | //===----------------------------------------------------------------------===// |
| 4220 | class CatchSwitchInst : public Instruction { |
| 4221 | using UnwindDestField = BoolBitfieldElementT<0>; |
| 4222 | |
| 4223 | /// The number of operands actually allocated. NumOperands is |
| 4224 | /// the number actually in use. |
| 4225 | unsigned ReservedSpace; |
| 4226 | |
| 4227 | // Operand[0] = Outer scope |
| 4228 | // Operand[1] = Unwind block destination |
| 4229 | // Operand[n] = BasicBlock to go to on match |
| 4230 | CatchSwitchInst(const CatchSwitchInst &CSI); |
| 4231 | |
| 4232 | /// Create a new switch instruction, specifying a |
| 4233 | /// default destination. The number of additional handlers can be specified |
| 4234 | /// here to make memory allocation more efficient. |
| 4235 | /// This constructor can also autoinsert before another instruction. |
| 4236 | CatchSwitchInst(Value *ParentPad, BasicBlock *UnwindDest, |
| 4237 | unsigned NumHandlers, const Twine &NameStr, |
| 4238 | Instruction *InsertBefore); |
| 4239 | |
| 4240 | /// Create a new switch instruction, specifying a |
| 4241 | /// default destination. The number of additional handlers can be specified |
| 4242 | /// here to make memory allocation more efficient. |
| 4243 | /// This constructor also autoinserts at the end of the specified BasicBlock. |
| 4244 | CatchSwitchInst(Value *ParentPad, BasicBlock *UnwindDest, |
| 4245 | unsigned NumHandlers, const Twine &NameStr, |
| 4246 | BasicBlock *InsertAtEnd); |
| 4247 | |
| 4248 | // allocate space for exactly zero operands |
| 4249 | void *operator new(size_t S) { return User::operator new(S); } |
| 4250 | |
| 4251 | void init(Value *ParentPad, BasicBlock *UnwindDest, unsigned NumReserved); |
| 4252 | void growOperands(unsigned Size); |
| 4253 | |
| 4254 | protected: |
| 4255 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4256 | friend class Instruction; |
| 4257 | |
| 4258 | CatchSwitchInst *cloneImpl() const; |
| 4259 | |
| 4260 | public: |
| 4261 | void operator delete(void *Ptr) { return User::operator delete(Ptr); } |
| 4262 | |
| 4263 | static CatchSwitchInst *Create(Value *ParentPad, BasicBlock *UnwindDest, |
| 4264 | unsigned NumHandlers, |
| 4265 | const Twine &NameStr = "", |
| 4266 | Instruction *InsertBefore = nullptr) { |
| 4267 | return new CatchSwitchInst(ParentPad, UnwindDest, NumHandlers, NameStr, |
| 4268 | InsertBefore); |
| 4269 | } |
| 4270 | |
| 4271 | static CatchSwitchInst *Create(Value *ParentPad, BasicBlock *UnwindDest, |
| 4272 | unsigned NumHandlers, const Twine &NameStr, |
| 4273 | BasicBlock *InsertAtEnd) { |
| 4274 | return new CatchSwitchInst(ParentPad, UnwindDest, NumHandlers, NameStr, |
| 4275 | InsertAtEnd); |
| 4276 | } |
| 4277 | |
| 4278 | /// Provide fast operand accessors |
| 4279 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 4280 | |
| 4281 | // Accessor Methods for CatchSwitch stmt |
| 4282 | Value *getParentPad() const { return getOperand(0); } |
| 4283 | void setParentPad(Value *ParentPad) { setOperand(0, ParentPad); } |
| 4284 | |
| 4285 | // Accessor Methods for CatchSwitch stmt |
| 4286 | bool hasUnwindDest() const { return getSubclassData<UnwindDestField>(); } |
| 4287 | bool unwindsToCaller() const { return !hasUnwindDest(); } |
| 4288 | BasicBlock *getUnwindDest() const { |
| 4289 | if (hasUnwindDest()) |
| 4290 | return cast<BasicBlock>(getOperand(1)); |
| 4291 | return nullptr; |
| 4292 | } |
| 4293 | void setUnwindDest(BasicBlock *UnwindDest) { |
| 4294 | assert(UnwindDest)((void)0); |
| 4295 | assert(hasUnwindDest())((void)0); |
| 4296 | setOperand(1, UnwindDest); |
| 4297 | } |
| 4298 | |
| 4299 | /// return the number of 'handlers' in this catchswitch |
| 4300 | /// instruction, except the default handler |
| 4301 | unsigned getNumHandlers() const { |
| 4302 | if (hasUnwindDest()) |
| 4303 | return getNumOperands() - 2; |
| 4304 | return getNumOperands() - 1; |
| 4305 | } |
| 4306 | |
| 4307 | private: |
| 4308 | static BasicBlock *handler_helper(Value *V) { return cast<BasicBlock>(V); } |
| 4309 | static const BasicBlock *handler_helper(const Value *V) { |
| 4310 | return cast<BasicBlock>(V); |
| 4311 | } |
| 4312 | |
| 4313 | public: |
| 4314 | using DerefFnTy = BasicBlock *(*)(Value *); |
| 4315 | using handler_iterator = mapped_iterator<op_iterator, DerefFnTy>; |
| 4316 | using handler_range = iterator_range<handler_iterator>; |
| 4317 | using ConstDerefFnTy = const BasicBlock *(*)(const Value *); |
| 4318 | using const_handler_iterator = |
| 4319 | mapped_iterator<const_op_iterator, ConstDerefFnTy>; |
| 4320 | using const_handler_range = iterator_range<const_handler_iterator>; |
| 4321 | |
| 4322 | /// Returns an iterator that points to the first handler in CatchSwitchInst. |
| 4323 | handler_iterator handler_begin() { |
| 4324 | op_iterator It = op_begin() + 1; |
| 4325 | if (hasUnwindDest()) |
| 4326 | ++It; |
| 4327 | return handler_iterator(It, DerefFnTy(handler_helper)); |
| 4328 | } |
| 4329 | |
| 4330 | /// Returns an iterator that points to the first handler in the |
| 4331 | /// CatchSwitchInst. |
| 4332 | const_handler_iterator handler_begin() const { |
| 4333 | const_op_iterator It = op_begin() + 1; |
| 4334 | if (hasUnwindDest()) |
| 4335 | ++It; |
| 4336 | return const_handler_iterator(It, ConstDerefFnTy(handler_helper)); |
| 4337 | } |
| 4338 | |
| 4339 | /// Returns a read-only iterator that points one past the last |
| 4340 | /// handler in the CatchSwitchInst. |
| 4341 | handler_iterator handler_end() { |
| 4342 | return handler_iterator(op_end(), DerefFnTy(handler_helper)); |
| 4343 | } |
| 4344 | |
| 4345 | /// Returns an iterator that points one past the last handler in the |
| 4346 | /// CatchSwitchInst. |
| 4347 | const_handler_iterator handler_end() const { |
| 4348 | return const_handler_iterator(op_end(), ConstDerefFnTy(handler_helper)); |
| 4349 | } |
| 4350 | |
| 4351 | /// iteration adapter for range-for loops. |
| 4352 | handler_range handlers() { |
| 4353 | return make_range(handler_begin(), handler_end()); |
| 4354 | } |
| 4355 | |
| 4356 | /// iteration adapter for range-for loops. |
| 4357 | const_handler_range handlers() const { |
| 4358 | return make_range(handler_begin(), handler_end()); |
| 4359 | } |
| 4360 | |
| 4361 | /// Add an entry to the switch instruction... |
| 4362 | /// Note: |
| 4363 | /// This action invalidates handler_end(). Old handler_end() iterator will |
| 4364 | /// point to the added handler. |
| 4365 | void addHandler(BasicBlock *Dest); |
| 4366 | |
| 4367 | void removeHandler(handler_iterator HI); |
| 4368 | |
| 4369 | unsigned getNumSuccessors() const { return getNumOperands() - 1; } |
| 4370 | BasicBlock *getSuccessor(unsigned Idx) const { |
| 4371 | assert(Idx < getNumSuccessors() &&((void)0) |
| 4372 | "Successor # out of range for catchswitch!")((void)0); |
| 4373 | return cast<BasicBlock>(getOperand(Idx + 1)); |
| 4374 | } |
| 4375 | void setSuccessor(unsigned Idx, BasicBlock *NewSucc) { |
| 4376 | assert(Idx < getNumSuccessors() &&((void)0) |
| 4377 | "Successor # out of range for catchswitch!")((void)0); |
| 4378 | setOperand(Idx + 1, NewSucc); |
| 4379 | } |
| 4380 | |
| 4381 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4382 | static bool classof(const Instruction *I) { |
| 4383 | return I->getOpcode() == Instruction::CatchSwitch; |
| 4384 | } |
| 4385 | static bool classof(const Value *V) { |
| 4386 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4387 | } |
| 4388 | }; |
| 4389 | |
| 4390 | template <> |
| 4391 | struct OperandTraits<CatchSwitchInst> : public HungoffOperandTraits<2> {}; |
| 4392 | |
| 4393 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CatchSwitchInst, Value)CatchSwitchInst::op_iterator CatchSwitchInst::op_begin() { return OperandTraits<CatchSwitchInst>::op_begin(this); } CatchSwitchInst ::const_op_iterator CatchSwitchInst::op_begin() const { return OperandTraits<CatchSwitchInst>::op_begin(const_cast< CatchSwitchInst*>(this)); } CatchSwitchInst::op_iterator CatchSwitchInst ::op_end() { return OperandTraits<CatchSwitchInst>::op_end (this); } CatchSwitchInst::const_op_iterator CatchSwitchInst:: op_end() const { return OperandTraits<CatchSwitchInst>:: op_end(const_cast<CatchSwitchInst*>(this)); } Value *CatchSwitchInst ::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null <Value>( OperandTraits<CatchSwitchInst>::op_begin (const_cast<CatchSwitchInst*>(this))[i_nocapture].get() ); } void CatchSwitchInst::setOperand(unsigned i_nocapture, Value *Val_nocapture) { ((void)0); OperandTraits<CatchSwitchInst >::op_begin(this)[i_nocapture] = Val_nocapture; } unsigned CatchSwitchInst::getNumOperands() const { return OperandTraits <CatchSwitchInst>::operands(this); } template <int Idx_nocapture > Use &CatchSwitchInst::Op() { return this->OpFrom< Idx_nocapture>(this); } template <int Idx_nocapture> const Use &CatchSwitchInst::Op() const { return this-> OpFrom<Idx_nocapture>(this); } |
| 4394 | |
| 4395 | //===----------------------------------------------------------------------===// |
| 4396 | // CleanupPadInst Class |
| 4397 | //===----------------------------------------------------------------------===// |
| 4398 | class CleanupPadInst : public FuncletPadInst { |
| 4399 | private: |
| 4400 | explicit CleanupPadInst(Value *ParentPad, ArrayRef<Value *> Args, |
| 4401 | unsigned Values, const Twine &NameStr, |
| 4402 | Instruction *InsertBefore) |
| 4403 | : FuncletPadInst(Instruction::CleanupPad, ParentPad, Args, Values, |
| 4404 | NameStr, InsertBefore) {} |
| 4405 | explicit CleanupPadInst(Value *ParentPad, ArrayRef<Value *> Args, |
| 4406 | unsigned Values, const Twine &NameStr, |
| 4407 | BasicBlock *InsertAtEnd) |
| 4408 | : FuncletPadInst(Instruction::CleanupPad, ParentPad, Args, Values, |
| 4409 | NameStr, InsertAtEnd) {} |
| 4410 | |
| 4411 | public: |
| 4412 | static CleanupPadInst *Create(Value *ParentPad, ArrayRef<Value *> Args = None, |
| 4413 | const Twine &NameStr = "", |
| 4414 | Instruction *InsertBefore = nullptr) { |
| 4415 | unsigned Values = 1 + Args.size(); |
| 4416 | return new (Values) |
| 4417 | CleanupPadInst(ParentPad, Args, Values, NameStr, InsertBefore); |
| 4418 | } |
| 4419 | |
| 4420 | static CleanupPadInst *Create(Value *ParentPad, ArrayRef<Value *> Args, |
| 4421 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 4422 | unsigned Values = 1 + Args.size(); |
| 4423 | return new (Values) |
| 4424 | CleanupPadInst(ParentPad, Args, Values, NameStr, InsertAtEnd); |
| 4425 | } |
| 4426 | |
| 4427 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4428 | static bool classof(const Instruction *I) { |
| 4429 | return I->getOpcode() == Instruction::CleanupPad; |
| 4430 | } |
| 4431 | static bool classof(const Value *V) { |
| 4432 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4433 | } |
| 4434 | }; |
| 4435 | |
| 4436 | //===----------------------------------------------------------------------===// |
| 4437 | // CatchPadInst Class |
| 4438 | //===----------------------------------------------------------------------===// |
| 4439 | class CatchPadInst : public FuncletPadInst { |
| 4440 | private: |
| 4441 | explicit CatchPadInst(Value *CatchSwitch, ArrayRef<Value *> Args, |
| 4442 | unsigned Values, const Twine &NameStr, |
| 4443 | Instruction *InsertBefore) |
| 4444 | : FuncletPadInst(Instruction::CatchPad, CatchSwitch, Args, Values, |
| 4445 | NameStr, InsertBefore) {} |
| 4446 | explicit CatchPadInst(Value *CatchSwitch, ArrayRef<Value *> Args, |
| 4447 | unsigned Values, const Twine &NameStr, |
| 4448 | BasicBlock *InsertAtEnd) |
| 4449 | : FuncletPadInst(Instruction::CatchPad, CatchSwitch, Args, Values, |
| 4450 | NameStr, InsertAtEnd) {} |
| 4451 | |
| 4452 | public: |
| 4453 | static CatchPadInst *Create(Value *CatchSwitch, ArrayRef<Value *> Args, |
| 4454 | const Twine &NameStr = "", |
| 4455 | Instruction *InsertBefore = nullptr) { |
| 4456 | unsigned Values = 1 + Args.size(); |
| 4457 | return new (Values) |
| 4458 | CatchPadInst(CatchSwitch, Args, Values, NameStr, InsertBefore); |
| 4459 | } |
| 4460 | |
| 4461 | static CatchPadInst *Create(Value *CatchSwitch, ArrayRef<Value *> Args, |
| 4462 | const Twine &NameStr, BasicBlock *InsertAtEnd) { |
| 4463 | unsigned Values = 1 + Args.size(); |
| 4464 | return new (Values) |
| 4465 | CatchPadInst(CatchSwitch, Args, Values, NameStr, InsertAtEnd); |
| 4466 | } |
| 4467 | |
| 4468 | /// Convenience accessors |
| 4469 | CatchSwitchInst *getCatchSwitch() const { |
| 4470 | return cast<CatchSwitchInst>(Op<-1>()); |
| 4471 | } |
| 4472 | void setCatchSwitch(Value *CatchSwitch) { |
| 4473 | assert(CatchSwitch)((void)0); |
| 4474 | Op<-1>() = CatchSwitch; |
| 4475 | } |
| 4476 | |
| 4477 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4478 | static bool classof(const Instruction *I) { |
| 4479 | return I->getOpcode() == Instruction::CatchPad; |
| 4480 | } |
| 4481 | static bool classof(const Value *V) { |
| 4482 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4483 | } |
| 4484 | }; |
| 4485 | |
| 4486 | //===----------------------------------------------------------------------===// |
| 4487 | // CatchReturnInst Class |
| 4488 | //===----------------------------------------------------------------------===// |
| 4489 | |
| 4490 | class CatchReturnInst : public Instruction { |
| 4491 | CatchReturnInst(const CatchReturnInst &RI); |
| 4492 | CatchReturnInst(Value *CatchPad, BasicBlock *BB, Instruction *InsertBefore); |
| 4493 | CatchReturnInst(Value *CatchPad, BasicBlock *BB, BasicBlock *InsertAtEnd); |
| 4494 | |
| 4495 | void init(Value *CatchPad, BasicBlock *BB); |
| 4496 | |
| 4497 | protected: |
| 4498 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4499 | friend class Instruction; |
| 4500 | |
| 4501 | CatchReturnInst *cloneImpl() const; |
| 4502 | |
| 4503 | public: |
| 4504 | static CatchReturnInst *Create(Value *CatchPad, BasicBlock *BB, |
| 4505 | Instruction *InsertBefore = nullptr) { |
| 4506 | assert(CatchPad)((void)0); |
| 4507 | assert(BB)((void)0); |
| 4508 | return new (2) CatchReturnInst(CatchPad, BB, InsertBefore); |
| 4509 | } |
| 4510 | |
| 4511 | static CatchReturnInst *Create(Value *CatchPad, BasicBlock *BB, |
| 4512 | BasicBlock *InsertAtEnd) { |
| 4513 | assert(CatchPad)((void)0); |
| 4514 | assert(BB)((void)0); |
| 4515 | return new (2) CatchReturnInst(CatchPad, BB, InsertAtEnd); |
| 4516 | } |
| 4517 | |
| 4518 | /// Provide fast operand accessors |
| 4519 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 4520 | |
| 4521 | /// Convenience accessors. |
| 4522 | CatchPadInst *getCatchPad() const { return cast<CatchPadInst>(Op<0>()); } |
| 4523 | void setCatchPad(CatchPadInst *CatchPad) { |
| 4524 | assert(CatchPad)((void)0); |
| 4525 | Op<0>() = CatchPad; |
| 4526 | } |
| 4527 | |
| 4528 | BasicBlock *getSuccessor() const { return cast<BasicBlock>(Op<1>()); } |
| 4529 | void setSuccessor(BasicBlock *NewSucc) { |
| 4530 | assert(NewSucc)((void)0); |
| 4531 | Op<1>() = NewSucc; |
| 4532 | } |
| 4533 | unsigned getNumSuccessors() const { return 1; } |
| 4534 | |
| 4535 | /// Get the parentPad of this catchret's catchpad's catchswitch. |
| 4536 | /// The successor block is implicitly a member of this funclet. |
| 4537 | Value *getCatchSwitchParentPad() const { |
| 4538 | return getCatchPad()->getCatchSwitch()->getParentPad(); |
| 4539 | } |
| 4540 | |
| 4541 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4542 | static bool classof(const Instruction *I) { |
| 4543 | return (I->getOpcode() == Instruction::CatchRet); |
| 4544 | } |
| 4545 | static bool classof(const Value *V) { |
| 4546 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4547 | } |
| 4548 | |
| 4549 | private: |
| 4550 | BasicBlock *getSuccessor(unsigned Idx) const { |
| 4551 | assert(Idx < getNumSuccessors() && "Successor # out of range for catchret!")((void)0); |
| 4552 | return getSuccessor(); |
| 4553 | } |
| 4554 | |
| 4555 | void setSuccessor(unsigned Idx, BasicBlock *B) { |
| 4556 | assert(Idx < getNumSuccessors() && "Successor # out of range for catchret!")((void)0); |
| 4557 | setSuccessor(B); |
| 4558 | } |
| 4559 | }; |
| 4560 | |
| 4561 | template <> |
| 4562 | struct OperandTraits<CatchReturnInst> |
| 4563 | : public FixedNumOperandTraits<CatchReturnInst, 2> {}; |
| 4564 | |
| 4565 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CatchReturnInst, Value)CatchReturnInst::op_iterator CatchReturnInst::op_begin() { return OperandTraits<CatchReturnInst>::op_begin(this); } CatchReturnInst ::const_op_iterator CatchReturnInst::op_begin() const { return OperandTraits<CatchReturnInst>::op_begin(const_cast< CatchReturnInst*>(this)); } CatchReturnInst::op_iterator CatchReturnInst ::op_end() { return OperandTraits<CatchReturnInst>::op_end (this); } CatchReturnInst::const_op_iterator CatchReturnInst:: op_end() const { return OperandTraits<CatchReturnInst>:: op_end(const_cast<CatchReturnInst*>(this)); } Value *CatchReturnInst ::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null <Value>( OperandTraits<CatchReturnInst>::op_begin (const_cast<CatchReturnInst*>(this))[i_nocapture].get() ); } void CatchReturnInst::setOperand(unsigned i_nocapture, Value *Val_nocapture) { ((void)0); OperandTraits<CatchReturnInst >::op_begin(this)[i_nocapture] = Val_nocapture; } unsigned CatchReturnInst::getNumOperands() const { return OperandTraits <CatchReturnInst>::operands(this); } template <int Idx_nocapture > Use &CatchReturnInst::Op() { return this->OpFrom< Idx_nocapture>(this); } template <int Idx_nocapture> const Use &CatchReturnInst::Op() const { return this-> OpFrom<Idx_nocapture>(this); } |
| 4566 | |
| 4567 | //===----------------------------------------------------------------------===// |
| 4568 | // CleanupReturnInst Class |
| 4569 | //===----------------------------------------------------------------------===// |
| 4570 | |
| 4571 | class CleanupReturnInst : public Instruction { |
| 4572 | using UnwindDestField = BoolBitfieldElementT<0>; |
| 4573 | |
| 4574 | private: |
| 4575 | CleanupReturnInst(const CleanupReturnInst &RI); |
| 4576 | CleanupReturnInst(Value *CleanupPad, BasicBlock *UnwindBB, unsigned Values, |
| 4577 | Instruction *InsertBefore = nullptr); |
| 4578 | CleanupReturnInst(Value *CleanupPad, BasicBlock *UnwindBB, unsigned Values, |
| 4579 | BasicBlock *InsertAtEnd); |
| 4580 | |
| 4581 | void init(Value *CleanupPad, BasicBlock *UnwindBB); |
| 4582 | |
| 4583 | protected: |
| 4584 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4585 | friend class Instruction; |
| 4586 | |
| 4587 | CleanupReturnInst *cloneImpl() const; |
| 4588 | |
| 4589 | public: |
| 4590 | static CleanupReturnInst *Create(Value *CleanupPad, |
| 4591 | BasicBlock *UnwindBB = nullptr, |
| 4592 | Instruction *InsertBefore = nullptr) { |
| 4593 | assert(CleanupPad)((void)0); |
| 4594 | unsigned Values = 1; |
| 4595 | if (UnwindBB) |
| 4596 | ++Values; |
| 4597 | return new (Values) |
| 4598 | CleanupReturnInst(CleanupPad, UnwindBB, Values, InsertBefore); |
| 4599 | } |
| 4600 | |
| 4601 | static CleanupReturnInst *Create(Value *CleanupPad, BasicBlock *UnwindBB, |
| 4602 | BasicBlock *InsertAtEnd) { |
| 4603 | assert(CleanupPad)((void)0); |
| 4604 | unsigned Values = 1; |
| 4605 | if (UnwindBB) |
| 4606 | ++Values; |
| 4607 | return new (Values) |
| 4608 | CleanupReturnInst(CleanupPad, UnwindBB, Values, InsertAtEnd); |
| 4609 | } |
| 4610 | |
| 4611 | /// Provide fast operand accessors |
| 4612 | DECLARE_TRANSPARENT_OPERAND_ACCESSORS(Value)public: inline Value *getOperand(unsigned) const; inline void setOperand(unsigned, Value*); inline op_iterator op_begin(); inline const_op_iterator op_begin() const; inline op_iterator op_end(); inline const_op_iterator op_end() const; protected : template <int> inline Use &Op(); template <int > inline const Use &Op() const; public: inline unsigned getNumOperands() const; |
| 4613 | |
| 4614 | bool hasUnwindDest() const { return getSubclassData<UnwindDestField>(); } |
| 4615 | bool unwindsToCaller() const { return !hasUnwindDest(); } |
| 4616 | |
| 4617 | /// Convenience accessor. |
| 4618 | CleanupPadInst *getCleanupPad() const { |
| 4619 | return cast<CleanupPadInst>(Op<0>()); |
| 4620 | } |
| 4621 | void setCleanupPad(CleanupPadInst *CleanupPad) { |
| 4622 | assert(CleanupPad)((void)0); |
| 4623 | Op<0>() = CleanupPad; |
| 4624 | } |
| 4625 | |
| 4626 | unsigned getNumSuccessors() const { return hasUnwindDest() ? 1 : 0; } |
| 4627 | |
| 4628 | BasicBlock *getUnwindDest() const { |
| 4629 | return hasUnwindDest() ? cast<BasicBlock>(Op<1>()) : nullptr; |
| 4630 | } |
| 4631 | void setUnwindDest(BasicBlock *NewDest) { |
| 4632 | assert(NewDest)((void)0); |
| 4633 | assert(hasUnwindDest())((void)0); |
| 4634 | Op<1>() = NewDest; |
| 4635 | } |
| 4636 | |
| 4637 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4638 | static bool classof(const Instruction *I) { |
| 4639 | return (I->getOpcode() == Instruction::CleanupRet); |
| 4640 | } |
| 4641 | static bool classof(const Value *V) { |
| 4642 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4643 | } |
| 4644 | |
| 4645 | private: |
| 4646 | BasicBlock *getSuccessor(unsigned Idx) const { |
| 4647 | assert(Idx == 0)((void)0); |
| 4648 | return getUnwindDest(); |
| 4649 | } |
| 4650 | |
| 4651 | void setSuccessor(unsigned Idx, BasicBlock *B) { |
| 4652 | assert(Idx == 0)((void)0); |
| 4653 | setUnwindDest(B); |
| 4654 | } |
| 4655 | |
| 4656 | // Shadow Instruction::setInstructionSubclassData with a private forwarding |
| 4657 | // method so that subclasses cannot accidentally use it. |
| 4658 | template <typename Bitfield> |
| 4659 | void setSubclassData(typename Bitfield::Type Value) { |
| 4660 | Instruction::setSubclassData<Bitfield>(Value); |
| 4661 | } |
| 4662 | }; |
| 4663 | |
| 4664 | template <> |
| 4665 | struct OperandTraits<CleanupReturnInst> |
| 4666 | : public VariadicOperandTraits<CleanupReturnInst, /*MINARITY=*/1> {}; |
| 4667 | |
| 4668 | DEFINE_TRANSPARENT_OPERAND_ACCESSORS(CleanupReturnInst, Value)CleanupReturnInst::op_iterator CleanupReturnInst::op_begin() { return OperandTraits<CleanupReturnInst>::op_begin(this ); } CleanupReturnInst::const_op_iterator CleanupReturnInst:: op_begin() const { return OperandTraits<CleanupReturnInst> ::op_begin(const_cast<CleanupReturnInst*>(this)); } CleanupReturnInst ::op_iterator CleanupReturnInst::op_end() { return OperandTraits <CleanupReturnInst>::op_end(this); } CleanupReturnInst:: const_op_iterator CleanupReturnInst::op_end() const { return OperandTraits <CleanupReturnInst>::op_end(const_cast<CleanupReturnInst *>(this)); } Value *CleanupReturnInst::getOperand(unsigned i_nocapture) const { ((void)0); return cast_or_null<Value >( OperandTraits<CleanupReturnInst>::op_begin(const_cast <CleanupReturnInst*>(this))[i_nocapture].get()); } void CleanupReturnInst::setOperand(unsigned i_nocapture, Value *Val_nocapture ) { ((void)0); OperandTraits<CleanupReturnInst>::op_begin (this)[i_nocapture] = Val_nocapture; } unsigned CleanupReturnInst ::getNumOperands() const { return OperandTraits<CleanupReturnInst >::operands(this); } template <int Idx_nocapture> Use &CleanupReturnInst::Op() { return this->OpFrom<Idx_nocapture >(this); } template <int Idx_nocapture> const Use & CleanupReturnInst::Op() const { return this->OpFrom<Idx_nocapture >(this); } |
| 4669 | |
| 4670 | //===----------------------------------------------------------------------===// |
| 4671 | // UnreachableInst Class |
| 4672 | //===----------------------------------------------------------------------===// |
| 4673 | |
| 4674 | //===--------------------------------------------------------------------------- |
| 4675 | /// This function has undefined behavior. In particular, the |
| 4676 | /// presence of this instruction indicates some higher level knowledge that the |
| 4677 | /// end of the block cannot be reached. |
| 4678 | /// |
| 4679 | class UnreachableInst : public Instruction { |
| 4680 | protected: |
| 4681 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4682 | friend class Instruction; |
| 4683 | |
| 4684 | UnreachableInst *cloneImpl() const; |
| 4685 | |
| 4686 | public: |
| 4687 | explicit UnreachableInst(LLVMContext &C, Instruction *InsertBefore = nullptr); |
| 4688 | explicit UnreachableInst(LLVMContext &C, BasicBlock *InsertAtEnd); |
| 4689 | |
| 4690 | // allocate space for exactly zero operands |
| 4691 | void *operator new(size_t S) { return User::operator new(S, 0); } |
| 4692 | void operator delete(void *Ptr) { User::operator delete(Ptr); } |
| 4693 | |
| 4694 | unsigned getNumSuccessors() const { return 0; } |
| 4695 | |
| 4696 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4697 | static bool classof(const Instruction *I) { |
| 4698 | return I->getOpcode() == Instruction::Unreachable; |
| 4699 | } |
| 4700 | static bool classof(const Value *V) { |
| 4701 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4702 | } |
| 4703 | |
| 4704 | private: |
| 4705 | BasicBlock *getSuccessor(unsigned idx) const { |
| 4706 | llvm_unreachable("UnreachableInst has no successors!")__builtin_unreachable(); |
| 4707 | } |
| 4708 | |
| 4709 | void setSuccessor(unsigned idx, BasicBlock *B) { |
| 4710 | llvm_unreachable("UnreachableInst has no successors!")__builtin_unreachable(); |
| 4711 | } |
| 4712 | }; |
| 4713 | |
| 4714 | //===----------------------------------------------------------------------===// |
| 4715 | // TruncInst Class |
| 4716 | //===----------------------------------------------------------------------===// |
| 4717 | |
| 4718 | /// This class represents a truncation of integer types. |
| 4719 | class TruncInst : public CastInst { |
| 4720 | protected: |
| 4721 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4722 | friend class Instruction; |
| 4723 | |
| 4724 | /// Clone an identical TruncInst |
| 4725 | TruncInst *cloneImpl() const; |
| 4726 | |
| 4727 | public: |
| 4728 | /// Constructor with insert-before-instruction semantics |
| 4729 | TruncInst( |
| 4730 | Value *S, ///< The value to be truncated |
| 4731 | Type *Ty, ///< The (smaller) type to truncate to |
| 4732 | const Twine &NameStr = "", ///< A name for the new instruction |
| 4733 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 4734 | ); |
| 4735 | |
| 4736 | /// Constructor with insert-at-end-of-block semantics |
| 4737 | TruncInst( |
| 4738 | Value *S, ///< The value to be truncated |
| 4739 | Type *Ty, ///< The (smaller) type to truncate to |
| 4740 | const Twine &NameStr, ///< A name for the new instruction |
| 4741 | BasicBlock *InsertAtEnd ///< The block to insert the instruction into |
| 4742 | ); |
| 4743 | |
| 4744 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4745 | static bool classof(const Instruction *I) { |
| 4746 | return I->getOpcode() == Trunc; |
| 4747 | } |
| 4748 | static bool classof(const Value *V) { |
| 4749 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4750 | } |
| 4751 | }; |
| 4752 | |
| 4753 | //===----------------------------------------------------------------------===// |
| 4754 | // ZExtInst Class |
| 4755 | //===----------------------------------------------------------------------===// |
| 4756 | |
| 4757 | /// This class represents zero extension of integer types. |
| 4758 | class ZExtInst : public CastInst { |
| 4759 | protected: |
| 4760 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4761 | friend class Instruction; |
| 4762 | |
| 4763 | /// Clone an identical ZExtInst |
| 4764 | ZExtInst *cloneImpl() const; |
| 4765 | |
| 4766 | public: |
| 4767 | /// Constructor with insert-before-instruction semantics |
| 4768 | ZExtInst( |
| 4769 | Value *S, ///< The value to be zero extended |
| 4770 | Type *Ty, ///< The type to zero extend to |
| 4771 | const Twine &NameStr = "", ///< A name for the new instruction |
| 4772 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 4773 | ); |
| 4774 | |
| 4775 | /// Constructor with insert-at-end semantics. |
| 4776 | ZExtInst( |
| 4777 | Value *S, ///< The value to be zero extended |
| 4778 | Type *Ty, ///< The type to zero extend to |
| 4779 | const Twine &NameStr, ///< A name for the new instruction |
| 4780 | BasicBlock *InsertAtEnd ///< The block to insert the instruction into |
| 4781 | ); |
| 4782 | |
| 4783 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4784 | static bool classof(const Instruction *I) { |
| 4785 | return I->getOpcode() == ZExt; |
| 4786 | } |
| 4787 | static bool classof(const Value *V) { |
| 4788 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4789 | } |
| 4790 | }; |
| 4791 | |
| 4792 | //===----------------------------------------------------------------------===// |
| 4793 | // SExtInst Class |
| 4794 | //===----------------------------------------------------------------------===// |
| 4795 | |
| 4796 | /// This class represents a sign extension of integer types. |
| 4797 | class SExtInst : public CastInst { |
| 4798 | protected: |
| 4799 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4800 | friend class Instruction; |
| 4801 | |
| 4802 | /// Clone an identical SExtInst |
| 4803 | SExtInst *cloneImpl() const; |
| 4804 | |
| 4805 | public: |
| 4806 | /// Constructor with insert-before-instruction semantics |
| 4807 | SExtInst( |
| 4808 | Value *S, ///< The value to be sign extended |
| 4809 | Type *Ty, ///< The type to sign extend to |
| 4810 | const Twine &NameStr = "", ///< A name for the new instruction |
| 4811 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 4812 | ); |
| 4813 | |
| 4814 | /// Constructor with insert-at-end-of-block semantics |
| 4815 | SExtInst( |
| 4816 | Value *S, ///< The value to be sign extended |
| 4817 | Type *Ty, ///< The type to sign extend to |
| 4818 | const Twine &NameStr, ///< A name for the new instruction |
| 4819 | BasicBlock *InsertAtEnd ///< The block to insert the instruction into |
| 4820 | ); |
| 4821 | |
| 4822 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4823 | static bool classof(const Instruction *I) { |
| 4824 | return I->getOpcode() == SExt; |
| 4825 | } |
| 4826 | static bool classof(const Value *V) { |
| 4827 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4828 | } |
| 4829 | }; |
| 4830 | |
| 4831 | //===----------------------------------------------------------------------===// |
| 4832 | // FPTruncInst Class |
| 4833 | //===----------------------------------------------------------------------===// |
| 4834 | |
| 4835 | /// This class represents a truncation of floating point types. |
| 4836 | class FPTruncInst : public CastInst { |
| 4837 | protected: |
| 4838 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4839 | friend class Instruction; |
| 4840 | |
| 4841 | /// Clone an identical FPTruncInst |
| 4842 | FPTruncInst *cloneImpl() const; |
| 4843 | |
| 4844 | public: |
| 4845 | /// Constructor with insert-before-instruction semantics |
| 4846 | FPTruncInst( |
| 4847 | Value *S, ///< The value to be truncated |
| 4848 | Type *Ty, ///< The type to truncate to |
| 4849 | const Twine &NameStr = "", ///< A name for the new instruction |
| 4850 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 4851 | ); |
| 4852 | |
| 4853 | /// Constructor with insert-before-instruction semantics |
| 4854 | FPTruncInst( |
| 4855 | Value *S, ///< The value to be truncated |
| 4856 | Type *Ty, ///< The type to truncate to |
| 4857 | const Twine &NameStr, ///< A name for the new instruction |
| 4858 | BasicBlock *InsertAtEnd ///< The block to insert the instruction into |
| 4859 | ); |
| 4860 | |
| 4861 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4862 | static bool classof(const Instruction *I) { |
| 4863 | return I->getOpcode() == FPTrunc; |
| 4864 | } |
| 4865 | static bool classof(const Value *V) { |
| 4866 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4867 | } |
| 4868 | }; |
| 4869 | |
| 4870 | //===----------------------------------------------------------------------===// |
| 4871 | // FPExtInst Class |
| 4872 | //===----------------------------------------------------------------------===// |
| 4873 | |
| 4874 | /// This class represents an extension of floating point types. |
| 4875 | class FPExtInst : public CastInst { |
| 4876 | protected: |
| 4877 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4878 | friend class Instruction; |
| 4879 | |
| 4880 | /// Clone an identical FPExtInst |
| 4881 | FPExtInst *cloneImpl() const; |
| 4882 | |
| 4883 | public: |
| 4884 | /// Constructor with insert-before-instruction semantics |
| 4885 | FPExtInst( |
| 4886 | Value *S, ///< The value to be extended |
| 4887 | Type *Ty, ///< The type to extend to |
| 4888 | const Twine &NameStr = "", ///< A name for the new instruction |
| 4889 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 4890 | ); |
| 4891 | |
| 4892 | /// Constructor with insert-at-end-of-block semantics |
| 4893 | FPExtInst( |
| 4894 | Value *S, ///< The value to be extended |
| 4895 | Type *Ty, ///< The type to extend to |
| 4896 | const Twine &NameStr, ///< A name for the new instruction |
| 4897 | BasicBlock *InsertAtEnd ///< The block to insert the instruction into |
| 4898 | ); |
| 4899 | |
| 4900 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4901 | static bool classof(const Instruction *I) { |
| 4902 | return I->getOpcode() == FPExt; |
| 4903 | } |
| 4904 | static bool classof(const Value *V) { |
| 4905 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4906 | } |
| 4907 | }; |
| 4908 | |
| 4909 | //===----------------------------------------------------------------------===// |
| 4910 | // UIToFPInst Class |
| 4911 | //===----------------------------------------------------------------------===// |
| 4912 | |
| 4913 | /// This class represents a cast unsigned integer to floating point. |
| 4914 | class UIToFPInst : public CastInst { |
| 4915 | protected: |
| 4916 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4917 | friend class Instruction; |
| 4918 | |
| 4919 | /// Clone an identical UIToFPInst |
| 4920 | UIToFPInst *cloneImpl() const; |
| 4921 | |
| 4922 | public: |
| 4923 | /// Constructor with insert-before-instruction semantics |
| 4924 | UIToFPInst( |
| 4925 | Value *S, ///< The value to be converted |
| 4926 | Type *Ty, ///< The type to convert to |
| 4927 | const Twine &NameStr = "", ///< A name for the new instruction |
| 4928 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 4929 | ); |
| 4930 | |
| 4931 | /// Constructor with insert-at-end-of-block semantics |
| 4932 | UIToFPInst( |
| 4933 | Value *S, ///< The value to be converted |
| 4934 | Type *Ty, ///< The type to convert to |
| 4935 | const Twine &NameStr, ///< A name for the new instruction |
| 4936 | BasicBlock *InsertAtEnd ///< The block to insert the instruction into |
| 4937 | ); |
| 4938 | |
| 4939 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4940 | static bool classof(const Instruction *I) { |
| 4941 | return I->getOpcode() == UIToFP; |
| 4942 | } |
| 4943 | static bool classof(const Value *V) { |
| 4944 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4945 | } |
| 4946 | }; |
| 4947 | |
| 4948 | //===----------------------------------------------------------------------===// |
| 4949 | // SIToFPInst Class |
| 4950 | //===----------------------------------------------------------------------===// |
| 4951 | |
| 4952 | /// This class represents a cast from signed integer to floating point. |
| 4953 | class SIToFPInst : public CastInst { |
| 4954 | protected: |
| 4955 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4956 | friend class Instruction; |
| 4957 | |
| 4958 | /// Clone an identical SIToFPInst |
| 4959 | SIToFPInst *cloneImpl() const; |
| 4960 | |
| 4961 | public: |
| 4962 | /// Constructor with insert-before-instruction semantics |
| 4963 | SIToFPInst( |
| 4964 | Value *S, ///< The value to be converted |
| 4965 | Type *Ty, ///< The type to convert to |
| 4966 | const Twine &NameStr = "", ///< A name for the new instruction |
| 4967 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 4968 | ); |
| 4969 | |
| 4970 | /// Constructor with insert-at-end-of-block semantics |
| 4971 | SIToFPInst( |
| 4972 | Value *S, ///< The value to be converted |
| 4973 | Type *Ty, ///< The type to convert to |
| 4974 | const Twine &NameStr, ///< A name for the new instruction |
| 4975 | BasicBlock *InsertAtEnd ///< The block to insert the instruction into |
| 4976 | ); |
| 4977 | |
| 4978 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 4979 | static bool classof(const Instruction *I) { |
| 4980 | return I->getOpcode() == SIToFP; |
| 4981 | } |
| 4982 | static bool classof(const Value *V) { |
| 4983 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 4984 | } |
| 4985 | }; |
| 4986 | |
| 4987 | //===----------------------------------------------------------------------===// |
| 4988 | // FPToUIInst Class |
| 4989 | //===----------------------------------------------------------------------===// |
| 4990 | |
| 4991 | /// This class represents a cast from floating point to unsigned integer |
| 4992 | class FPToUIInst : public CastInst { |
| 4993 | protected: |
| 4994 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 4995 | friend class Instruction; |
| 4996 | |
| 4997 | /// Clone an identical FPToUIInst |
| 4998 | FPToUIInst *cloneImpl() const; |
| 4999 | |
| 5000 | public: |
| 5001 | /// Constructor with insert-before-instruction semantics |
| 5002 | FPToUIInst( |
| 5003 | Value *S, ///< The value to be converted |
| 5004 | Type *Ty, ///< The type to convert to |
| 5005 | const Twine &NameStr = "", ///< A name for the new instruction |
| 5006 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 5007 | ); |
| 5008 | |
| 5009 | /// Constructor with insert-at-end-of-block semantics |
| 5010 | FPToUIInst( |
| 5011 | Value *S, ///< The value to be converted |
| 5012 | Type *Ty, ///< The type to convert to |
| 5013 | const Twine &NameStr, ///< A name for the new instruction |
| 5014 | BasicBlock *InsertAtEnd ///< Where to insert the new instruction |
| 5015 | ); |
| 5016 | |
| 5017 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 5018 | static bool classof(const Instruction *I) { |
| 5019 | return I->getOpcode() == FPToUI; |
| 5020 | } |
| 5021 | static bool classof(const Value *V) { |
| 5022 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 5023 | } |
| 5024 | }; |
| 5025 | |
| 5026 | //===----------------------------------------------------------------------===// |
| 5027 | // FPToSIInst Class |
| 5028 | //===----------------------------------------------------------------------===// |
| 5029 | |
| 5030 | /// This class represents a cast from floating point to signed integer. |
| 5031 | class FPToSIInst : public CastInst { |
| 5032 | protected: |
| 5033 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 5034 | friend class Instruction; |
| 5035 | |
| 5036 | /// Clone an identical FPToSIInst |
| 5037 | FPToSIInst *cloneImpl() const; |
| 5038 | |
| 5039 | public: |
| 5040 | /// Constructor with insert-before-instruction semantics |
| 5041 | FPToSIInst( |
| 5042 | Value *S, ///< The value to be converted |
| 5043 | Type *Ty, ///< The type to convert to |
| 5044 | const Twine &NameStr = "", ///< A name for the new instruction |
| 5045 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 5046 | ); |
| 5047 | |
| 5048 | /// Constructor with insert-at-end-of-block semantics |
| 5049 | FPToSIInst( |
| 5050 | Value *S, ///< The value to be converted |
| 5051 | Type *Ty, ///< The type to convert to |
| 5052 | const Twine &NameStr, ///< A name for the new instruction |
| 5053 | BasicBlock *InsertAtEnd ///< The block to insert the instruction into |
| 5054 | ); |
| 5055 | |
| 5056 | /// Methods for support type inquiry through isa, cast, and dyn_cast: |
| 5057 | static bool classof(const Instruction *I) { |
| 5058 | return I->getOpcode() == FPToSI; |
| 5059 | } |
| 5060 | static bool classof(const Value *V) { |
| 5061 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 5062 | } |
| 5063 | }; |
| 5064 | |
| 5065 | //===----------------------------------------------------------------------===// |
| 5066 | // IntToPtrInst Class |
| 5067 | //===----------------------------------------------------------------------===// |
| 5068 | |
| 5069 | /// This class represents a cast from an integer to a pointer. |
| 5070 | class IntToPtrInst : public CastInst { |
| 5071 | public: |
| 5072 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 5073 | friend class Instruction; |
| 5074 | |
| 5075 | /// Constructor with insert-before-instruction semantics |
| 5076 | IntToPtrInst( |
| 5077 | Value *S, ///< The value to be converted |
| 5078 | Type *Ty, ///< The type to convert to |
| 5079 | const Twine &NameStr = "", ///< A name for the new instruction |
| 5080 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 5081 | ); |
| 5082 | |
| 5083 | /// Constructor with insert-at-end-of-block semantics |
| 5084 | IntToPtrInst( |
| 5085 | Value *S, ///< The value to be converted |
| 5086 | Type *Ty, ///< The type to convert to |
| 5087 | const Twine &NameStr, ///< A name for the new instruction |
| 5088 | BasicBlock *InsertAtEnd ///< The block to insert the instruction into |
| 5089 | ); |
| 5090 | |
| 5091 | /// Clone an identical IntToPtrInst. |
| 5092 | IntToPtrInst *cloneImpl() const; |
| 5093 | |
| 5094 | /// Returns the address space of this instruction's pointer type. |
| 5095 | unsigned getAddressSpace() const { |
| 5096 | return getType()->getPointerAddressSpace(); |
| 5097 | } |
| 5098 | |
| 5099 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 5100 | static bool classof(const Instruction *I) { |
| 5101 | return I->getOpcode() == IntToPtr; |
| 5102 | } |
| 5103 | static bool classof(const Value *V) { |
| 5104 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 5105 | } |
| 5106 | }; |
| 5107 | |
| 5108 | //===----------------------------------------------------------------------===// |
| 5109 | // PtrToIntInst Class |
| 5110 | //===----------------------------------------------------------------------===// |
| 5111 | |
| 5112 | /// This class represents a cast from a pointer to an integer. |
| 5113 | class PtrToIntInst : public CastInst { |
| 5114 | protected: |
| 5115 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 5116 | friend class Instruction; |
| 5117 | |
| 5118 | /// Clone an identical PtrToIntInst. |
| 5119 | PtrToIntInst *cloneImpl() const; |
| 5120 | |
| 5121 | public: |
| 5122 | /// Constructor with insert-before-instruction semantics |
| 5123 | PtrToIntInst( |
| 5124 | Value *S, ///< The value to be converted |
| 5125 | Type *Ty, ///< The type to convert to |
| 5126 | const Twine &NameStr = "", ///< A name for the new instruction |
| 5127 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 5128 | ); |
| 5129 | |
| 5130 | /// Constructor with insert-at-end-of-block semantics |
| 5131 | PtrToIntInst( |
| 5132 | Value *S, ///< The value to be converted |
| 5133 | Type *Ty, ///< The type to convert to |
| 5134 | const Twine &NameStr, ///< A name for the new instruction |
| 5135 | BasicBlock *InsertAtEnd ///< The block to insert the instruction into |
| 5136 | ); |
| 5137 | |
| 5138 | /// Gets the pointer operand. |
| 5139 | Value *getPointerOperand() { return getOperand(0); } |
| 5140 | /// Gets the pointer operand. |
| 5141 | const Value *getPointerOperand() const { return getOperand(0); } |
| 5142 | /// Gets the operand index of the pointer operand. |
| 5143 | static unsigned getPointerOperandIndex() { return 0U; } |
| 5144 | |
| 5145 | /// Returns the address space of the pointer operand. |
| 5146 | unsigned getPointerAddressSpace() const { |
| 5147 | return getPointerOperand()->getType()->getPointerAddressSpace(); |
| 5148 | } |
| 5149 | |
| 5150 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 5151 | static bool classof(const Instruction *I) { |
| 5152 | return I->getOpcode() == PtrToInt; |
| 5153 | } |
| 5154 | static bool classof(const Value *V) { |
| 5155 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 5156 | } |
| 5157 | }; |
| 5158 | |
| 5159 | //===----------------------------------------------------------------------===// |
| 5160 | // BitCastInst Class |
| 5161 | //===----------------------------------------------------------------------===// |
| 5162 | |
| 5163 | /// This class represents a no-op cast from one type to another. |
| 5164 | class BitCastInst : public CastInst { |
| 5165 | protected: |
| 5166 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 5167 | friend class Instruction; |
| 5168 | |
| 5169 | /// Clone an identical BitCastInst. |
| 5170 | BitCastInst *cloneImpl() const; |
| 5171 | |
| 5172 | public: |
| 5173 | /// Constructor with insert-before-instruction semantics |
| 5174 | BitCastInst( |
| 5175 | Value *S, ///< The value to be casted |
| 5176 | Type *Ty, ///< The type to casted to |
| 5177 | const Twine &NameStr = "", ///< A name for the new instruction |
| 5178 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 5179 | ); |
| 5180 | |
| 5181 | /// Constructor with insert-at-end-of-block semantics |
| 5182 | BitCastInst( |
| 5183 | Value *S, ///< The value to be casted |
| 5184 | Type *Ty, ///< The type to casted to |
| 5185 | const Twine &NameStr, ///< A name for the new instruction |
| 5186 | BasicBlock *InsertAtEnd ///< The block to insert the instruction into |
| 5187 | ); |
| 5188 | |
| 5189 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 5190 | static bool classof(const Instruction *I) { |
| 5191 | return I->getOpcode() == BitCast; |
| 5192 | } |
| 5193 | static bool classof(const Value *V) { |
| 5194 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 5195 | } |
| 5196 | }; |
| 5197 | |
| 5198 | //===----------------------------------------------------------------------===// |
| 5199 | // AddrSpaceCastInst Class |
| 5200 | //===----------------------------------------------------------------------===// |
| 5201 | |
| 5202 | /// This class represents a conversion between pointers from one address space |
| 5203 | /// to another. |
| 5204 | class AddrSpaceCastInst : public CastInst { |
| 5205 | protected: |
| 5206 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 5207 | friend class Instruction; |
| 5208 | |
| 5209 | /// Clone an identical AddrSpaceCastInst. |
| 5210 | AddrSpaceCastInst *cloneImpl() const; |
| 5211 | |
| 5212 | public: |
| 5213 | /// Constructor with insert-before-instruction semantics |
| 5214 | AddrSpaceCastInst( |
| 5215 | Value *S, ///< The value to be casted |
| 5216 | Type *Ty, ///< The type to casted to |
| 5217 | const Twine &NameStr = "", ///< A name for the new instruction |
| 5218 | Instruction *InsertBefore = nullptr ///< Where to insert the new instruction |
| 5219 | ); |
| 5220 | |
| 5221 | /// Constructor with insert-at-end-of-block semantics |
| 5222 | AddrSpaceCastInst( |
| 5223 | Value *S, ///< The value to be casted |
| 5224 | Type *Ty, ///< The type to casted to |
| 5225 | const Twine &NameStr, ///< A name for the new instruction |
| 5226 | BasicBlock *InsertAtEnd ///< The block to insert the instruction into |
| 5227 | ); |
| 5228 | |
| 5229 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 5230 | static bool classof(const Instruction *I) { |
| 5231 | return I->getOpcode() == AddrSpaceCast; |
| 5232 | } |
| 5233 | static bool classof(const Value *V) { |
| 5234 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 5235 | } |
| 5236 | |
| 5237 | /// Gets the pointer operand. |
| 5238 | Value *getPointerOperand() { |
| 5239 | return getOperand(0); |
| 5240 | } |
| 5241 | |
| 5242 | /// Gets the pointer operand. |
| 5243 | const Value *getPointerOperand() const { |
| 5244 | return getOperand(0); |
| 5245 | } |
| 5246 | |
| 5247 | /// Gets the operand index of the pointer operand. |
| 5248 | static unsigned getPointerOperandIndex() { |
| 5249 | return 0U; |
| 5250 | } |
| 5251 | |
| 5252 | /// Returns the address space of the pointer operand. |
| 5253 | unsigned getSrcAddressSpace() const { |
| 5254 | return getPointerOperand()->getType()->getPointerAddressSpace(); |
| 5255 | } |
| 5256 | |
| 5257 | /// Returns the address space of the result. |
| 5258 | unsigned getDestAddressSpace() const { |
| 5259 | return getType()->getPointerAddressSpace(); |
| 5260 | } |
| 5261 | }; |
| 5262 | |
| 5263 | /// A helper function that returns the pointer operand of a load or store |
| 5264 | /// instruction. Returns nullptr if not load or store. |
| 5265 | inline const Value *getLoadStorePointerOperand(const Value *V) { |
| 5266 | if (auto *Load = dyn_cast<LoadInst>(V)) |
| 5267 | return Load->getPointerOperand(); |
| 5268 | if (auto *Store = dyn_cast<StoreInst>(V)) |
| 5269 | return Store->getPointerOperand(); |
| 5270 | return nullptr; |
| 5271 | } |
| 5272 | inline Value *getLoadStorePointerOperand(Value *V) { |
| 5273 | return const_cast<Value *>( |
| 5274 | getLoadStorePointerOperand(static_cast<const Value *>(V))); |
| 5275 | } |
| 5276 | |
| 5277 | /// A helper function that returns the pointer operand of a load, store |
| 5278 | /// or GEP instruction. Returns nullptr if not load, store, or GEP. |
| 5279 | inline const Value *getPointerOperand(const Value *V) { |
| 5280 | if (auto *Ptr = getLoadStorePointerOperand(V)) |
| 5281 | return Ptr; |
| 5282 | if (auto *Gep = dyn_cast<GetElementPtrInst>(V)) |
| 5283 | return Gep->getPointerOperand(); |
| 5284 | return nullptr; |
| 5285 | } |
| 5286 | inline Value *getPointerOperand(Value *V) { |
| 5287 | return const_cast<Value *>(getPointerOperand(static_cast<const Value *>(V))); |
| 5288 | } |
| 5289 | |
| 5290 | /// A helper function that returns the alignment of load or store instruction. |
| 5291 | inline Align getLoadStoreAlignment(Value *I) { |
| 5292 | assert((isa<LoadInst>(I) || isa<StoreInst>(I)) &&((void)0) |
| 5293 | "Expected Load or Store instruction")((void)0); |
| 5294 | if (auto *LI = dyn_cast<LoadInst>(I)) |
| 5295 | return LI->getAlign(); |
| 5296 | return cast<StoreInst>(I)->getAlign(); |
| 5297 | } |
| 5298 | |
| 5299 | /// A helper function that returns the address space of the pointer operand of |
| 5300 | /// load or store instruction. |
| 5301 | inline unsigned getLoadStoreAddressSpace(Value *I) { |
| 5302 | assert((isa<LoadInst>(I) || isa<StoreInst>(I)) &&((void)0) |
| 5303 | "Expected Load or Store instruction")((void)0); |
| 5304 | if (auto *LI = dyn_cast<LoadInst>(I)) |
| 5305 | return LI->getPointerAddressSpace(); |
| 5306 | return cast<StoreInst>(I)->getPointerAddressSpace(); |
| 5307 | } |
| 5308 | |
| 5309 | /// A helper function that returns the type of a load or store instruction. |
| 5310 | inline Type *getLoadStoreType(Value *I) { |
| 5311 | assert((isa<LoadInst>(I) || isa<StoreInst>(I)) &&((void)0) |
| 5312 | "Expected Load or Store instruction")((void)0); |
| 5313 | if (auto *LI = dyn_cast<LoadInst>(I)) |
| 5314 | return LI->getType(); |
| 5315 | return cast<StoreInst>(I)->getValueOperand()->getType(); |
| 5316 | } |
| 5317 | |
| 5318 | //===----------------------------------------------------------------------===// |
| 5319 | // FreezeInst Class |
| 5320 | //===----------------------------------------------------------------------===// |
| 5321 | |
| 5322 | /// This class represents a freeze function that returns random concrete |
| 5323 | /// value if an operand is either a poison value or an undef value |
| 5324 | class FreezeInst : public UnaryInstruction { |
| 5325 | protected: |
| 5326 | // Note: Instruction needs to be a friend here to call cloneImpl. |
| 5327 | friend class Instruction; |
| 5328 | |
| 5329 | /// Clone an identical FreezeInst |
| 5330 | FreezeInst *cloneImpl() const; |
| 5331 | |
| 5332 | public: |
| 5333 | explicit FreezeInst(Value *S, |
| 5334 | const Twine &NameStr = "", |
| 5335 | Instruction *InsertBefore = nullptr); |
| 5336 | FreezeInst(Value *S, const Twine &NameStr, BasicBlock *InsertAtEnd); |
| 5337 | |
| 5338 | // Methods for support type inquiry through isa, cast, and dyn_cast: |
| 5339 | static inline bool classof(const Instruction *I) { |
| 5340 | return I->getOpcode() == Freeze; |
| 5341 | } |
| 5342 | static inline bool classof(const Value *V) { |
| 5343 | return isa<Instruction>(V) && classof(cast<Instruction>(V)); |
| 5344 | } |
| 5345 | }; |
| 5346 | |
| 5347 | } // end namespace llvm |
| 5348 | |
| 5349 | #endif // LLVM_IR_INSTRUCTIONS_H |
| 1 | //===-- llvm/Support/Alignment.h - Useful alignment functions ---*- C++ -*-===// | |||
| 2 | // | |||
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | |||
| 4 | // See https://llvm.org/LICENSE.txt for license information. | |||
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | |||
| 6 | // | |||
| 7 | //===----------------------------------------------------------------------===// | |||
| 8 | // | |||
| 9 | // This file contains types to represent alignments. | |||
| 10 | // They are instrumented to guarantee some invariants are preserved and prevent | |||
| 11 | // invalid manipulations. | |||
| 12 | // | |||
| 13 | // - Align represents an alignment in bytes, it is always set and always a valid | |||
| 14 | // power of two, its minimum value is 1 which means no alignment requirements. | |||
| 15 | // | |||
| 16 | // - MaybeAlign is an optional type, it may be undefined or set. When it's set | |||
| 17 | // you can get the underlying Align type by using the getValue() method. | |||
| 18 | // | |||
| 19 | //===----------------------------------------------------------------------===// | |||
| 20 | ||||
| 21 | #ifndef LLVM_SUPPORT_ALIGNMENT_H_ | |||
| 22 | #define LLVM_SUPPORT_ALIGNMENT_H_ | |||
| 23 | ||||
| 24 | #include "llvm/ADT/Optional.h" | |||
| 25 | #include "llvm/Support/MathExtras.h" | |||
| 26 | #include <cassert> | |||
| 27 | #ifndef NDEBUG1 | |||
| 28 | #include <string> | |||
| 29 | #endif // NDEBUG | |||
| 30 | ||||
| 31 | namespace llvm { | |||
| 32 | ||||
| 33 | #define ALIGN_CHECK_ISPOSITIVE(decl) \ | |||
| 34 | assert(decl > 0 && (#decl " should be defined"))((void)0) | |||
| 35 | ||||
| 36 | /// This struct is a compact representation of a valid (non-zero power of two) | |||
| 37 | /// alignment. | |||
| 38 | /// It is suitable for use as static global constants. | |||
| 39 | struct Align { | |||
| 40 | private: | |||
| 41 | uint8_t ShiftValue = 0; /// The log2 of the required alignment. | |||
| 42 | /// ShiftValue is less than 64 by construction. | |||
| 43 | ||||
| 44 | friend struct MaybeAlign; | |||
| 45 | friend unsigned Log2(Align); | |||
| 46 | friend bool operator==(Align Lhs, Align Rhs); | |||
| 47 | friend bool operator!=(Align Lhs, Align Rhs); | |||
| 48 | friend bool operator<=(Align Lhs, Align Rhs); | |||
| 49 | friend bool operator>=(Align Lhs, Align Rhs); | |||
| 50 | friend bool operator<(Align Lhs, Align Rhs); | |||
| 51 | friend bool operator>(Align Lhs, Align Rhs); | |||
| 52 | friend unsigned encode(struct MaybeAlign A); | |||
| 53 | friend struct MaybeAlign decodeMaybeAlign(unsigned Value); | |||
| 54 | ||||
| 55 | /// A trivial type to allow construction of constexpr Align. | |||
| 56 | /// This is currently needed to workaround a bug in GCC 5.3 which prevents | |||
| 57 | /// definition of constexpr assign operators. | |||
| 58 | /// https://stackoverflow.com/questions/46756288/explicitly-defaulted-function-cannot-be-declared-as-constexpr-because-the-implic | |||
| 59 | /// FIXME: Remove this, make all assign operators constexpr and introduce user | |||
| 60 | /// defined literals when we don't have to support GCC 5.3 anymore. | |||
| 61 | /// https://llvm.org/docs/GettingStarted.html#getting-a-modern-host-c-toolchain | |||
| 62 | struct LogValue { | |||
| 63 | uint8_t Log; | |||
| 64 | }; | |||
| 65 | ||||
| 66 | public: | |||
| 67 | /// Default is byte-aligned. | |||
| 68 | constexpr Align() = default; | |||
| 69 | /// Do not perform checks in case of copy/move construct/assign, because the | |||
| 70 | /// checks have been performed when building `Other`. | |||
| 71 | constexpr Align(const Align &Other) = default; | |||
| 72 | constexpr Align(Align &&Other) = default; | |||
| 73 | Align &operator=(const Align &Other) = default; | |||
| 74 | Align &operator=(Align &&Other) = default; | |||
| 75 | ||||
| 76 | explicit Align(uint64_t Value) { | |||
| 77 | assert(Value > 0 && "Value must not be 0")((void)0); | |||
| 78 | assert(llvm::isPowerOf2_64(Value) && "Alignment is not a power of 2")((void)0); | |||
| 79 | ShiftValue = Log2_64(Value); | |||
| 80 | assert(ShiftValue < 64 && "Broken invariant")((void)0); | |||
| 81 | } | |||
| 82 | ||||
| 83 | /// This is a hole in the type system and should not be abused. | |||
| 84 | /// Needed to interact with C for instance. | |||
| 85 | uint64_t value() const { return uint64_t(1) << ShiftValue; } | |||
| ||||
| 86 | ||||
| 87 | /// Allow constructions of constexpr Align. | |||
| 88 | template <size_t kValue> constexpr static LogValue Constant() { | |||
| 89 | return LogValue{static_cast<uint8_t>(CTLog2<kValue>())}; | |||
| 90 | } | |||
| 91 | ||||
| 92 | /// Allow constructions of constexpr Align from types. | |||
| 93 | /// Compile time equivalent to Align(alignof(T)). | |||
| 94 | template <typename T> constexpr static LogValue Of() { | |||
| 95 | return Constant<std::alignment_of<T>::value>(); | |||
| 96 | } | |||
| 97 | ||||
| 98 | /// Constexpr constructor from LogValue type. | |||
| 99 | constexpr Align(LogValue CA) : ShiftValue(CA.Log) {} | |||
| 100 | }; | |||
| 101 | ||||
| 102 | /// Treats the value 0 as a 1, so Align is always at least 1. | |||
| 103 | inline Align assumeAligned(uint64_t Value) { | |||
| 104 | return Value ? Align(Value) : Align(); | |||
| 105 | } | |||
| 106 | ||||
| 107 | /// This struct is a compact representation of a valid (power of two) or | |||
| 108 | /// undefined (0) alignment. | |||
| 109 | struct MaybeAlign : public llvm::Optional<Align> { | |||
| 110 | private: | |||
| 111 | using UP = llvm::Optional<Align>; | |||
| 112 | ||||
| 113 | public: | |||
| 114 | /// Default is undefined. | |||
| 115 | MaybeAlign() = default; | |||
| 116 | /// Do not perform checks in case of copy/move construct/assign, because the | |||
| 117 | /// checks have been performed when building `Other`. | |||
| 118 | MaybeAlign(const MaybeAlign &Other) = default; | |||
| 119 | MaybeAlign &operator=(const MaybeAlign &Other) = default; | |||
| 120 | MaybeAlign(MaybeAlign &&Other) = default; | |||
| 121 | MaybeAlign &operator=(MaybeAlign &&Other) = default; | |||
| 122 | ||||
| 123 | /// Use llvm::Optional<Align> constructor. | |||
| 124 | using UP::UP; | |||
| 125 | ||||
| 126 | explicit MaybeAlign(uint64_t Value) { | |||
| 127 | assert((Value == 0 || llvm::isPowerOf2_64(Value)) &&((void)0) | |||
| 128 | "Alignment is neither 0 nor a power of 2")((void)0); | |||
| 129 | if (Value) | |||
| 130 | emplace(Value); | |||
| 131 | } | |||
| 132 | ||||
| 133 | /// For convenience, returns a valid alignment or 1 if undefined. | |||
| 134 | Align valueOrOne() const { return hasValue() ? getValue() : Align(); } | |||
| 135 | }; | |||
| 136 | ||||
| 137 | /// Checks that SizeInBytes is a multiple of the alignment. | |||
| 138 | inline bool isAligned(Align Lhs, uint64_t SizeInBytes) { | |||
| 139 | return SizeInBytes % Lhs.value() == 0; | |||
| 140 | } | |||
| 141 | ||||
| 142 | /// Checks that Addr is a multiple of the alignment. | |||
| 143 | inline bool isAddrAligned(Align Lhs, const void *Addr) { | |||
| 144 | return isAligned(Lhs, reinterpret_cast<uintptr_t>(Addr)); | |||
| 145 | } | |||
| 146 | ||||
| 147 | /// Returns a multiple of A needed to store `Size` bytes. | |||
| 148 | inline uint64_t alignTo(uint64_t Size, Align A) { | |||
| 149 | const uint64_t Value = A.value(); | |||
| 150 | // The following line is equivalent to `(Size + Value - 1) / Value * Value`. | |||
| 151 | ||||
| 152 | // The division followed by a multiplication can be thought of as a right | |||
| 153 | // shift followed by a left shift which zeros out the extra bits produced in | |||
| 154 | // the bump; `~(Value - 1)` is a mask where all those bits being zeroed out | |||
| 155 | // are just zero. | |||
| 156 | ||||
| 157 | // Most compilers can generate this code but the pattern may be missed when | |||
| 158 | // multiple functions gets inlined. | |||
| 159 | return (Size + Value - 1) & ~(Value - 1U); | |||
| 160 | } | |||
| 161 | ||||
| 162 | /// If non-zero \p Skew is specified, the return value will be a minimal integer | |||
| 163 | /// that is greater than or equal to \p Size and equal to \p A * N + \p Skew for | |||
| 164 | /// some integer N. If \p Skew is larger than \p A, its value is adjusted to '\p | |||
| 165 | /// Skew mod \p A'. | |||
| 166 | /// | |||
| 167 | /// Examples: | |||
| 168 | /// \code | |||
| 169 | /// alignTo(5, Align(8), 7) = 7 | |||
| 170 | /// alignTo(17, Align(8), 1) = 17 | |||
| 171 | /// alignTo(~0LL, Align(8), 3) = 3 | |||
| 172 | /// \endcode | |||
| 173 | inline uint64_t alignTo(uint64_t Size, Align A, uint64_t Skew) { | |||
| 174 | const uint64_t Value = A.value(); | |||
| 175 | Skew %= Value; | |||
| 176 | return ((Size + Value - 1 - Skew) & ~(Value - 1U)) + Skew; | |||
| 177 | } | |||
| 178 | ||||
| 179 | /// Returns a multiple of A needed to store `Size` bytes. | |||
| 180 | /// Returns `Size` if current alignment is undefined. | |||
| 181 | inline uint64_t alignTo(uint64_t Size, MaybeAlign A) { | |||
| 182 | return A ? alignTo(Size, A.getValue()) : Size; | |||
| 183 | } | |||
| 184 | ||||
| 185 | /// Aligns `Addr` to `Alignment` bytes, rounding up. | |||
| 186 | inline uintptr_t alignAddr(const void *Addr, Align Alignment) { | |||
| 187 | uintptr_t ArithAddr = reinterpret_cast<uintptr_t>(Addr); | |||
| 188 | assert(static_cast<uintptr_t>(ArithAddr + Alignment.value() - 1) >=((void)0) | |||
| 189 | ArithAddr &&((void)0) | |||
| 190 | "Overflow")((void)0); | |||
| 191 | return alignTo(ArithAddr, Alignment); | |||
| 192 | } | |||
| 193 | ||||
| 194 | /// Returns the offset to the next integer (mod 2**64) that is greater than | |||
| 195 | /// or equal to \p Value and is a multiple of \p Align. | |||
| 196 | inline uint64_t offsetToAlignment(uint64_t Value, Align Alignment) { | |||
| 197 | return alignTo(Value, Alignment) - Value; | |||
| 198 | } | |||
| 199 | ||||
| 200 | /// Returns the necessary adjustment for aligning `Addr` to `Alignment` | |||
| 201 | /// bytes, rounding up. | |||
| 202 | inline uint64_t offsetToAlignedAddr(const void *Addr, Align Alignment) { | |||
| 203 | return offsetToAlignment(reinterpret_cast<uintptr_t>(Addr), Alignment); | |||
| 204 | } | |||
| 205 | ||||
| 206 | /// Returns the log2 of the alignment. | |||
| 207 | inline unsigned Log2(Align A) { return A.ShiftValue; } | |||
| 208 | ||||
| 209 | /// Returns the alignment that satisfies both alignments. | |||
| 210 | /// Same semantic as MinAlign. | |||
| 211 | inline Align commonAlignment(Align A, Align B) { return std::min(A, B); } | |||
| 212 | ||||
| 213 | /// Returns the alignment that satisfies both alignments. | |||
| 214 | /// Same semantic as MinAlign. | |||
| 215 | inline Align commonAlignment(Align A, uint64_t Offset) { | |||
| 216 | return Align(MinAlign(A.value(), Offset)); | |||
| 217 | } | |||
| 218 | ||||
| 219 | /// Returns the alignment that satisfies both alignments. | |||
| 220 | /// Same semantic as MinAlign. | |||
| 221 | inline MaybeAlign commonAlignment(MaybeAlign A, MaybeAlign B) { | |||
| 222 | return A && B ? commonAlignment(*A, *B) : A ? A : B; | |||
| 223 | } | |||
| 224 | ||||
| 225 | /// Returns the alignment that satisfies both alignments. | |||
| 226 | /// Same semantic as MinAlign. | |||
| 227 | inline MaybeAlign commonAlignment(MaybeAlign A, uint64_t Offset) { | |||
| 228 | return MaybeAlign(MinAlign((*A).value(), Offset)); | |||
| 229 | } | |||
| 230 | ||||
| 231 | /// Returns a representation of the alignment that encodes undefined as 0. | |||
| 232 | inline unsigned encode(MaybeAlign A) { return A ? A->ShiftValue + 1 : 0; } | |||
| 233 | ||||
| 234 | /// Dual operation of the encode function above. | |||
| 235 | inline MaybeAlign decodeMaybeAlign(unsigned Value) { | |||
| 236 | if (Value == 0) | |||
| 237 | return MaybeAlign(); | |||
| 238 | Align Out; | |||
| 239 | Out.ShiftValue = Value - 1; | |||
| 240 | return Out; | |||
| 241 | } | |||
| 242 | ||||
| 243 | /// Returns a representation of the alignment, the encoded value is positive by | |||
| 244 | /// definition. | |||
| 245 | inline unsigned encode(Align A) { return encode(MaybeAlign(A)); } | |||
| 246 | ||||
| 247 | /// Comparisons between Align and scalars. Rhs must be positive. | |||
| 248 | inline bool operator==(Align Lhs, uint64_t Rhs) { | |||
| 249 | ALIGN_CHECK_ISPOSITIVE(Rhs); | |||
| 250 | return Lhs.value() == Rhs; | |||
| 251 | } | |||
| 252 | inline bool operator!=(Align Lhs, uint64_t Rhs) { | |||
| 253 | ALIGN_CHECK_ISPOSITIVE(Rhs); | |||
| 254 | return Lhs.value() != Rhs; | |||
| 255 | } | |||
| 256 | inline bool operator<=(Align Lhs, uint64_t Rhs) { | |||
| 257 | ALIGN_CHECK_ISPOSITIVE(Rhs); | |||
| 258 | return Lhs.value() <= Rhs; | |||
| 259 | } | |||
| 260 | inline bool operator>=(Align Lhs, uint64_t Rhs) { | |||
| 261 | ALIGN_CHECK_ISPOSITIVE(Rhs); | |||
| 262 | return Lhs.value() >= Rhs; | |||
| 263 | } | |||
| 264 | inline bool operator<(Align Lhs, uint64_t Rhs) { | |||
| 265 | ALIGN_CHECK_ISPOSITIVE(Rhs); | |||
| 266 | return Lhs.value() < Rhs; | |||
| 267 | } | |||
| 268 | inline bool operator>(Align Lhs, uint64_t Rhs) { | |||
| 269 | ALIGN_CHECK_ISPOSITIVE(Rhs); | |||
| 270 | return Lhs.value() > Rhs; | |||
| 271 | } | |||
| 272 | ||||
| 273 | /// Comparisons between MaybeAlign and scalars. | |||
| 274 | inline bool operator==(MaybeAlign Lhs, uint64_t Rhs) { | |||
| 275 | return Lhs ? (*Lhs).value() == Rhs : Rhs == 0; | |||
| 276 | } | |||
| 277 | inline bool operator!=(MaybeAlign Lhs, uint64_t Rhs) { | |||
| 278 | return Lhs ? (*Lhs).value() != Rhs : Rhs != 0; | |||
| 279 | } | |||
| 280 | ||||
| 281 | /// Comparisons operators between Align. | |||
| 282 | inline bool operator==(Align Lhs, Align Rhs) { | |||
| 283 | return Lhs.ShiftValue == Rhs.ShiftValue; | |||
| 284 | } | |||
| 285 | inline bool operator!=(Align Lhs, Align Rhs) { | |||
| 286 | return Lhs.ShiftValue != Rhs.ShiftValue; | |||
| 287 | } | |||
| 288 | inline bool operator<=(Align Lhs, Align Rhs) { | |||
| 289 | return Lhs.ShiftValue <= Rhs.ShiftValue; | |||
| 290 | } | |||
| 291 | inline bool operator>=(Align Lhs, Align Rhs) { | |||
| 292 | return Lhs.ShiftValue >= Rhs.ShiftValue; | |||
| 293 | } | |||
| 294 | inline bool operator<(Align Lhs, Align Rhs) { | |||
| 295 | return Lhs.ShiftValue < Rhs.ShiftValue; | |||
| 296 | } | |||
| 297 | inline bool operator>(Align Lhs, Align Rhs) { | |||
| 298 | return Lhs.ShiftValue > Rhs.ShiftValue; | |||
| 299 | } | |||
| 300 | ||||
| 301 | // Don't allow relational comparisons with MaybeAlign. | |||
| 302 | bool operator<=(Align Lhs, MaybeAlign Rhs) = delete; | |||
| 303 | bool operator>=(Align Lhs, MaybeAlign Rhs) = delete; | |||
| 304 | bool operator<(Align Lhs, MaybeAlign Rhs) = delete; | |||
| 305 | bool operator>(Align Lhs, MaybeAlign Rhs) = delete; | |||
| 306 | ||||
| 307 | bool operator<=(MaybeAlign Lhs, Align Rhs) = delete; | |||
| 308 | bool operator>=(MaybeAlign Lhs, Align Rhs) = delete; | |||
| 309 | bool operator<(MaybeAlign Lhs, Align Rhs) = delete; | |||
| 310 | bool operator>(MaybeAlign Lhs, Align Rhs) = delete; | |||
| 311 | ||||
| 312 | bool operator<=(MaybeAlign Lhs, MaybeAlign Rhs) = delete; | |||
| 313 | bool operator>=(MaybeAlign Lhs, MaybeAlign Rhs) = delete; | |||
| 314 | bool operator<(MaybeAlign Lhs, MaybeAlign Rhs) = delete; | |||
| 315 | bool operator>(MaybeAlign Lhs, MaybeAlign Rhs) = delete; | |||
| 316 | ||||
| 317 | inline Align operator*(Align Lhs, uint64_t Rhs) { | |||
| 318 | assert(Rhs > 0 && "Rhs must be positive")((void)0); | |||
| 319 | return Align(Lhs.value() * Rhs); | |||
| 320 | } | |||
| 321 | ||||
| 322 | inline MaybeAlign operator*(MaybeAlign Lhs, uint64_t Rhs) { | |||
| 323 | assert(Rhs > 0 && "Rhs must be positive")((void)0); | |||
| 324 | return Lhs ? Lhs.getValue() * Rhs : MaybeAlign(); | |||
| 325 | } | |||
| 326 | ||||
| 327 | inline Align operator/(Align Lhs, uint64_t Divisor) { | |||
| 328 | assert(llvm::isPowerOf2_64(Divisor) &&((void)0) | |||
| 329 | "Divisor must be positive and a power of 2")((void)0); | |||
| 330 | assert(Lhs != 1 && "Can't halve byte alignment")((void)0); | |||
| 331 | return Align(Lhs.value() / Divisor); | |||
| 332 | } | |||
| 333 | ||||
| 334 | inline MaybeAlign operator/(MaybeAlign Lhs, uint64_t Divisor) { | |||
| 335 | assert(llvm::isPowerOf2_64(Divisor) &&((void)0) | |||
| 336 | "Divisor must be positive and a power of 2")((void)0); | |||
| 337 | return Lhs ? Lhs.getValue() / Divisor : MaybeAlign(); | |||
| 338 | } | |||
| 339 | ||||
| 340 | inline Align max(MaybeAlign Lhs, Align Rhs) { | |||
| 341 | return Lhs && *Lhs > Rhs ? *Lhs : Rhs; | |||
| 342 | } | |||
| 343 | ||||
| 344 | inline Align max(Align Lhs, MaybeAlign Rhs) { | |||
| 345 | return Rhs && *Rhs > Lhs ? *Rhs : Lhs; | |||
| 346 | } | |||
| 347 | ||||
| 348 | #ifndef NDEBUG1 | |||
| 349 | // For usage in LLVM_DEBUG macros. | |||
| 350 | inline std::string DebugStr(const Align &A) { | |||
| 351 | return std::to_string(A.value()); | |||
| 352 | } | |||
| 353 | // For usage in LLVM_DEBUG macros. | |||
| 354 | inline std::string DebugStr(const MaybeAlign &MA) { | |||
| 355 | if (MA) | |||
| 356 | return std::to_string(MA->value()); | |||
| 357 | return "None"; | |||
| 358 | } | |||
| 359 | #endif // NDEBUG | |||
| 360 | ||||
| 361 | #undef ALIGN_CHECK_ISPOSITIVE | |||
| 362 | ||||
| 363 | } // namespace llvm | |||
| 364 | ||||
| 365 | #endif // LLVM_SUPPORT_ALIGNMENT_H_ |
| 1 | //===-- llvm/Support/MathExtras.h - Useful math functions -------*- C++ -*-===// |
| 2 | // |
| 3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | // See https://llvm.org/LICENSE.txt for license information. |
| 5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | // |
| 7 | //===----------------------------------------------------------------------===// |
| 8 | // |
| 9 | // This file contains some functions that are useful for math stuff. |
| 10 | // |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | #ifndef LLVM_SUPPORT_MATHEXTRAS_H |
| 14 | #define LLVM_SUPPORT_MATHEXTRAS_H |
| 15 | |
| 16 | #include "llvm/Support/Compiler.h" |
| 17 | #include <cassert> |
| 18 | #include <climits> |
| 19 | #include <cmath> |
| 20 | #include <cstdint> |
| 21 | #include <cstring> |
| 22 | #include <limits> |
| 23 | #include <type_traits> |
| 24 | |
| 25 | #ifdef __ANDROID_NDK__ |
| 26 | #include <android/api-level.h> |
| 27 | #endif |
| 28 | |
| 29 | #ifdef _MSC_VER |
| 30 | // Declare these intrinsics manually rather including intrin.h. It's very |
| 31 | // expensive, and MathExtras.h is popular. |
| 32 | // #include <intrin.h> |
| 33 | extern "C" { |
| 34 | unsigned char _BitScanForward(unsigned long *_Index, unsigned long _Mask); |
| 35 | unsigned char _BitScanForward64(unsigned long *_Index, unsigned __int64 _Mask); |
| 36 | unsigned char _BitScanReverse(unsigned long *_Index, unsigned long _Mask); |
| 37 | unsigned char _BitScanReverse64(unsigned long *_Index, unsigned __int64 _Mask); |
| 38 | } |
| 39 | #endif |
| 40 | |
| 41 | namespace llvm { |
| 42 | |
| 43 | /// The behavior an operation has on an input of 0. |
| 44 | enum ZeroBehavior { |
| 45 | /// The returned value is undefined. |
| 46 | ZB_Undefined, |
| 47 | /// The returned value is numeric_limits<T>::max() |
| 48 | ZB_Max, |
| 49 | /// The returned value is numeric_limits<T>::digits |
| 50 | ZB_Width |
| 51 | }; |
| 52 | |
| 53 | /// Mathematical constants. |
| 54 | namespace numbers { |
| 55 | // TODO: Track C++20 std::numbers. |
| 56 | // TODO: Favor using the hexadecimal FP constants (requires C++17). |
| 57 | constexpr double e = 2.7182818284590452354, // (0x1.5bf0a8b145749P+1) https://oeis.org/A001113 |
| 58 | egamma = .57721566490153286061, // (0x1.2788cfc6fb619P-1) https://oeis.org/A001620 |
| 59 | ln2 = .69314718055994530942, // (0x1.62e42fefa39efP-1) https://oeis.org/A002162 |
| 60 | ln10 = 2.3025850929940456840, // (0x1.24bb1bbb55516P+1) https://oeis.org/A002392 |
| 61 | log2e = 1.4426950408889634074, // (0x1.71547652b82feP+0) |
| 62 | log10e = .43429448190325182765, // (0x1.bcb7b1526e50eP-2) |
| 63 | pi = 3.1415926535897932385, // (0x1.921fb54442d18P+1) https://oeis.org/A000796 |
| 64 | inv_pi = .31830988618379067154, // (0x1.45f306bc9c883P-2) https://oeis.org/A049541 |
| 65 | sqrtpi = 1.7724538509055160273, // (0x1.c5bf891b4ef6bP+0) https://oeis.org/A002161 |
| 66 | inv_sqrtpi = .56418958354775628695, // (0x1.20dd750429b6dP-1) https://oeis.org/A087197 |
| 67 | sqrt2 = 1.4142135623730950488, // (0x1.6a09e667f3bcdP+0) https://oeis.org/A00219 |
| 68 | inv_sqrt2 = .70710678118654752440, // (0x1.6a09e667f3bcdP-1) |
| 69 | sqrt3 = 1.7320508075688772935, // (0x1.bb67ae8584caaP+0) https://oeis.org/A002194 |
| 70 | inv_sqrt3 = .57735026918962576451, // (0x1.279a74590331cP-1) |
| 71 | phi = 1.6180339887498948482; // (0x1.9e3779b97f4a8P+0) https://oeis.org/A001622 |
| 72 | constexpr float ef = 2.71828183F, // (0x1.5bf0a8P+1) https://oeis.org/A001113 |
| 73 | egammaf = .577215665F, // (0x1.2788d0P-1) https://oeis.org/A001620 |
| 74 | ln2f = .693147181F, // (0x1.62e430P-1) https://oeis.org/A002162 |
| 75 | ln10f = 2.30258509F, // (0x1.26bb1cP+1) https://oeis.org/A002392 |
| 76 | log2ef = 1.44269504F, // (0x1.715476P+0) |
| 77 | log10ef = .434294482F, // (0x1.bcb7b2P-2) |
| 78 | pif = 3.14159265F, // (0x1.921fb6P+1) https://oeis.org/A000796 |
| 79 | inv_pif = .318309886F, // (0x1.45f306P-2) https://oeis.org/A049541 |
| 80 | sqrtpif = 1.77245385F, // (0x1.c5bf8aP+0) https://oeis.org/A002161 |
| 81 | inv_sqrtpif = .564189584F, // (0x1.20dd76P-1) https://oeis.org/A087197 |
| 82 | sqrt2f = 1.41421356F, // (0x1.6a09e6P+0) https://oeis.org/A002193 |
| 83 | inv_sqrt2f = .707106781F, // (0x1.6a09e6P-1) |
| 84 | sqrt3f = 1.73205081F, // (0x1.bb67aeP+0) https://oeis.org/A002194 |
| 85 | inv_sqrt3f = .577350269F, // (0x1.279a74P-1) |
| 86 | phif = 1.61803399F; // (0x1.9e377aP+0) https://oeis.org/A001622 |
| 87 | } // namespace numbers |
| 88 | |
| 89 | namespace detail { |
| 90 | template <typename T, std::size_t SizeOfT> struct TrailingZerosCounter { |
| 91 | static unsigned count(T Val, ZeroBehavior) { |
| 92 | if (!Val) |
| 93 | return std::numeric_limits<T>::digits; |
| 94 | if (Val & 0x1) |
| 95 | return 0; |
| 96 | |
| 97 | // Bisection method. |
| 98 | unsigned ZeroBits = 0; |
| 99 | T Shift = std::numeric_limits<T>::digits >> 1; |
| 100 | T Mask = std::numeric_limits<T>::max() >> Shift; |
| 101 | while (Shift) { |
| 102 | if ((Val & Mask) == 0) { |
| 103 | Val >>= Shift; |
| 104 | ZeroBits |= Shift; |
| 105 | } |
| 106 | Shift >>= 1; |
| 107 | Mask >>= Shift; |
| 108 | } |
| 109 | return ZeroBits; |
| 110 | } |
| 111 | }; |
| 112 | |
| 113 | #if defined(__GNUC__4) || defined(_MSC_VER) |
| 114 | template <typename T> struct TrailingZerosCounter<T, 4> { |
| 115 | static unsigned count(T Val, ZeroBehavior ZB) { |
| 116 | if (ZB != ZB_Undefined && Val == 0) |
| 117 | return 32; |
| 118 | |
| 119 | #if __has_builtin(__builtin_ctz)1 || defined(__GNUC__4) |
| 120 | return __builtin_ctz(Val); |
| 121 | #elif defined(_MSC_VER) |
| 122 | unsigned long Index; |
| 123 | _BitScanForward(&Index, Val); |
| 124 | return Index; |
| 125 | #endif |
| 126 | } |
| 127 | }; |
| 128 | |
| 129 | #if !defined(_MSC_VER) || defined(_M_X64) |
| 130 | template <typename T> struct TrailingZerosCounter<T, 8> { |
| 131 | static unsigned count(T Val, ZeroBehavior ZB) { |
| 132 | if (ZB != ZB_Undefined && Val == 0) |
| 133 | return 64; |
| 134 | |
| 135 | #if __has_builtin(__builtin_ctzll)1 || defined(__GNUC__4) |
| 136 | return __builtin_ctzll(Val); |
| 137 | #elif defined(_MSC_VER) |
| 138 | unsigned long Index; |
| 139 | _BitScanForward64(&Index, Val); |
| 140 | return Index; |
| 141 | #endif |
| 142 | } |
| 143 | }; |
| 144 | #endif |
| 145 | #endif |
| 146 | } // namespace detail |
| 147 | |
| 148 | /// Count number of 0's from the least significant bit to the most |
| 149 | /// stopping at the first 1. |
| 150 | /// |
| 151 | /// Only unsigned integral types are allowed. |
| 152 | /// |
| 153 | /// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are |
| 154 | /// valid arguments. |
| 155 | template <typename T> |
| 156 | unsigned countTrailingZeros(T Val, ZeroBehavior ZB = ZB_Width) { |
| 157 | static_assert(std::numeric_limits<T>::is_integer && |
| 158 | !std::numeric_limits<T>::is_signed, |
| 159 | "Only unsigned integral types are allowed."); |
| 160 | return llvm::detail::TrailingZerosCounter<T, sizeof(T)>::count(Val, ZB); |
| 161 | } |
| 162 | |
| 163 | namespace detail { |
| 164 | template <typename T, std::size_t SizeOfT> struct LeadingZerosCounter { |
| 165 | static unsigned count(T Val, ZeroBehavior) { |
| 166 | if (!Val) |
| 167 | return std::numeric_limits<T>::digits; |
| 168 | |
| 169 | // Bisection method. |
| 170 | unsigned ZeroBits = 0; |
| 171 | for (T Shift = std::numeric_limits<T>::digits >> 1; Shift; Shift >>= 1) { |
| 172 | T Tmp = Val >> Shift; |
| 173 | if (Tmp) |
| 174 | Val = Tmp; |
| 175 | else |
| 176 | ZeroBits |= Shift; |
| 177 | } |
| 178 | return ZeroBits; |
| 179 | } |
| 180 | }; |
| 181 | |
| 182 | #if defined(__GNUC__4) || defined(_MSC_VER) |
| 183 | template <typename T> struct LeadingZerosCounter<T, 4> { |
| 184 | static unsigned count(T Val, ZeroBehavior ZB) { |
| 185 | if (ZB != ZB_Undefined && Val == 0) |
| 186 | return 32; |
| 187 | |
| 188 | #if __has_builtin(__builtin_clz)1 || defined(__GNUC__4) |
| 189 | return __builtin_clz(Val); |
| 190 | #elif defined(_MSC_VER) |
| 191 | unsigned long Index; |
| 192 | _BitScanReverse(&Index, Val); |
| 193 | return Index ^ 31; |
| 194 | #endif |
| 195 | } |
| 196 | }; |
| 197 | |
| 198 | #if !defined(_MSC_VER) || defined(_M_X64) |
| 199 | template <typename T> struct LeadingZerosCounter<T, 8> { |
| 200 | static unsigned count(T Val, ZeroBehavior ZB) { |
| 201 | if (ZB != ZB_Undefined && Val == 0) |
| 202 | return 64; |
| 203 | |
| 204 | #if __has_builtin(__builtin_clzll)1 || defined(__GNUC__4) |
| 205 | return __builtin_clzll(Val); |
| 206 | #elif defined(_MSC_VER) |
| 207 | unsigned long Index; |
| 208 | _BitScanReverse64(&Index, Val); |
| 209 | return Index ^ 63; |
| 210 | #endif |
| 211 | } |
| 212 | }; |
| 213 | #endif |
| 214 | #endif |
| 215 | } // namespace detail |
| 216 | |
| 217 | /// Count number of 0's from the most significant bit to the least |
| 218 | /// stopping at the first 1. |
| 219 | /// |
| 220 | /// Only unsigned integral types are allowed. |
| 221 | /// |
| 222 | /// \param ZB the behavior on an input of 0. Only ZB_Width and ZB_Undefined are |
| 223 | /// valid arguments. |
| 224 | template <typename T> |
| 225 | unsigned countLeadingZeros(T Val, ZeroBehavior ZB = ZB_Width) { |
| 226 | static_assert(std::numeric_limits<T>::is_integer && |
| 227 | !std::numeric_limits<T>::is_signed, |
| 228 | "Only unsigned integral types are allowed."); |
| 229 | return llvm::detail::LeadingZerosCounter<T, sizeof(T)>::count(Val, ZB); |
| 230 | } |
| 231 | |
| 232 | /// Get the index of the first set bit starting from the least |
| 233 | /// significant bit. |
| 234 | /// |
| 235 | /// Only unsigned integral types are allowed. |
| 236 | /// |
| 237 | /// \param ZB the behavior on an input of 0. Only ZB_Max and ZB_Undefined are |
| 238 | /// valid arguments. |
| 239 | template <typename T> T findFirstSet(T Val, ZeroBehavior ZB = ZB_Max) { |
| 240 | if (ZB == ZB_Max && Val == 0) |
| 241 | return std::numeric_limits<T>::max(); |
| 242 | |
| 243 | return countTrailingZeros(Val, ZB_Undefined); |
| 244 | } |
| 245 | |
| 246 | /// Create a bitmask with the N right-most bits set to 1, and all other |
| 247 | /// bits set to 0. Only unsigned types are allowed. |
| 248 | template <typename T> T maskTrailingOnes(unsigned N) { |
| 249 | static_assert(std::is_unsigned<T>::value, "Invalid type!"); |
| 250 | const unsigned Bits = CHAR_BIT8 * sizeof(T); |
| 251 | assert(N <= Bits && "Invalid bit index")((void)0); |
| 252 | return N == 0 ? 0 : (T(-1) >> (Bits - N)); |
| 253 | } |
| 254 | |
| 255 | /// Create a bitmask with the N left-most bits set to 1, and all other |
| 256 | /// bits set to 0. Only unsigned types are allowed. |
| 257 | template <typename T> T maskLeadingOnes(unsigned N) { |
| 258 | return ~maskTrailingOnes<T>(CHAR_BIT8 * sizeof(T) - N); |
| 259 | } |
| 260 | |
| 261 | /// Create a bitmask with the N right-most bits set to 0, and all other |
| 262 | /// bits set to 1. Only unsigned types are allowed. |
| 263 | template <typename T> T maskTrailingZeros(unsigned N) { |
| 264 | return maskLeadingOnes<T>(CHAR_BIT8 * sizeof(T) - N); |
| 265 | } |
| 266 | |
| 267 | /// Create a bitmask with the N left-most bits set to 0, and all other |
| 268 | /// bits set to 1. Only unsigned types are allowed. |
| 269 | template <typename T> T maskLeadingZeros(unsigned N) { |
| 270 | return maskTrailingOnes<T>(CHAR_BIT8 * sizeof(T) - N); |
| 271 | } |
| 272 | |
| 273 | /// Get the index of the last set bit starting from the least |
| 274 | /// significant bit. |
| 275 | /// |
| 276 | /// Only unsigned integral types are allowed. |
| 277 | /// |
| 278 | /// \param ZB the behavior on an input of 0. Only ZB_Max and ZB_Undefined are |
| 279 | /// valid arguments. |
| 280 | template <typename T> T findLastSet(T Val, ZeroBehavior ZB = ZB_Max) { |
| 281 | if (ZB == ZB_Max && Val == 0) |
| 282 | return std::numeric_limits<T>::max(); |
| 283 | |
| 284 | // Use ^ instead of - because both gcc and llvm can remove the associated ^ |
| 285 | // in the __builtin_clz intrinsic on x86. |
| 286 | return countLeadingZeros(Val, ZB_Undefined) ^ |
| 287 | (std::numeric_limits<T>::digits - 1); |
| 288 | } |
| 289 | |
| 290 | /// Macro compressed bit reversal table for 256 bits. |
| 291 | /// |
| 292 | /// http://graphics.stanford.edu/~seander/bithacks.html#BitReverseTable |
| 293 | static const unsigned char BitReverseTable256[256] = { |
| 294 | #define R2(n) n, n + 2 * 64, n + 1 * 64, n + 3 * 64 |
| 295 | #define R4(n) R2(n), R2(n + 2 * 16), R2(n + 1 * 16), R2(n + 3 * 16) |
| 296 | #define R6(n) R4(n), R4(n + 2 * 4), R4(n + 1 * 4), R4(n + 3 * 4) |
| 297 | R6(0), R6(2), R6(1), R6(3) |
| 298 | #undef R2 |
| 299 | #undef R4 |
| 300 | #undef R6 |
| 301 | }; |
| 302 | |
| 303 | /// Reverse the bits in \p Val. |
| 304 | template <typename T> |
| 305 | T reverseBits(T Val) { |
| 306 | unsigned char in[sizeof(Val)]; |
| 307 | unsigned char out[sizeof(Val)]; |
| 308 | std::memcpy(in, &Val, sizeof(Val)); |
| 309 | for (unsigned i = 0; i < sizeof(Val); ++i) |
| 310 | out[(sizeof(Val) - i) - 1] = BitReverseTable256[in[i]]; |
| 311 | std::memcpy(&Val, out, sizeof(Val)); |
| 312 | return Val; |
| 313 | } |
| 314 | |
| 315 | #if __has_builtin(__builtin_bitreverse8)1 |
| 316 | template<> |
| 317 | inline uint8_t reverseBits<uint8_t>(uint8_t Val) { |
| 318 | return __builtin_bitreverse8(Val); |
| 319 | } |
| 320 | #endif |
| 321 | |
| 322 | #if __has_builtin(__builtin_bitreverse16)1 |
| 323 | template<> |
| 324 | inline uint16_t reverseBits<uint16_t>(uint16_t Val) { |
| 325 | return __builtin_bitreverse16(Val); |
| 326 | } |
| 327 | #endif |
| 328 | |
| 329 | #if __has_builtin(__builtin_bitreverse32)1 |
| 330 | template<> |
| 331 | inline uint32_t reverseBits<uint32_t>(uint32_t Val) { |
| 332 | return __builtin_bitreverse32(Val); |
| 333 | } |
| 334 | #endif |
| 335 | |
| 336 | #if __has_builtin(__builtin_bitreverse64)1 |
| 337 | template<> |
| 338 | inline uint64_t reverseBits<uint64_t>(uint64_t Val) { |
| 339 | return __builtin_bitreverse64(Val); |
| 340 | } |
| 341 | #endif |
| 342 | |
| 343 | // NOTE: The following support functions use the _32/_64 extensions instead of |
| 344 | // type overloading so that signed and unsigned integers can be used without |
| 345 | // ambiguity. |
| 346 | |
| 347 | /// Return the high 32 bits of a 64 bit value. |
| 348 | constexpr inline uint32_t Hi_32(uint64_t Value) { |
| 349 | return static_cast<uint32_t>(Value >> 32); |
| 350 | } |
| 351 | |
| 352 | /// Return the low 32 bits of a 64 bit value. |
| 353 | constexpr inline uint32_t Lo_32(uint64_t Value) { |
| 354 | return static_cast<uint32_t>(Value); |
| 355 | } |
| 356 | |
| 357 | /// Make a 64-bit integer from a high / low pair of 32-bit integers. |
| 358 | constexpr inline uint64_t Make_64(uint32_t High, uint32_t Low) { |
| 359 | return ((uint64_t)High << 32) | (uint64_t)Low; |
| 360 | } |
| 361 | |
| 362 | /// Checks if an integer fits into the given bit width. |
| 363 | template <unsigned N> constexpr inline bool isInt(int64_t x) { |
| 364 | return N >= 64 || (-(INT64_C(1)1LL<<(N-1)) <= x && x < (INT64_C(1)1LL<<(N-1))); |
| 365 | } |
| 366 | // Template specializations to get better code for common cases. |
| 367 | template <> constexpr inline bool isInt<8>(int64_t x) { |
| 368 | return static_cast<int8_t>(x) == x; |
| 369 | } |
| 370 | template <> constexpr inline bool isInt<16>(int64_t x) { |
| 371 | return static_cast<int16_t>(x) == x; |
| 372 | } |
| 373 | template <> constexpr inline bool isInt<32>(int64_t x) { |
| 374 | return static_cast<int32_t>(x) == x; |
| 375 | } |
| 376 | |
| 377 | /// Checks if a signed integer is an N bit number shifted left by S. |
| 378 | template <unsigned N, unsigned S> |
| 379 | constexpr inline bool isShiftedInt(int64_t x) { |
| 380 | static_assert( |
| 381 | N > 0, "isShiftedInt<0> doesn't make sense (refers to a 0-bit number."); |
| 382 | static_assert(N + S <= 64, "isShiftedInt<N, S> with N + S > 64 is too wide."); |
| 383 | return isInt<N + S>(x) && (x % (UINT64_C(1)1ULL << S) == 0); |
| 384 | } |
| 385 | |
| 386 | /// Checks if an unsigned integer fits into the given bit width. |
| 387 | /// |
| 388 | /// This is written as two functions rather than as simply |
| 389 | /// |
| 390 | /// return N >= 64 || X < (UINT64_C(1) << N); |
| 391 | /// |
| 392 | /// to keep MSVC from (incorrectly) warning on isUInt<64> that we're shifting |
| 393 | /// left too many places. |
| 394 | template <unsigned N> |
| 395 | constexpr inline std::enable_if_t<(N < 64), bool> isUInt(uint64_t X) { |
| 396 | static_assert(N > 0, "isUInt<0> doesn't make sense"); |
| 397 | return X < (UINT64_C(1)1ULL << (N)); |
| 398 | } |
| 399 | template <unsigned N> |
| 400 | constexpr inline std::enable_if_t<N >= 64, bool> isUInt(uint64_t) { |
| 401 | return true; |
| 402 | } |
| 403 | |
| 404 | // Template specializations to get better code for common cases. |
| 405 | template <> constexpr inline bool isUInt<8>(uint64_t x) { |
| 406 | return static_cast<uint8_t>(x) == x; |
| 407 | } |
| 408 | template <> constexpr inline bool isUInt<16>(uint64_t x) { |
| 409 | return static_cast<uint16_t>(x) == x; |
| 410 | } |
| 411 | template <> constexpr inline bool isUInt<32>(uint64_t x) { |
| 412 | return static_cast<uint32_t>(x) == x; |
| 413 | } |
| 414 | |
| 415 | /// Checks if a unsigned integer is an N bit number shifted left by S. |
| 416 | template <unsigned N, unsigned S> |
| 417 | constexpr inline bool isShiftedUInt(uint64_t x) { |
| 418 | static_assert( |
| 419 | N > 0, "isShiftedUInt<0> doesn't make sense (refers to a 0-bit number)"); |
| 420 | static_assert(N + S <= 64, |
| 421 | "isShiftedUInt<N, S> with N + S > 64 is too wide."); |
| 422 | // Per the two static_asserts above, S must be strictly less than 64. So |
| 423 | // 1 << S is not undefined behavior. |
| 424 | return isUInt<N + S>(x) && (x % (UINT64_C(1)1ULL << S) == 0); |
| 425 | } |
| 426 | |
| 427 | /// Gets the maximum value for a N-bit unsigned integer. |
| 428 | inline uint64_t maxUIntN(uint64_t N) { |
| 429 | assert(N > 0 && N <= 64 && "integer width out of range")((void)0); |
| 430 | |
| 431 | // uint64_t(1) << 64 is undefined behavior, so we can't do |
| 432 | // (uint64_t(1) << N) - 1 |
| 433 | // without checking first that N != 64. But this works and doesn't have a |
| 434 | // branch. |
| 435 | return UINT64_MAX0xffffffffffffffffULL >> (64 - N); |
| 436 | } |
| 437 | |
| 438 | /// Gets the minimum value for a N-bit signed integer. |
| 439 | inline int64_t minIntN(int64_t N) { |
| 440 | assert(N > 0 && N <= 64 && "integer width out of range")((void)0); |
| 441 | |
| 442 | return UINT64_C(1)1ULL + ~(UINT64_C(1)1ULL << (N - 1)); |
| 443 | } |
| 444 | |
| 445 | /// Gets the maximum value for a N-bit signed integer. |
| 446 | inline int64_t maxIntN(int64_t N) { |
| 447 | assert(N > 0 && N <= 64 && "integer width out of range")((void)0); |
| 448 | |
| 449 | // This relies on two's complement wraparound when N == 64, so we convert to |
| 450 | // int64_t only at the very end to avoid UB. |
| 451 | return (UINT64_C(1)1ULL << (N - 1)) - 1; |
| 452 | } |
| 453 | |
| 454 | /// Checks if an unsigned integer fits into the given (dynamic) bit width. |
| 455 | inline bool isUIntN(unsigned N, uint64_t x) { |
| 456 | return N >= 64 || x <= maxUIntN(N); |
| 457 | } |
| 458 | |
| 459 | /// Checks if an signed integer fits into the given (dynamic) bit width. |
| 460 | inline bool isIntN(unsigned N, int64_t x) { |
| 461 | return N >= 64 || (minIntN(N) <= x && x <= maxIntN(N)); |
| 462 | } |
| 463 | |
| 464 | /// Return true if the argument is a non-empty sequence of ones starting at the |
| 465 | /// least significant bit with the remainder zero (32 bit version). |
| 466 | /// Ex. isMask_32(0x0000FFFFU) == true. |
| 467 | constexpr inline bool isMask_32(uint32_t Value) { |
| 468 | return Value && ((Value + 1) & Value) == 0; |
| 469 | } |
| 470 | |
| 471 | /// Return true if the argument is a non-empty sequence of ones starting at the |
| 472 | /// least significant bit with the remainder zero (64 bit version). |
| 473 | constexpr inline bool isMask_64(uint64_t Value) { |
| 474 | return Value && ((Value + 1) & Value) == 0; |
| 475 | } |
| 476 | |
| 477 | /// Return true if the argument contains a non-empty sequence of ones with the |
| 478 | /// remainder zero (32 bit version.) Ex. isShiftedMask_32(0x0000FF00U) == true. |
| 479 | constexpr inline bool isShiftedMask_32(uint32_t Value) { |
| 480 | return Value && isMask_32((Value - 1) | Value); |
| 481 | } |
| 482 | |
| 483 | /// Return true if the argument contains a non-empty sequence of ones with the |
| 484 | /// remainder zero (64 bit version.) |
| 485 | constexpr inline bool isShiftedMask_64(uint64_t Value) { |
| 486 | return Value && isMask_64((Value - 1) | Value); |
| 487 | } |
| 488 | |
| 489 | /// Return true if the argument is a power of two > 0. |
| 490 | /// Ex. isPowerOf2_32(0x00100000U) == true (32 bit edition.) |
| 491 | constexpr inline bool isPowerOf2_32(uint32_t Value) { |
| 492 | return Value && !(Value & (Value - 1)); |
| 493 | } |
| 494 | |
| 495 | /// Return true if the argument is a power of two > 0 (64 bit edition.) |
| 496 | constexpr inline bool isPowerOf2_64(uint64_t Value) { |
| 497 | return Value && !(Value & (Value - 1)); |
| 498 | } |
| 499 | |
| 500 | /// Count the number of ones from the most significant bit to the first |
| 501 | /// zero bit. |
| 502 | /// |
| 503 | /// Ex. countLeadingOnes(0xFF0FFF00) == 8. |
| 504 | /// Only unsigned integral types are allowed. |
| 505 | /// |
| 506 | /// \param ZB the behavior on an input of all ones. Only ZB_Width and |
| 507 | /// ZB_Undefined are valid arguments. |
| 508 | template <typename T> |
| 509 | unsigned countLeadingOnes(T Value, ZeroBehavior ZB = ZB_Width) { |
| 510 | static_assert(std::numeric_limits<T>::is_integer && |
| 511 | !std::numeric_limits<T>::is_signed, |
| 512 | "Only unsigned integral types are allowed."); |
| 513 | return countLeadingZeros<T>(~Value, ZB); |
| 514 | } |
| 515 | |
| 516 | /// Count the number of ones from the least significant bit to the first |
| 517 | /// zero bit. |
| 518 | /// |
| 519 | /// Ex. countTrailingOnes(0x00FF00FF) == 8. |
| 520 | /// Only unsigned integral types are allowed. |
| 521 | /// |
| 522 | /// \param ZB the behavior on an input of all ones. Only ZB_Width and |
| 523 | /// ZB_Undefined are valid arguments. |
| 524 | template <typename T> |
| 525 | unsigned countTrailingOnes(T Value, ZeroBehavior ZB = ZB_Width) { |
| 526 | static_assert(std::numeric_limits<T>::is_integer && |
| 527 | !std::numeric_limits<T>::is_signed, |
| 528 | "Only unsigned integral types are allowed."); |
| 529 | return countTrailingZeros<T>(~Value, ZB); |
| 530 | } |
| 531 | |
| 532 | namespace detail { |
| 533 | template <typename T, std::size_t SizeOfT> struct PopulationCounter { |
| 534 | static unsigned count(T Value) { |
| 535 | // Generic version, forward to 32 bits. |
| 536 | static_assert(SizeOfT <= 4, "Not implemented!"); |
| 537 | #if defined(__GNUC__4) |
| 538 | return __builtin_popcount(Value); |
| 539 | #else |
| 540 | uint32_t v = Value; |
| 541 | v = v - ((v >> 1) & 0x55555555); |
| 542 | v = (v & 0x33333333) + ((v >> 2) & 0x33333333); |
| 543 | return ((v + (v >> 4) & 0xF0F0F0F) * 0x1010101) >> 24; |
| 544 | #endif |
| 545 | } |
| 546 | }; |
| 547 | |
| 548 | template <typename T> struct PopulationCounter<T, 8> { |
| 549 | static unsigned count(T Value) { |
| 550 | #if defined(__GNUC__4) |
| 551 | return __builtin_popcountll(Value); |
| 552 | #else |
| 553 | uint64_t v = Value; |
| 554 | v = v - ((v >> 1) & 0x5555555555555555ULL); |
| 555 | v = (v & 0x3333333333333333ULL) + ((v >> 2) & 0x3333333333333333ULL); |
| 556 | v = (v + (v >> 4)) & 0x0F0F0F0F0F0F0F0FULL; |
| 557 | return unsigned((uint64_t)(v * 0x0101010101010101ULL) >> 56); |
| 558 | #endif |
| 559 | } |
| 560 | }; |
| 561 | } // namespace detail |
| 562 | |
| 563 | /// Count the number of set bits in a value. |
| 564 | /// Ex. countPopulation(0xF000F000) = 8 |
| 565 | /// Returns 0 if the word is zero. |
| 566 | template <typename T> |
| 567 | inline unsigned countPopulation(T Value) { |
| 568 | static_assert(std::numeric_limits<T>::is_integer && |
| 569 | !std::numeric_limits<T>::is_signed, |
| 570 | "Only unsigned integral types are allowed."); |
| 571 | return detail::PopulationCounter<T, sizeof(T)>::count(Value); |
| 572 | } |
| 573 | |
| 574 | /// Compile time Log2. |
| 575 | /// Valid only for positive powers of two. |
| 576 | template <size_t kValue> constexpr inline size_t CTLog2() { |
| 577 | static_assert(kValue > 0 && llvm::isPowerOf2_64(kValue), |
| 578 | "Value is not a valid power of 2"); |
| 579 | return 1 + CTLog2<kValue / 2>(); |
| 580 | } |
| 581 | |
| 582 | template <> constexpr inline size_t CTLog2<1>() { return 0; } |
| 583 | |
| 584 | /// Return the log base 2 of the specified value. |
| 585 | inline double Log2(double Value) { |
| 586 | #if defined(__ANDROID_API__) && __ANDROID_API__ < 18 |
| 587 | return __builtin_log(Value) / __builtin_log(2.0); |
| 588 | #else |
| 589 | return log2(Value); |
| 590 | #endif |
| 591 | } |
| 592 | |
| 593 | /// Return the floor log base 2 of the specified value, -1 if the value is zero. |
| 594 | /// (32 bit edition.) |
| 595 | /// Ex. Log2_32(32) == 5, Log2_32(1) == 0, Log2_32(0) == -1, Log2_32(6) == 2 |
| 596 | inline unsigned Log2_32(uint32_t Value) { |
| 597 | return 31 - countLeadingZeros(Value); |
| 598 | } |
| 599 | |
| 600 | /// Return the floor log base 2 of the specified value, -1 if the value is zero. |
| 601 | /// (64 bit edition.) |
| 602 | inline unsigned Log2_64(uint64_t Value) { |
| 603 | return 63 - countLeadingZeros(Value); |
| 604 | } |
| 605 | |
| 606 | /// Return the ceil log base 2 of the specified value, 32 if the value is zero. |
| 607 | /// (32 bit edition). |
| 608 | /// Ex. Log2_32_Ceil(32) == 5, Log2_32_Ceil(1) == 0, Log2_32_Ceil(6) == 3 |
| 609 | inline unsigned Log2_32_Ceil(uint32_t Value) { |
| 610 | return 32 - countLeadingZeros(Value - 1); |
| 611 | } |
| 612 | |
| 613 | /// Return the ceil log base 2 of the specified value, 64 if the value is zero. |
| 614 | /// (64 bit edition.) |
| 615 | inline unsigned Log2_64_Ceil(uint64_t Value) { |
| 616 | return 64 - countLeadingZeros(Value - 1); |
| 617 | } |
| 618 | |
| 619 | /// Return the greatest common divisor of the values using Euclid's algorithm. |
| 620 | template <typename T> |
| 621 | inline T greatestCommonDivisor(T A, T B) { |
| 622 | while (B) { |
| 623 | T Tmp = B; |
| 624 | B = A % B; |
| 625 | A = Tmp; |
| 626 | } |
| 627 | return A; |
| 628 | } |
| 629 | |
| 630 | inline uint64_t GreatestCommonDivisor64(uint64_t A, uint64_t B) { |
| 631 | return greatestCommonDivisor<uint64_t>(A, B); |
| 632 | } |
| 633 | |
| 634 | /// This function takes a 64-bit integer and returns the bit equivalent double. |
| 635 | inline double BitsToDouble(uint64_t Bits) { |
| 636 | double D; |
| 637 | static_assert(sizeof(uint64_t) == sizeof(double), "Unexpected type sizes"); |
| 638 | memcpy(&D, &Bits, sizeof(Bits)); |
| 639 | return D; |
| 640 | } |
| 641 | |
| 642 | /// This function takes a 32-bit integer and returns the bit equivalent float. |
| 643 | inline float BitsToFloat(uint32_t Bits) { |
| 644 | float F; |
| 645 | static_assert(sizeof(uint32_t) == sizeof(float), "Unexpected type sizes"); |
| 646 | memcpy(&F, &Bits, sizeof(Bits)); |
| 647 | return F; |
| 648 | } |
| 649 | |
| 650 | /// This function takes a double and returns the bit equivalent 64-bit integer. |
| 651 | /// Note that copying doubles around changes the bits of NaNs on some hosts, |
| 652 | /// notably x86, so this routine cannot be used if these bits are needed. |
| 653 | inline uint64_t DoubleToBits(double Double) { |
| 654 | uint64_t Bits; |
| 655 | static_assert(sizeof(uint64_t) == sizeof(double), "Unexpected type sizes"); |
| 656 | memcpy(&Bits, &Double, sizeof(Double)); |
| 657 | return Bits; |
| 658 | } |
| 659 | |
| 660 | /// This function takes a float and returns the bit equivalent 32-bit integer. |
| 661 | /// Note that copying floats around changes the bits of NaNs on some hosts, |
| 662 | /// notably x86, so this routine cannot be used if these bits are needed. |
| 663 | inline uint32_t FloatToBits(float Float) { |
| 664 | uint32_t Bits; |
| 665 | static_assert(sizeof(uint32_t) == sizeof(float), "Unexpected type sizes"); |
| 666 | memcpy(&Bits, &Float, sizeof(Float)); |
| 667 | return Bits; |
| 668 | } |
| 669 | |
| 670 | /// A and B are either alignments or offsets. Return the minimum alignment that |
| 671 | /// may be assumed after adding the two together. |
| 672 | constexpr inline uint64_t MinAlign(uint64_t A, uint64_t B) { |
| 673 | // The largest power of 2 that divides both A and B. |
| 674 | // |
| 675 | // Replace "-Value" by "1+~Value" in the following commented code to avoid |
| 676 | // MSVC warning C4146 |
| 677 | // return (A | B) & -(A | B); |
| 678 | return (A | B) & (1 + ~(A | B)); |
| 679 | } |
| 680 | |
| 681 | /// Returns the next power of two (in 64-bits) that is strictly greater than A. |
| 682 | /// Returns zero on overflow. |
| 683 | inline uint64_t NextPowerOf2(uint64_t A) { |
| 684 | A |= (A >> 1); |
| 685 | A |= (A >> 2); |
| 686 | A |= (A >> 4); |
| 687 | A |= (A >> 8); |
| 688 | A |= (A >> 16); |
| 689 | A |= (A >> 32); |
| 690 | return A + 1; |
| 691 | } |
| 692 | |
| 693 | /// Returns the power of two which is less than or equal to the given value. |
| 694 | /// Essentially, it is a floor operation across the domain of powers of two. |
| 695 | inline uint64_t PowerOf2Floor(uint64_t A) { |
| 696 | if (!A) return 0; |
| 697 | return 1ull << (63 - countLeadingZeros(A, ZB_Undefined)); |
| 698 | } |
| 699 | |
| 700 | /// Returns the power of two which is greater than or equal to the given value. |
| 701 | /// Essentially, it is a ceil operation across the domain of powers of two. |
| 702 | inline uint64_t PowerOf2Ceil(uint64_t A) { |
| 703 | if (!A) |
| 704 | return 0; |
| 705 | return NextPowerOf2(A - 1); |
| 706 | } |
| 707 | |
| 708 | /// Returns the next integer (mod 2**64) that is greater than or equal to |
| 709 | /// \p Value and is a multiple of \p Align. \p Align must be non-zero. |
| 710 | /// |
| 711 | /// If non-zero \p Skew is specified, the return value will be a minimal |
| 712 | /// integer that is greater than or equal to \p Value and equal to |
| 713 | /// \p Align * N + \p Skew for some integer N. If \p Skew is larger than |
| 714 | /// \p Align, its value is adjusted to '\p Skew mod \p Align'. |
| 715 | /// |
| 716 | /// Examples: |
| 717 | /// \code |
| 718 | /// alignTo(5, 8) = 8 |
| 719 | /// alignTo(17, 8) = 24 |
| 720 | /// alignTo(~0LL, 8) = 0 |
| 721 | /// alignTo(321, 255) = 510 |
| 722 | /// |
| 723 | /// alignTo(5, 8, 7) = 7 |
| 724 | /// alignTo(17, 8, 1) = 17 |
| 725 | /// alignTo(~0LL, 8, 3) = 3 |
| 726 | /// alignTo(321, 255, 42) = 552 |
| 727 | /// \endcode |
| 728 | inline uint64_t alignTo(uint64_t Value, uint64_t Align, uint64_t Skew = 0) { |
| 729 | assert(Align != 0u && "Align can't be 0.")((void)0); |
| 730 | Skew %= Align; |
| 731 | return (Value + Align - 1 - Skew) / Align * Align + Skew; |
| 732 | } |
| 733 | |
| 734 | /// Returns the next integer (mod 2**64) that is greater than or equal to |
| 735 | /// \p Value and is a multiple of \c Align. \c Align must be non-zero. |
| 736 | template <uint64_t Align> constexpr inline uint64_t alignTo(uint64_t Value) { |
| 737 | static_assert(Align != 0u, "Align must be non-zero"); |
| 738 | return (Value + Align - 1) / Align * Align; |
| 739 | } |
| 740 | |
| 741 | /// Returns the integer ceil(Numerator / Denominator). |
| 742 | inline uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator) { |
| 743 | return alignTo(Numerator, Denominator) / Denominator; |
| 744 | } |
| 745 | |
| 746 | /// Returns the integer nearest(Numerator / Denominator). |
| 747 | inline uint64_t divideNearest(uint64_t Numerator, uint64_t Denominator) { |
| 748 | return (Numerator + (Denominator / 2)) / Denominator; |
| 749 | } |
| 750 | |
| 751 | /// Returns the largest uint64_t less than or equal to \p Value and is |
| 752 | /// \p Skew mod \p Align. \p Align must be non-zero |
| 753 | inline uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew = 0) { |
| 754 | assert(Align != 0u && "Align can't be 0.")((void)0); |
| 755 | Skew %= Align; |
| 756 | return (Value - Skew) / Align * Align + Skew; |
| 757 | } |
| 758 | |
| 759 | /// Sign-extend the number in the bottom B bits of X to a 32-bit integer. |
| 760 | /// Requires 0 < B <= 32. |
| 761 | template <unsigned B> constexpr inline int32_t SignExtend32(uint32_t X) { |
| 762 | static_assert(B > 0, "Bit width can't be 0."); |
| 763 | static_assert(B <= 32, "Bit width out of range."); |
| 764 | return int32_t(X << (32 - B)) >> (32 - B); |
| 765 | } |
| 766 | |
| 767 | /// Sign-extend the number in the bottom B bits of X to a 32-bit integer. |
| 768 | /// Requires 0 < B <= 32. |
| 769 | inline int32_t SignExtend32(uint32_t X, unsigned B) { |
| 770 | assert(B > 0 && "Bit width can't be 0.")((void)0); |
| 771 | assert(B <= 32 && "Bit width out of range.")((void)0); |
| 772 | return int32_t(X << (32 - B)) >> (32 - B); |
| 773 | } |
| 774 | |
| 775 | /// Sign-extend the number in the bottom B bits of X to a 64-bit integer. |
| 776 | /// Requires 0 < B <= 64. |
| 777 | template <unsigned B> constexpr inline int64_t SignExtend64(uint64_t x) { |
| 778 | static_assert(B > 0, "Bit width can't be 0."); |
| 779 | static_assert(B <= 64, "Bit width out of range."); |
| 780 | return int64_t(x << (64 - B)) >> (64 - B); |
| 781 | } |
| 782 | |
| 783 | /// Sign-extend the number in the bottom B bits of X to a 64-bit integer. |
| 784 | /// Requires 0 < B <= 64. |
| 785 | inline int64_t SignExtend64(uint64_t X, unsigned B) { |
| 786 | assert(B > 0 && "Bit width can't be 0.")((void)0); |
| 787 | assert(B <= 64 && "Bit width out of range.")((void)0); |
| 788 | return int64_t(X << (64 - B)) >> (64 - B); |
| 789 | } |
| 790 | |
| 791 | /// Subtract two unsigned integers, X and Y, of type T and return the absolute |
| 792 | /// value of the result. |
| 793 | template <typename T> |
| 794 | std::enable_if_t<std::is_unsigned<T>::value, T> AbsoluteDifference(T X, T Y) { |
| 795 | return X > Y ? (X - Y) : (Y - X); |
| 796 | } |
| 797 | |
| 798 | /// Add two unsigned integers, X and Y, of type T. Clamp the result to the |
| 799 | /// maximum representable value of T on overflow. ResultOverflowed indicates if |
| 800 | /// the result is larger than the maximum representable value of type T. |
| 801 | template <typename T> |
| 802 | std::enable_if_t<std::is_unsigned<T>::value, T> |
| 803 | SaturatingAdd(T X, T Y, bool *ResultOverflowed = nullptr) { |
| 804 | bool Dummy; |
| 805 | bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy; |
| 806 | // Hacker's Delight, p. 29 |
| 807 | T Z = X + Y; |
| 808 | Overflowed = (Z < X || Z < Y); |
| 809 | if (Overflowed) |
| 810 | return std::numeric_limits<T>::max(); |
| 811 | else |
| 812 | return Z; |
| 813 | } |
| 814 | |
| 815 | /// Multiply two unsigned integers, X and Y, of type T. Clamp the result to the |
| 816 | /// maximum representable value of T on overflow. ResultOverflowed indicates if |
| 817 | /// the result is larger than the maximum representable value of type T. |
| 818 | template <typename T> |
| 819 | std::enable_if_t<std::is_unsigned<T>::value, T> |
| 820 | SaturatingMultiply(T X, T Y, bool *ResultOverflowed = nullptr) { |
| 821 | bool Dummy; |
| 822 | bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy; |
| 823 | |
| 824 | // Hacker's Delight, p. 30 has a different algorithm, but we don't use that |
| 825 | // because it fails for uint16_t (where multiplication can have undefined |
| 826 | // behavior due to promotion to int), and requires a division in addition |
| 827 | // to the multiplication. |
| 828 | |
| 829 | Overflowed = false; |
| 830 | |
| 831 | // Log2(Z) would be either Log2Z or Log2Z + 1. |
| 832 | // Special case: if X or Y is 0, Log2_64 gives -1, and Log2Z |
| 833 | // will necessarily be less than Log2Max as desired. |
| 834 | int Log2Z = Log2_64(X) + Log2_64(Y); |
| 835 | const T Max = std::numeric_limits<T>::max(); |
| 836 | int Log2Max = Log2_64(Max); |
| 837 | if (Log2Z < Log2Max) { |
| 838 | return X * Y; |
| 839 | } |
| 840 | if (Log2Z > Log2Max) { |
| 841 | Overflowed = true; |
| 842 | return Max; |
| 843 | } |
| 844 | |
| 845 | // We're going to use the top bit, and maybe overflow one |
| 846 | // bit past it. Multiply all but the bottom bit then add |
| 847 | // that on at the end. |
| 848 | T Z = (X >> 1) * Y; |
| 849 | if (Z & ~(Max >> 1)) { |
| 850 | Overflowed = true; |
| 851 | return Max; |
| 852 | } |
| 853 | Z <<= 1; |
| 854 | if (X & 1) |
| 855 | return SaturatingAdd(Z, Y, ResultOverflowed); |
| 856 | |
| 857 | return Z; |
| 858 | } |
| 859 | |
| 860 | /// Multiply two unsigned integers, X and Y, and add the unsigned integer, A to |
| 861 | /// the product. Clamp the result to the maximum representable value of T on |
| 862 | /// overflow. ResultOverflowed indicates if the result is larger than the |
| 863 | /// maximum representable value of type T. |
| 864 | template <typename T> |
| 865 | std::enable_if_t<std::is_unsigned<T>::value, T> |
| 866 | SaturatingMultiplyAdd(T X, T Y, T A, bool *ResultOverflowed = nullptr) { |
| 867 | bool Dummy; |
| 868 | bool &Overflowed = ResultOverflowed ? *ResultOverflowed : Dummy; |
| 869 | |
| 870 | T Product = SaturatingMultiply(X, Y, &Overflowed); |
| 871 | if (Overflowed) |
| 872 | return Product; |
| 873 | |
| 874 | return SaturatingAdd(A, Product, &Overflowed); |
| 875 | } |
| 876 | |
| 877 | /// Use this rather than HUGE_VALF; the latter causes warnings on MSVC. |
| 878 | extern const float huge_valf; |
| 879 | |
| 880 | |
| 881 | /// Add two signed integers, computing the two's complement truncated result, |
| 882 | /// returning true if overflow occured. |
| 883 | template <typename T> |
| 884 | std::enable_if_t<std::is_signed<T>::value, T> AddOverflow(T X, T Y, T &Result) { |
| 885 | #if __has_builtin(__builtin_add_overflow)1 |
| 886 | return __builtin_add_overflow(X, Y, &Result); |
| 887 | #else |
| 888 | // Perform the unsigned addition. |
| 889 | using U = std::make_unsigned_t<T>; |
| 890 | const U UX = static_cast<U>(X); |
| 891 | const U UY = static_cast<U>(Y); |
| 892 | const U UResult = UX + UY; |
| 893 | |
| 894 | // Convert to signed. |
| 895 | Result = static_cast<T>(UResult); |
| 896 | |
| 897 | // Adding two positive numbers should result in a positive number. |
| 898 | if (X > 0 && Y > 0) |
| 899 | return Result <= 0; |
| 900 | // Adding two negatives should result in a negative number. |
| 901 | if (X < 0 && Y < 0) |
| 902 | return Result >= 0; |
| 903 | return false; |
| 904 | #endif |
| 905 | } |
| 906 | |
| 907 | /// Subtract two signed integers, computing the two's complement truncated |
| 908 | /// result, returning true if an overflow ocurred. |
| 909 | template <typename T> |
| 910 | std::enable_if_t<std::is_signed<T>::value, T> SubOverflow(T X, T Y, T &Result) { |
| 911 | #if __has_builtin(__builtin_sub_overflow)1 |
| 912 | return __builtin_sub_overflow(X, Y, &Result); |
| 913 | #else |
| 914 | // Perform the unsigned addition. |
| 915 | using U = std::make_unsigned_t<T>; |
| 916 | const U UX = static_cast<U>(X); |
| 917 | const U UY = static_cast<U>(Y); |
| 918 | const U UResult = UX - UY; |
| 919 | |
| 920 | // Convert to signed. |
| 921 | Result = static_cast<T>(UResult); |
| 922 | |
| 923 | // Subtracting a positive number from a negative results in a negative number. |
| 924 | if (X <= 0 && Y > 0) |
| 925 | return Result >= 0; |
| 926 | // Subtracting a negative number from a positive results in a positive number. |
| 927 | if (X >= 0 && Y < 0) |
| 928 | return Result <= 0; |
| 929 | return false; |
| 930 | #endif |
| 931 | } |
| 932 | |
| 933 | /// Multiply two signed integers, computing the two's complement truncated |
| 934 | /// result, returning true if an overflow ocurred. |
| 935 | template <typename T> |
| 936 | std::enable_if_t<std::is_signed<T>::value, T> MulOverflow(T X, T Y, T &Result) { |
| 937 | // Perform the unsigned multiplication on absolute values. |
| 938 | using U = std::make_unsigned_t<T>; |
| 939 | const U UX = X < 0 ? (0 - static_cast<U>(X)) : static_cast<U>(X); |
| 940 | const U UY = Y < 0 ? (0 - static_cast<U>(Y)) : static_cast<U>(Y); |
| 941 | const U UResult = UX * UY; |
| 942 | |
| 943 | // Convert to signed. |
| 944 | const bool IsNegative = (X < 0) ^ (Y < 0); |
| 945 | Result = IsNegative ? (0 - UResult) : UResult; |
| 946 | |
| 947 | // If any of the args was 0, result is 0 and no overflow occurs. |
| 948 | if (UX == 0 || UY == 0) |
| 949 | return false; |
| 950 | |
| 951 | // UX and UY are in [1, 2^n], where n is the number of digits. |
| 952 | // Check how the max allowed absolute value (2^n for negative, 2^(n-1) for |
| 953 | // positive) divided by an argument compares to the other. |
| 954 | if (IsNegative) |
| 955 | return UX > (static_cast<U>(std::numeric_limits<T>::max()) + U(1)) / UY; |
| 956 | else |
| 957 | return UX > (static_cast<U>(std::numeric_limits<T>::max())) / UY; |
| 958 | } |
| 959 | |
| 960 | } // End llvm namespace |
| 961 | |
| 962 | #endif |