File: | src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c |
Warning: | line 5139, column 2 Value stored to 'value' is never read |
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1 | /* i386.c -- Assemble code for the Intel 80386 |
2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
3 | 2000, 2001, 2002, 2003, 2004, 2005, 2006 |
4 | Free Software Foundation, Inc. |
5 | |
6 | This file is part of GAS, the GNU Assembler. |
7 | |
8 | GAS is free software; you can redistribute it and/or modify |
9 | it under the terms of the GNU General Public License as published by |
10 | the Free Software Foundation; either version 2, or (at your option) |
11 | any later version. |
12 | |
13 | GAS is distributed in the hope that it will be useful, |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
16 | GNU General Public License for more details. |
17 | |
18 | You should have received a copy of the GNU General Public License |
19 | along with GAS; see the file COPYING. If not, write to the Free |
20 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
21 | 02110-1301, USA. */ |
22 | |
23 | /* Intel 80386 machine specific gas. |
24 | Written by Eliot Dresselhaus (eliot@mgm.mit.edu). |
25 | x86_64 support by Jan Hubicka (jh@suse.cz) |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz) |
27 | Bugs & suggestions are completely welcome. This is free software. |
28 | Please help us make it better. */ |
29 | |
30 | #include "as.h" |
31 | #include "safe-ctype.h" |
32 | #include "subsegs.h" |
33 | #include "dwarf2dbg.h" |
34 | #include "dw2gencfi.h" |
35 | #include "opcode/i386.h" |
36 | #include "elf/x86-64.h" |
37 | |
38 | #ifndef REGISTER_WARNINGS1 |
39 | #define REGISTER_WARNINGS1 1 |
40 | #endif |
41 | |
42 | #ifndef INFER_ADDR_PREFIX1 |
43 | #define INFER_ADDR_PREFIX1 1 |
44 | #endif |
45 | |
46 | #ifndef SCALE1_WHEN_NO_INDEX1 |
47 | /* Specifying a scale factor besides 1 when there is no index is |
48 | futile. eg. `mov (%ebx,2),%al' does exactly the same as |
49 | `mov (%ebx),%al'. To slavishly follow what the programmer |
50 | specified, set SCALE1_WHEN_NO_INDEX to 0. */ |
51 | #define SCALE1_WHEN_NO_INDEX1 1 |
52 | #endif |
53 | |
54 | #ifndef DEFAULT_ARCH"x86_64" |
55 | #define DEFAULT_ARCH"x86_64" "i386" |
56 | #endif |
57 | |
58 | #ifndef INLINE__inline__ |
59 | #if __GNUC__4 >= 2 |
60 | #define INLINE__inline__ __inline__ |
61 | #else |
62 | #define INLINE__inline__ |
63 | #endif |
64 | #endif |
65 | |
66 | static INLINE__inline__ unsigned int mode_from_disp_size PARAMS ((unsigned int))(unsigned int); |
67 | static INLINE__inline__ int fits_in_signed_byte PARAMS ((offsetT))(offsetT); |
68 | static INLINE__inline__ int fits_in_unsigned_byte PARAMS ((offsetT))(offsetT); |
69 | static INLINE__inline__ int fits_in_unsigned_word PARAMS ((offsetT))(offsetT); |
70 | static INLINE__inline__ int fits_in_signed_word PARAMS ((offsetT))(offsetT); |
71 | static INLINE__inline__ int fits_in_unsigned_long PARAMS ((offsetT))(offsetT); |
72 | static INLINE__inline__ int fits_in_signed_long PARAMS ((offsetT))(offsetT); |
73 | static int smallest_imm_type PARAMS ((offsetT))(offsetT); |
74 | static offsetT offset_in_range PARAMS ((offsetT, int))(offsetT, int); |
75 | static int add_prefix PARAMS ((unsigned int))(unsigned int); |
76 | static void set_code_flag PARAMS ((int))(int); |
77 | static void set_16bit_gcc_code_flag PARAMS ((int))(int); |
78 | static void set_intel_syntax PARAMS ((int))(int); |
79 | static void set_cpu_arch PARAMS ((int))(int); |
80 | #ifdef TE_PE |
81 | static void pe_directive_secrel PARAMS ((int))(int); |
82 | #endif |
83 | static void signed_cons PARAMS ((int))(int); |
84 | static char *output_invalid PARAMS ((int c))(int c); |
85 | static int i386_operand PARAMS ((char *operand_string))(char *operand_string); |
86 | static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float))(char *operand_string, int got_a_float); |
87 | static const reg_entry *parse_register PARAMS ((char *reg_string,(char *reg_string, char **end_op) |
88 | char **end_op))(char *reg_string, char **end_op); |
89 | static char *parse_insn PARAMS ((char *, char *))(char *, char *); |
90 | static char *parse_operands PARAMS ((char *, const char *))(char *, const char *); |
91 | static void swap_operands PARAMS ((void))(void); |
92 | static void optimize_imm PARAMS ((void))(void); |
93 | static void optimize_disp PARAMS ((void))(void); |
94 | static int match_template PARAMS ((void))(void); |
95 | static int check_string PARAMS ((void))(void); |
96 | static int process_suffix PARAMS ((void))(void); |
97 | static int check_byte_reg PARAMS ((void))(void); |
98 | static int check_long_reg PARAMS ((void))(void); |
99 | static int check_qword_reg PARAMS ((void))(void); |
100 | static int check_word_reg PARAMS ((void))(void); |
101 | static int finalize_imm PARAMS ((void))(void); |
102 | static int process_operands PARAMS ((void))(void); |
103 | static const seg_entry *build_modrm_byte PARAMS ((void))(void); |
104 | static void output_insn PARAMS ((void))(void); |
105 | static void output_branch PARAMS ((void))(void); |
106 | static void output_jump PARAMS ((void))(void); |
107 | static void output_interseg_jump PARAMS ((void))(void); |
108 | static void output_imm PARAMS ((fragS *insn_start_frag,(fragS *insn_start_frag, offsetT insn_start_off) |
109 | offsetT insn_start_off))(fragS *insn_start_frag, offsetT insn_start_off); |
110 | static void output_disp PARAMS ((fragS *insn_start_frag,(fragS *insn_start_frag, offsetT insn_start_off) |
111 | offsetT insn_start_off))(fragS *insn_start_frag, offsetT insn_start_off); |
112 | #ifndef I386COFF |
113 | static void s_bss PARAMS ((int))(int); |
114 | #endif |
115 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
116 | static void handle_large_common (int small ATTRIBUTE_UNUSED__attribute__ ((__unused__))); |
117 | #endif |
118 | |
119 | static const char *default_arch = DEFAULT_ARCH"x86_64"; |
120 | |
121 | /* 'md_assemble ()' gathers together information and puts it into a |
122 | i386_insn. */ |
123 | |
124 | union i386_op |
125 | { |
126 | expressionS *disps; |
127 | expressionS *imms; |
128 | const reg_entry *regs; |
129 | }; |
130 | |
131 | struct _i386_insn |
132 | { |
133 | /* TM holds the template for the insn were currently assembling. */ |
134 | template tm; |
135 | |
136 | /* SUFFIX holds the instruction mnemonic suffix if given. |
137 | (e.g. 'l' for 'movl') */ |
138 | char suffix; |
139 | |
140 | /* OPERANDS gives the number of given operands. */ |
141 | unsigned int operands; |
142 | |
143 | /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number |
144 | of given register, displacement, memory operands and immediate |
145 | operands. */ |
146 | unsigned int reg_operands, disp_operands, mem_operands, imm_operands; |
147 | |
148 | /* TYPES [i] is the type (see above #defines) which tells us how to |
149 | use OP[i] for the corresponding operand. */ |
150 | unsigned int types[MAX_OPERANDS3]; |
151 | |
152 | /* Displacement expression, immediate expression, or register for each |
153 | operand. */ |
154 | union i386_op op[MAX_OPERANDS3]; |
155 | |
156 | /* Flags for operands. */ |
157 | unsigned int flags[MAX_OPERANDS3]; |
158 | #define Operand_PCrel1 1 |
159 | |
160 | /* Relocation type for operand */ |
161 | enum bfd_reloc_code_real reloc[MAX_OPERANDS3]; |
162 | |
163 | /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode |
164 | the base index byte below. */ |
165 | const reg_entry *base_reg; |
166 | const reg_entry *index_reg; |
167 | unsigned int log2_scale_factor; |
168 | |
169 | /* SEG gives the seg_entries of this insn. They are zero unless |
170 | explicit segment overrides are given. */ |
171 | const seg_entry *seg[2]; |
172 | |
173 | /* PREFIX holds all the given prefix opcodes (usually null). |
174 | PREFIXES is the number of prefix opcodes. */ |
175 | unsigned int prefixes; |
176 | unsigned char prefix[MAX_PREFIXES6]; |
177 | |
178 | /* RM and SIB are the modrm byte and the sib byte where the |
179 | addressing modes of this insn are encoded. */ |
180 | |
181 | modrm_byte rm; |
182 | rex_byte rex; |
183 | sib_byte sib; |
184 | }; |
185 | |
186 | typedef struct _i386_insn i386_insn; |
187 | |
188 | /* List of chars besides those in app.c:symbol_chars that can start an |
189 | operand. Used to prevent the scrubber eating vital white-space. */ |
190 | const char extra_symbol_chars[] = "*%-([" |
191 | #ifdef LEX_AT |
192 | "@" |
193 | #endif |
194 | #ifdef LEX_QM |
195 | "?" |
196 | #endif |
197 | ; |
198 | |
199 | #if (defined (TE_I386AIX) \ |
200 | || ((defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)) \ |
201 | && !defined (TE_GNU) \ |
202 | && !defined (TE_LINUX) \ |
203 | && !defined (TE_NETWARE) \ |
204 | && !defined (TE_FreeBSD) \ |
205 | && !defined (TE_NetBSD) \ |
206 | && !defined (TE_OpenBSD1))) |
207 | /* This array holds the chars that always start a comment. If the |
208 | pre-processor is disabled, these aren't very useful. The option |
209 | --divide will remove '/' from this list. */ |
210 | const char *i386_comment_chars = "#/"; |
211 | #define SVR4_COMMENT_CHARS 1 |
212 | #define PREFIX_SEPARATOR'/' '\\' |
213 | |
214 | #else |
215 | const char *i386_comment_chars = "#"; |
216 | #define PREFIX_SEPARATOR'/' '/' |
217 | #endif |
218 | |
219 | /* This array holds the chars that only start a comment at the beginning of |
220 | a line. If the line seems to have the form '# 123 filename' |
221 | .line and .file directives will appear in the pre-processed output. |
222 | Note that input_file.c hand checks for '#' at the beginning of the |
223 | first line of the input file. This is because the compiler outputs |
224 | #NO_APP at the beginning of its output. |
225 | Also note that comments started like this one will always work if |
226 | '/' isn't otherwise defined. */ |
227 | const char line_comment_chars[] = "#/"; |
228 | |
229 | const char line_separator_chars[] = ";"; |
230 | |
231 | /* Chars that can be used to separate mant from exp in floating point |
232 | nums. */ |
233 | const char EXP_CHARS[] = "eE"; |
234 | |
235 | /* Chars that mean this number is a floating point constant |
236 | As in 0f12.456 |
237 | or 0d1.2345e12. */ |
238 | const char FLT_CHARS[] = "fFdDxX"; |
239 | |
240 | /* Tables for lexical analysis. */ |
241 | static char mnemonic_chars[256]; |
242 | static char register_chars[256]; |
243 | static char operand_chars[256]; |
244 | static char identifier_chars[256]; |
245 | static char digit_chars[256]; |
246 | |
247 | /* Lexical macros. */ |
248 | #define is_mnemonic_char(x)(mnemonic_chars[(unsigned char) x]) (mnemonic_chars[(unsigned char) x]) |
249 | #define is_operand_char(x)(operand_chars[(unsigned char) x]) (operand_chars[(unsigned char) x]) |
250 | #define is_register_char(x)(register_chars[(unsigned char) x]) (register_chars[(unsigned char) x]) |
251 | #define is_space_char(x)((x) == ' ') ((x) == ' ') |
252 | #define is_identifier_char(x)(identifier_chars[(unsigned char) x]) (identifier_chars[(unsigned char) x]) |
253 | #define is_digit_char(x)(digit_chars[(unsigned char) x]) (digit_chars[(unsigned char) x]) |
254 | |
255 | /* All non-digit non-letter characters that may occur in an operand. */ |
256 | static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]"; |
257 | |
258 | /* md_assemble() always leaves the strings it's passed unaltered. To |
259 | effect this we maintain a stack of saved characters that we've smashed |
260 | with '\0's (indicating end of strings for various sub-fields of the |
261 | assembler instruction). */ |
262 | static char save_stack[32]; |
263 | static char *save_stack_p; |
264 | #define END_STRING_AND_SAVE(s)do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) \ |
265 | do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0) |
266 | #define RESTORE_END_STRING(s)do { *(s) = *--save_stack_p; } while (0) \ |
267 | do { *(s) = *--save_stack_p; } while (0) |
268 | |
269 | /* The instruction we're assembling. */ |
270 | static i386_insn i; |
271 | |
272 | /* Possible templates for current insn. */ |
273 | static const templates *current_templates; |
274 | |
275 | /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */ |
276 | static expressionS disp_expressions[2], im_expressions[2]; |
277 | |
278 | /* Current operand we are working on. */ |
279 | static int this_operand; |
280 | |
281 | /* We support four different modes. FLAG_CODE variable is used to distinguish |
282 | these. */ |
283 | |
284 | enum flag_code { |
285 | CODE_32BIT, |
286 | CODE_16BIT, |
287 | CODE_64BIT }; |
288 | #define NUM_FLAG_CODE((int) CODE_64BIT + 1) ((int) CODE_64BIT + 1) |
289 | |
290 | static enum flag_code flag_code; |
291 | static unsigned int object_64bit; |
292 | static int use_rela_relocations = 0; |
293 | |
294 | /* The names used to print error messages. */ |
295 | static const char *flag_code_names[] = |
296 | { |
297 | "32", |
298 | "16", |
299 | "64" |
300 | }; |
301 | |
302 | /* 1 for intel syntax, |
303 | 0 if att syntax. */ |
304 | static int intel_syntax = 0; |
305 | |
306 | /* 1 if register prefix % not required. */ |
307 | static int allow_naked_reg = 0; |
308 | |
309 | /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter, |
310 | leave, push, and pop instructions so that gcc has the same stack |
311 | frame as in 32 bit mode. */ |
312 | static char stackop_size = '\0'; |
313 | |
314 | /* Non-zero to optimize code alignment. */ |
315 | int optimize_align_code = 1; |
316 | |
317 | /* Non-zero to quieten some warnings. */ |
318 | static int quiet_warnings = 0; |
319 | |
320 | /* CPU name. */ |
321 | static const char *cpu_arch_name = NULL((void*)0); |
322 | static const char *cpu_sub_arch_name = NULL((void*)0); |
323 | |
324 | /* CPU feature flags. */ |
325 | static unsigned int cpu_arch_flags = CpuUnknownFlags(0x1|0x2|0x4|0x8|0x10|0x20|0x40 |0x80|0x400|0x800|0x1000|0x2000 |0x4000|0x20000|0x100000 |0x8000|0x10000|0x100|0x200|0x40000| 0x80000|0x200000 |0x400000|0x800000|0x1000000|0x2000000|0x4000000 ) | CpuNo640x10000000; |
326 | |
327 | /* If set, conditional jumps are not automatically promoted to handle |
328 | larger than a byte offset. */ |
329 | static unsigned int no_cond_jump_promotion = 0; |
330 | |
331 | /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */ |
332 | static symbolS *GOT_symbol; |
333 | |
334 | /* The dwarf2 return column, adjusted for 32 or 64 bit. */ |
335 | unsigned int x86_dwarf2_return_column; |
336 | |
337 | /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */ |
338 | int x86_cie_data_alignment; |
339 | |
340 | /* Interface to relax_segment. |
341 | There are 3 major relax states for 386 jump insns because the |
342 | different types of jumps add different sizes to frags when we're |
343 | figuring out what sort of jump to choose to reach a given label. */ |
344 | |
345 | /* Types. */ |
346 | #define UNCOND_JUMP0 0 |
347 | #define COND_JUMP1 1 |
348 | #define COND_JUMP862 2 |
349 | |
350 | /* Sizes. */ |
351 | #define CODE161 1 |
352 | #define SMALL0 0 |
353 | #define SMALL16(0 | 1) (SMALL0 | CODE161) |
354 | #define BIG2 2 |
355 | #define BIG16(2 | 1) (BIG2 | CODE161) |
356 | |
357 | #ifndef INLINE__inline__ |
358 | #ifdef __GNUC__4 |
359 | #define INLINE__inline__ __inline__ |
360 | #else |
361 | #define INLINE__inline__ |
362 | #endif |
363 | #endif |
364 | |
365 | #define ENCODE_RELAX_STATE(type, size)((relax_substateT) (((type) << 2) | (size))) \ |
366 | ((relax_substateT) (((type) << 2) | (size))) |
367 | #define TYPE_FROM_RELAX_STATE(s)((s) >> 2) \ |
368 | ((s) >> 2) |
369 | #define DISP_SIZE_FROM_RELAX_STATE(s)((((s) & 3) == 2 ? 4 : (((s) & 3) == (2 | 1) ? 2 : 1) )) \ |
370 | ((((s) & 3) == BIG2 ? 4 : (((s) & 3) == BIG16(2 | 1) ? 2 : 1))) |
371 | |
372 | /* This table is used by relax_frag to promote short jumps to long |
373 | ones where necessary. SMALL (short) jumps may be promoted to BIG |
374 | (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We |
375 | don't allow a short jump in a 32 bit code segment to be promoted to |
376 | a 16 bit offset jump because it's slower (requires data size |
377 | prefix), and doesn't work, unless the destination is in the bottom |
378 | 64k of the code segment (The top 16 bits of eip are zeroed). */ |
379 | |
380 | const relax_typeS md_relax_table[] = |
381 | { |
382 | /* The fields are: |
383 | 1) most positive reach of this state, |
384 | 2) most negative reach of this state, |
385 | 3) how many bytes this mode will have in the variable part of the frag |
386 | 4) which index into the table to try if we can't fit into this one. */ |
387 | |
388 | /* UNCOND_JUMP states. */ |
389 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)((relax_substateT) (((0) << 2) | (2)))}, |
390 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)((relax_substateT) (((0) << 2) | ((2 | 1))))}, |
391 | /* dword jmp adds 4 bytes to frag: |
392 | 0 extra opcode bytes, 4 displacement bytes. */ |
393 | {0, 0, 4, 0}, |
394 | /* word jmp adds 2 byte2 to frag: |
395 | 0 extra opcode bytes, 2 displacement bytes. */ |
396 | {0, 0, 2, 0}, |
397 | |
398 | /* COND_JUMP states. */ |
399 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)((relax_substateT) (((1) << 2) | (2)))}, |
400 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)((relax_substateT) (((1) << 2) | ((2 | 1))))}, |
401 | /* dword conditionals adds 5 bytes to frag: |
402 | 1 extra opcode byte, 4 displacement bytes. */ |
403 | {0, 0, 5, 0}, |
404 | /* word conditionals add 3 bytes to frag: |
405 | 1 extra opcode byte, 2 displacement bytes. */ |
406 | {0, 0, 3, 0}, |
407 | |
408 | /* COND_JUMP86 states. */ |
409 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)((relax_substateT) (((2) << 2) | (2)))}, |
410 | {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)((relax_substateT) (((2) << 2) | ((2 | 1))))}, |
411 | /* dword conditionals adds 5 bytes to frag: |
412 | 1 extra opcode byte, 4 displacement bytes. */ |
413 | {0, 0, 5, 0}, |
414 | /* word conditionals add 4 bytes to frag: |
415 | 1 displacement byte and a 3 byte long branch insn. */ |
416 | {0, 0, 4, 0} |
417 | }; |
418 | |
419 | static const arch_entry cpu_arch[] = { |
420 | {"i8086", Cpu0860x1 }, |
421 | {"i186", Cpu0860x1|Cpu1860x2 }, |
422 | {"i286", Cpu0860x1|Cpu1860x2|Cpu2860x4 }, |
423 | {"i386", Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8 }, |
424 | {"i486", Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10 }, |
425 | {"i586", Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20 }, |
426 | {"i686", Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40 }, |
427 | {"pentium", Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20 }, |
428 | {"pentiumpro",Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40 }, |
429 | {"pentiumii", Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuMMX0x800 }, |
430 | {"pentiumiii",Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuMMX0x800|CpuMMX20x1000|CpuSSE0x2000 }, |
431 | {"pentium4", Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuP40x80|CpuMMX0x800|CpuMMX20x1000|CpuSSE0x2000|CpuSSE20x4000 }, |
432 | {"prescott", Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuP40x80|CpuMMX0x800|CpuMMX20x1000|CpuSSE0x2000|CpuSSE20x4000|CpuPNI0x20000 }, |
433 | {"k6", Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|CpuK60x100|CpuMMX0x800 }, |
434 | {"k6_2", Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|CpuK60x100|CpuMMX0x800|Cpu3dnow0x8000 }, |
435 | {"athlon", Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuK60x100|CpuAthlon0x200|CpuMMX0x800|CpuMMX20x1000|Cpu3dnow0x8000|Cpu3dnowA0x10000 }, |
436 | {"sledgehammer",Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuK60x100|CpuAthlon0x200|CpuSledgehammer0x400|CpuMMX0x800|CpuMMX20x1000|Cpu3dnow0x8000|Cpu3dnowA0x10000|CpuSSE0x2000|CpuSSE20x4000 }, |
437 | {"opteron", Cpu0860x1|Cpu1860x2|Cpu2860x4|Cpu3860x8|Cpu4860x10|Cpu5860x20|Cpu6860x40|CpuK60x100|CpuAthlon0x200|CpuSledgehammer0x400|CpuMMX0x800|CpuMMX20x1000|Cpu3dnow0x8000|Cpu3dnowA0x10000|CpuSSE0x2000|CpuSSE20x4000 }, |
438 | {".mmx", CpuMMX0x800 }, |
439 | {".sse", CpuMMX0x800|CpuMMX20x1000|CpuSSE0x2000 }, |
440 | {".sse2", CpuMMX0x800|CpuMMX20x1000|CpuSSE0x2000|CpuSSE20x4000 }, |
441 | {".sse3", CpuMMX0x800|CpuMMX20x1000|CpuSSE0x2000|CpuSSE20x4000|CpuSSE30x20000 }, |
442 | {".3dnow", CpuMMX0x800|Cpu3dnow0x8000 }, |
443 | {".3dnowa", CpuMMX0x800|CpuMMX20x1000|Cpu3dnow0x8000|Cpu3dnowA0x10000 }, |
444 | {".padlock", CpuPadLock0x40000 }, |
445 | {".pacifica", CpuSVME0x80000 }, |
446 | {".svme", CpuSVME0x80000 }, |
447 | {NULL((void*)0), 0 } |
448 | }; |
449 | |
450 | const pseudo_typeS md_pseudo_table[] = |
451 | { |
452 | #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO) |
453 | {"align", s_align_bytes, 0}, |
454 | #else |
455 | {"align", s_align_ptwo, 0}, |
456 | #endif |
457 | {"arch", set_cpu_arch, 0}, |
458 | #ifndef I386COFF |
459 | {"bss", s_bss, 0}, |
460 | #endif |
461 | {"ffloat", float_cons, 'f'}, |
462 | {"dfloat", float_cons, 'd'}, |
463 | {"tfloat", float_cons, 'x'}, |
464 | {"value", cons, 2}, |
465 | {"slong", signed_cons, 4}, |
466 | {"noopt", s_ignore, 0}, |
467 | {"optim", s_ignore, 0}, |
468 | {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT}, |
469 | {"code16", set_code_flag, CODE_16BIT}, |
470 | {"code32", set_code_flag, CODE_32BIT}, |
471 | {"code64", set_code_flag, CODE_64BIT}, |
472 | {"intel_syntax", set_intel_syntax, 1}, |
473 | {"att_syntax", set_intel_syntax, 0}, |
474 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
475 | {"largecomm", handle_large_common, 0}, |
476 | #else |
477 | {"file", (void (*) PARAMS ((int))(int)) dwarf2_directive_file, 0}, |
478 | {"loc", dwarf2_directive_loc, 0}, |
479 | {"loc_mark_labels", dwarf2_directive_loc_mark_labels, 0}, |
480 | #endif |
481 | #ifdef TE_PE |
482 | {"secrel32", pe_directive_secrel, 0}, |
483 | #endif |
484 | {0, 0, 0} |
485 | }; |
486 | |
487 | /* For interface with expression (). */ |
488 | extern char *input_line_pointer; |
489 | |
490 | /* Hash table for instruction mnemonic lookup. */ |
491 | static struct hash_control *op_hash; |
492 | |
493 | /* Hash table for register lookup. */ |
494 | static struct hash_control *reg_hash; |
495 | |
496 | void |
497 | i386_align_code (fragP, count) |
498 | fragS *fragP; |
499 | int count; |
500 | { |
501 | /* Various efficient no-op patterns for aligning code labels. |
502 | Note: Don't try to assemble the instructions in the comments. |
503 | 0L and 0w are not legal. */ |
504 | static const char f32_1[] = |
505 | {0x90}; /* nop */ |
506 | static const char f32_2[] = |
507 | {0x89,0xf6}; /* movl %esi,%esi */ |
508 | static const char f32_15[] = |
509 | {0xeb,0x0d,0xCC,0xCC,0xCC,0xCC,0xCC, /* jmp .+15; lotsa int3 */ |
510 | 0xCC,0xCC,0xCC,0xCC,0xCC,0xCC,0xCC,0xCC}; |
511 | static const char f16_3[] = |
512 | {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */ |
513 | static const char f16_4[] = |
514 | {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
515 | static const char f16_5[] = |
516 | {0x90, /* nop */ |
517 | 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */ |
518 | static const char f16_6[] = |
519 | {0x89,0xf6, /* mov %si,%si */ |
520 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
521 | static const char f16_7[] = |
522 | {0x8d,0x74,0x00, /* lea 0(%si),%si */ |
523 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
524 | static const char f16_8[] = |
525 | {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */ |
526 | 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */ |
527 | static const char f64_2[] = |
528 | {0x66,0x90}; /* data16, nop*/ |
529 | static const char *const f32_patt[] = { |
530 | f32_1, f32_2, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, |
531 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
532 | }; |
533 | static const char *const f16_patt[] = { |
534 | f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8, |
535 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
536 | }; |
537 | static const char *const f64_patt[] = { |
538 | f32_1, f64_2, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, |
539 | f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15 |
540 | }; |
541 | |
542 | if (count <= 0 || count > 15) |
543 | return; |
544 | |
545 | if (flag_code == CODE_64BIT) |
546 | { |
547 | memcpy(fragP->fr_literal + fragP->fr_fix, |
548 | f64_patt[count -1], count); |
549 | if (count > 2) |
550 | /* Adjust jump offset */ |
551 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
552 | } |
553 | else |
554 | if (flag_code == CODE_16BIT) |
555 | { |
556 | memcpy (fragP->fr_literal + fragP->fr_fix, |
557 | f16_patt[count - 1], count); |
558 | if (count > 8) |
559 | /* Adjust jump offset. */ |
560 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
561 | } |
562 | else |
563 | { |
564 | memcpy (fragP->fr_literal + fragP->fr_fix, |
565 | f32_patt[count - 1], count); |
566 | if (count > 2) |
567 | /* Adjust jump offset */ |
568 | fragP->fr_literal[fragP->fr_fix + 1] = count - 2; |
569 | } |
570 | fragP->fr_var = count; |
571 | } |
572 | |
573 | static INLINE__inline__ unsigned int |
574 | mode_from_disp_size (t) |
575 | unsigned int t; |
576 | { |
577 | return (t & Disp80x1000) ? 1 : (t & (Disp160x2000 | Disp320x4000 | Disp32S0x8000)) ? 2 : 0; |
578 | } |
579 | |
580 | static INLINE__inline__ int |
581 | fits_in_signed_byte (num) |
582 | offsetT num; |
583 | { |
584 | return (num >= -128) && (num <= 127); |
585 | } |
586 | |
587 | static INLINE__inline__ int |
588 | fits_in_unsigned_byte (num) |
589 | offsetT num; |
590 | { |
591 | return (num & 0xff) == num; |
592 | } |
593 | |
594 | static INLINE__inline__ int |
595 | fits_in_unsigned_word (num) |
596 | offsetT num; |
597 | { |
598 | return (num & 0xffff) == num; |
599 | } |
600 | |
601 | static INLINE__inline__ int |
602 | fits_in_signed_word (num) |
603 | offsetT num; |
604 | { |
605 | return (-32768 <= num) && (num <= 32767); |
606 | } |
607 | static INLINE__inline__ int |
608 | fits_in_signed_long (num) |
609 | offsetT num ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
610 | { |
611 | #ifndef BFD64 |
612 | return 1; |
613 | #else |
614 | return (!(-((offsetT) 1 << 31) & num) |
615 | || (-((offsetT) 1 << 31) & num) == -((offsetT) 1 << 31)); |
616 | #endif |
617 | } /* fits_in_signed_long() */ |
618 | static INLINE__inline__ int |
619 | fits_in_unsigned_long (num) |
620 | offsetT num ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
621 | { |
622 | #ifndef BFD64 |
623 | return 1; |
624 | #else |
625 | return (num & (((offsetT) 2 << 31) - 1)) == num; |
626 | #endif |
627 | } /* fits_in_unsigned_long() */ |
628 | |
629 | static int |
630 | smallest_imm_type (num) |
631 | offsetT num; |
632 | { |
633 | if (cpu_arch_flags != (Cpu0860x1 | Cpu1860x2 | Cpu2860x4 | Cpu3860x8 | Cpu4860x10 | CpuNo640x10000000)) |
634 | { |
635 | /* This code is disabled on the 486 because all the Imm1 forms |
636 | in the opcode table are slower on the i486. They're the |
637 | versions with the implicitly specified single-position |
638 | displacement, which has another syntax if you really want to |
639 | use that form. */ |
640 | if (num == 1) |
641 | return Imm10x400 | Imm80x10 | Imm8S0x20 | Imm160x40 | Imm320x80 | Imm32S0x100 | Imm640x200; |
642 | } |
643 | return (fits_in_signed_byte (num) |
644 | ? (Imm8S0x20 | Imm80x10 | Imm160x40 | Imm320x80 | Imm32S0x100 | Imm640x200) |
645 | : fits_in_unsigned_byte (num) |
646 | ? (Imm80x10 | Imm160x40 | Imm320x80 | Imm32S0x100 | Imm640x200) |
647 | : (fits_in_signed_word (num) || fits_in_unsigned_word (num)) |
648 | ? (Imm160x40 | Imm320x80 | Imm32S0x100 | Imm640x200) |
649 | : fits_in_signed_long (num) |
650 | ? (Imm320x80 | Imm32S0x100 | Imm640x200) |
651 | : fits_in_unsigned_long (num) |
652 | ? (Imm320x80 | Imm640x200) |
653 | : Imm640x200); |
654 | } |
655 | |
656 | static offsetT |
657 | offset_in_range (val, size) |
658 | offsetT val; |
659 | int size; |
660 | { |
661 | addressT mask; |
662 | |
663 | switch (size) |
664 | { |
665 | case 1: mask = ((addressT) 1 << 8) - 1; break; |
666 | case 2: mask = ((addressT) 1 << 16) - 1; break; |
667 | case 4: mask = ((addressT) 2 << 31) - 1; break; |
668 | #ifdef BFD64 |
669 | case 8: mask = ((addressT) 2 << 63) - 1; break; |
670 | #endif |
671 | default: abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 671, __PRETTY_FUNCTION__); |
672 | } |
673 | |
674 | /* If BFD64, sign extend val. */ |
675 | if (!use_rela_relocations) |
676 | if ((val & ~(((addressT) 2 << 31) - 1)) == 0) |
677 | val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
678 | |
679 | if ((val & ~mask) != 0 && (val & ~mask) != ~mask) |
680 | { |
681 | char buf1[40], buf2[40]; |
682 | |
683 | sprint_value (buf1, val); |
684 | sprint_value (buf2, val & mask); |
685 | as_warn (_("%s shortened to %s")("%s shortened to %s"), buf1, buf2); |
686 | } |
687 | return val & mask; |
688 | } |
689 | |
690 | /* Returns 0 if attempting to add a prefix where one from the same |
691 | class already exists, 1 if non rep/repne added, 2 if rep/repne |
692 | added. */ |
693 | static int |
694 | add_prefix (prefix) |
695 | unsigned int prefix; |
696 | { |
697 | int ret = 1; |
698 | unsigned int q; |
699 | |
700 | if (prefix >= REX_OPCODE0x40 && prefix < REX_OPCODE0x40 + 16 |
701 | && flag_code == CODE_64BIT) |
702 | { |
703 | if ((i.prefix[REX_PREFIX5] & prefix & REX_MODE648) |
704 | || ((i.prefix[REX_PREFIX5] & (REX_EXTX4 | REX_EXTY2 | REX_EXTZ1)) |
705 | && (prefix & (REX_EXTX4 | REX_EXTY2 | REX_EXTZ1)))) |
706 | ret = 0; |
707 | q = REX_PREFIX5; |
708 | } |
709 | else |
710 | { |
711 | switch (prefix) |
712 | { |
713 | default: |
714 | abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 714, __PRETTY_FUNCTION__); |
715 | |
716 | case CS_PREFIX_OPCODE0x2e: |
717 | case DS_PREFIX_OPCODE0x3e: |
718 | case ES_PREFIX_OPCODE0x26: |
719 | case FS_PREFIX_OPCODE0x64: |
720 | case GS_PREFIX_OPCODE0x65: |
721 | case SS_PREFIX_OPCODE0x36: |
722 | q = SEG_PREFIX4; |
723 | break; |
724 | |
725 | case REPNE_PREFIX_OPCODE0xf2: |
726 | case REPE_PREFIX_OPCODE0xf3: |
727 | ret = 2; |
728 | /* fall thru */ |
729 | case LOCK_PREFIX_OPCODE0xf0: |
730 | q = LOCKREP_PREFIX1; |
731 | break; |
732 | |
733 | case FWAIT_OPCODE0x9b: |
734 | q = WAIT_PREFIX0; |
735 | break; |
736 | |
737 | case ADDR_PREFIX_OPCODE0x67: |
738 | q = ADDR_PREFIX2; |
739 | break; |
740 | |
741 | case DATA_PREFIX_OPCODE0x66: |
742 | q = DATA_PREFIX3; |
743 | break; |
744 | } |
745 | if (i.prefix[q] != 0) |
746 | ret = 0; |
747 | } |
748 | |
749 | if (ret) |
750 | { |
751 | if (!i.prefix[q]) |
752 | ++i.prefixes; |
753 | i.prefix[q] |= prefix; |
754 | } |
755 | else |
756 | as_bad (_("same type of prefix used twice")("same type of prefix used twice")); |
757 | |
758 | return ret; |
759 | } |
760 | |
761 | static void |
762 | set_code_flag (value) |
763 | int value; |
764 | { |
765 | flag_code = value; |
766 | cpu_arch_flags &= ~(Cpu640x8000000 | CpuNo640x10000000); |
767 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu640x8000000 : CpuNo640x10000000); |
768 | if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer0x400)) |
769 | { |
770 | as_bad (_("64bit mode not supported on this CPU.")("64bit mode not supported on this CPU.")); |
771 | } |
772 | if (value == CODE_32BIT && !(cpu_arch_flags & Cpu3860x8)) |
773 | { |
774 | as_bad (_("32bit mode not supported on this CPU.")("32bit mode not supported on this CPU.")); |
775 | } |
776 | stackop_size = '\0'; |
777 | } |
778 | |
779 | static void |
780 | set_16bit_gcc_code_flag (new_code_flag) |
781 | int new_code_flag; |
782 | { |
783 | flag_code = new_code_flag; |
784 | cpu_arch_flags &= ~(Cpu640x8000000 | CpuNo640x10000000); |
785 | cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu640x8000000 : CpuNo640x10000000); |
786 | stackop_size = LONG_MNEM_SUFFIX'l'; |
787 | } |
788 | |
789 | static void |
790 | set_intel_syntax (syntax_flag) |
791 | int syntax_flag; |
792 | { |
793 | /* Find out if register prefixing is specified. */ |
794 | int ask_naked_reg = 0; |
795 | |
796 | SKIP_WHITESPACE ()((*input_line_pointer == ' ') ? ++input_line_pointer : 0); |
797 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
798 | { |
799 | char *string = input_line_pointer; |
800 | int e = get_symbol_end (); |
801 | |
802 | if (strcmp (string, "prefix") == 0) |
803 | ask_naked_reg = 1; |
804 | else if (strcmp (string, "noprefix") == 0) |
805 | ask_naked_reg = -1; |
806 | else |
807 | as_bad (_("bad argument to syntax directive.")("bad argument to syntax directive.")); |
808 | *input_line_pointer = e; |
809 | } |
810 | demand_empty_rest_of_line (); |
811 | |
812 | intel_syntax = syntax_flag; |
813 | |
814 | if (ask_naked_reg == 0) |
815 | allow_naked_reg = (intel_syntax |
816 | && (bfd_get_symbol_leading_char (stdoutput)((stdoutput)->xvec->symbol_leading_char) != '\0')); |
817 | else |
818 | allow_naked_reg = (ask_naked_reg < 0); |
819 | |
820 | identifier_chars['%'] = intel_syntax && allow_naked_reg ? '%' : 0; |
821 | identifier_chars['$'] = intel_syntax ? '$' : 0; |
822 | } |
823 | |
824 | static void |
825 | set_cpu_arch (dummy) |
826 | int dummy ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
827 | { |
828 | SKIP_WHITESPACE ()((*input_line_pointer == ' ') ? ++input_line_pointer : 0); |
829 | |
830 | if (!is_end_of_line[(unsigned char) *input_line_pointer]) |
831 | { |
832 | char *string = input_line_pointer; |
833 | int e = get_symbol_end (); |
834 | int i; |
835 | |
836 | for (i = 0; cpu_arch[i].name; i++) |
837 | { |
838 | if (strcmp (string, cpu_arch[i].name) == 0) |
839 | { |
840 | if (*string != '.') |
841 | { |
842 | cpu_arch_name = cpu_arch[i].name; |
843 | cpu_sub_arch_name = NULL((void*)0); |
844 | cpu_arch_flags = (cpu_arch[i].flags |
845 | | (flag_code == CODE_64BIT ? Cpu640x8000000 : CpuNo640x10000000)); |
846 | break; |
847 | } |
848 | if ((cpu_arch_flags | cpu_arch[i].flags) != cpu_arch_flags) |
849 | { |
850 | cpu_sub_arch_name = cpu_arch[i].name; |
851 | cpu_arch_flags |= cpu_arch[i].flags; |
852 | } |
853 | *input_line_pointer = e; |
854 | demand_empty_rest_of_line (); |
855 | return; |
856 | } |
857 | } |
858 | if (!cpu_arch[i].name) |
859 | as_bad (_("no such architecture: `%s'")("no such architecture: `%s'"), string); |
860 | |
861 | *input_line_pointer = e; |
862 | } |
863 | else |
864 | as_bad (_("missing cpu architecture")("missing cpu architecture")); |
865 | |
866 | no_cond_jump_promotion = 0; |
867 | if (*input_line_pointer == ',' |
868 | && !is_end_of_line[(unsigned char) input_line_pointer[1]]) |
869 | { |
870 | char *string = ++input_line_pointer; |
871 | int e = get_symbol_end (); |
872 | |
873 | if (strcmp (string, "nojumps") == 0) |
874 | no_cond_jump_promotion = 1; |
875 | else if (strcmp (string, "jumps") == 0) |
876 | ; |
877 | else |
878 | as_bad (_("no such architecture modifier: `%s'")("no such architecture modifier: `%s'"), string); |
879 | |
880 | *input_line_pointer = e; |
881 | } |
882 | |
883 | demand_empty_rest_of_line (); |
884 | } |
885 | |
886 | unsigned long |
887 | i386_mach () |
888 | { |
889 | if (!strcmp (default_arch, "x86_64")) |
890 | return bfd_mach_x86_6464; |
891 | else if (!strcmp (default_arch, "i386")) |
892 | return bfd_mach_i386_i3861; |
893 | else |
894 | as_fatal (_("Unknown architecture")("Unknown architecture")); |
895 | } |
896 | |
897 | void |
898 | md_begin () |
899 | { |
900 | const char *hash_err; |
901 | |
902 | /* Initialize op_hash hash table. */ |
903 | op_hash = hash_new (); |
904 | |
905 | { |
906 | const template *optab; |
907 | templates *core_optab; |
908 | |
909 | /* Setup for loop. */ |
910 | optab = i386_optab; |
911 | core_optab = (templates *) xmalloc (sizeof (templates)); |
912 | core_optab->start = optab; |
913 | |
914 | while (1) |
915 | { |
916 | ++optab; |
917 | if (optab->name == NULL((void*)0) |
918 | || strcmp (optab->name, (optab - 1)->name) != 0) |
919 | { |
920 | /* different name --> ship out current template list; |
921 | add to hash table; & begin anew. */ |
922 | core_optab->end = optab; |
923 | hash_err = hash_insert (op_hash, |
924 | (optab - 1)->name, |
925 | (PTRvoid *) core_optab); |
926 | if (hash_err) |
927 | { |
928 | as_fatal (_("Internal Error: Can't hash %s: %s")("Internal Error: Can't hash %s: %s"), |
929 | (optab - 1)->name, |
930 | hash_err); |
931 | } |
932 | if (optab->name == NULL((void*)0)) |
933 | break; |
934 | core_optab = (templates *) xmalloc (sizeof (templates)); |
935 | core_optab->start = optab; |
936 | } |
937 | } |
938 | } |
939 | |
940 | /* Initialize reg_hash hash table. */ |
941 | reg_hash = hash_new (); |
942 | { |
943 | const reg_entry *regtab; |
944 | |
945 | for (regtab = i386_regtab; |
946 | regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]); |
947 | regtab++) |
948 | { |
949 | hash_err = hash_insert (reg_hash, regtab->reg_name, (PTRvoid *) regtab); |
950 | if (hash_err) |
951 | as_fatal (_("Internal Error: Can't hash %s: %s")("Internal Error: Can't hash %s: %s"), |
952 | regtab->reg_name, |
953 | hash_err); |
954 | } |
955 | } |
956 | |
957 | /* Fill in lexical tables: mnemonic_chars, operand_chars. */ |
958 | { |
959 | int c; |
960 | char *p; |
961 | |
962 | for (c = 0; c < 256; c++) |
963 | { |
964 | if (ISDIGIT (c)(_sch_istable[(c) & 0xff] & (unsigned short)(_sch_isdigit ))) |
965 | { |
966 | digit_chars[c] = c; |
967 | mnemonic_chars[c] = c; |
968 | register_chars[c] = c; |
969 | operand_chars[c] = c; |
970 | } |
971 | else if (ISLOWER (c)(_sch_istable[(c) & 0xff] & (unsigned short)(_sch_islower ))) |
972 | { |
973 | mnemonic_chars[c] = c; |
974 | register_chars[c] = c; |
975 | operand_chars[c] = c; |
976 | } |
977 | else if (ISUPPER (c)(_sch_istable[(c) & 0xff] & (unsigned short)(_sch_isupper ))) |
978 | { |
979 | mnemonic_chars[c] = TOLOWER (c)_sch_tolower[(c) & 0xff]; |
980 | register_chars[c] = mnemonic_chars[c]; |
981 | operand_chars[c] = c; |
982 | } |
983 | |
984 | if (ISALPHA (c)(_sch_istable[(c) & 0xff] & (unsigned short)(_sch_isalpha )) || ISDIGIT (c)(_sch_istable[(c) & 0xff] & (unsigned short)(_sch_isdigit ))) |
985 | identifier_chars[c] = c; |
986 | else if (c >= 128) |
987 | { |
988 | identifier_chars[c] = c; |
989 | operand_chars[c] = c; |
990 | } |
991 | } |
992 | |
993 | #ifdef LEX_AT |
994 | identifier_chars['@'] = '@'; |
995 | #endif |
996 | #ifdef LEX_QM |
997 | identifier_chars['?'] = '?'; |
998 | operand_chars['?'] = '?'; |
999 | #endif |
1000 | digit_chars['-'] = '-'; |
1001 | mnemonic_chars['-'] = '-'; |
1002 | identifier_chars['_'] = '_'; |
1003 | identifier_chars['.'] = '.'; |
1004 | |
1005 | for (p = operand_special_chars; *p != '\0'; p++) |
1006 | operand_chars[(unsigned char) *p] = *p; |
1007 | } |
1008 | |
1009 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
1010 | if (IS_ELF1) |
1011 | { |
1012 | record_alignment (text_section, 2); |
1013 | record_alignment (data_section, 2); |
1014 | record_alignment (bss_section, 2); |
1015 | } |
1016 | #endif |
1017 | |
1018 | if (flag_code == CODE_64BIT) |
1019 | { |
1020 | x86_dwarf2_return_column = 16; |
1021 | x86_cie_data_alignment = -8; |
1022 | } |
1023 | else |
1024 | { |
1025 | x86_dwarf2_return_column = 8; |
1026 | x86_cie_data_alignment = -4; |
1027 | } |
1028 | } |
1029 | |
1030 | void |
1031 | i386_print_statistics (file) |
1032 | FILE *file; |
1033 | { |
1034 | hash_print_statistics (file, "i386 opcode", op_hash); |
1035 | hash_print_statistics (file, "i386 register", reg_hash); |
1036 | } |
1037 | |
1038 | #ifdef DEBUG386 |
1039 | |
1040 | /* Debugging routines for md_assemble. */ |
1041 | static void pi PARAMS ((char *, i386_insn *))(char *, i386_insn *); |
1042 | static void pte PARAMS ((template *))(template *); |
1043 | static void pt PARAMS ((unsigned int))(unsigned int); |
1044 | static void pe PARAMS ((expressionS *))(expressionS *); |
1045 | static void ps PARAMS ((symbolS *))(symbolS *); |
1046 | |
1047 | static void |
1048 | pi (line, x) |
1049 | char *line; |
1050 | i386_insn *x; |
1051 | { |
1052 | unsigned int i; |
1053 | |
1054 | fprintf (stdout(&__sF[1]), "%s: template ", line); |
1055 | pte (&x->tm); |
1056 | fprintf (stdout(&__sF[1]), " address: base %s index %s scale %x\n", |
1057 | x->base_reg ? x->base_reg->reg_name : "none", |
1058 | x->index_reg ? x->index_reg->reg_name : "none", |
1059 | x->log2_scale_factor); |
1060 | fprintf (stdout(&__sF[1]), " modrm: mode %x reg %x reg/mem %x\n", |
1061 | x->rm.mode, x->rm.reg, x->rm.regmem); |
1062 | fprintf (stdout(&__sF[1]), " sib: base %x index %x scale %x\n", |
1063 | x->sib.base, x->sib.index, x->sib.scale); |
1064 | fprintf (stdout(&__sF[1]), " rex: 64bit %x extX %x extY %x extZ %x\n", |
1065 | (x->rex & REX_MODE648) != 0, |
1066 | (x->rex & REX_EXTX4) != 0, |
1067 | (x->rex & REX_EXTY2) != 0, |
1068 | (x->rex & REX_EXTZ1) != 0); |
1069 | for (i = 0; i < x->operands; i++) |
1070 | { |
1071 | fprintf (stdout(&__sF[1]), " #%d: ", i + 1); |
1072 | pt (x->types[i]); |
1073 | fprintf (stdout(&__sF[1]), "\n"); |
1074 | if (x->types[i] |
1075 | & (Reg(0x1|0x2|0x4|0x8) | SReg20x1000000 | SReg30x2000000 | Control0x80000 | Debug0x100000 | Test0x200000 | RegMMX0x10000000 | RegXMM0x20000000)) |
1076 | fprintf (stdout(&__sF[1]), "%s\n", x->op[i].regs->reg_name); |
1077 | if (x->types[i] & Imm(0x10|0x20|0x40|0x100|0x80|0x200)) |
1078 | pe (x->op[i].imms); |
1079 | if (x->types[i] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000)) |
1080 | pe (x->op[i].disps); |
1081 | } |
1082 | } |
1083 | |
1084 | static void |
1085 | pte (t) |
1086 | template *t; |
1087 | { |
1088 | unsigned int i; |
1089 | fprintf (stdout(&__sF[1]), " %d operands ", t->operands); |
1090 | fprintf (stdout(&__sF[1]), "opcode %x ", t->base_opcode); |
1091 | if (t->extension_opcode != None0xffff) |
1092 | fprintf (stdout(&__sF[1]), "ext %x ", t->extension_opcode); |
1093 | if (t->opcode_modifier & D0x2) |
1094 | fprintf (stdout(&__sF[1]), "D"); |
1095 | if (t->opcode_modifier & W0x1) |
1096 | fprintf (stdout(&__sF[1]), "W"); |
1097 | fprintf (stdout(&__sF[1]), "\n"); |
1098 | for (i = 0; i < t->operands; i++) |
1099 | { |
1100 | fprintf (stdout(&__sF[1]), " #%d type ", i + 1); |
1101 | pt (t->operand_types[i]); |
1102 | fprintf (stdout(&__sF[1]), "\n"); |
1103 | } |
1104 | } |
1105 | |
1106 | static void |
1107 | pe (e) |
1108 | expressionS *e; |
1109 | { |
1110 | fprintf (stdout(&__sF[1]), " operation %d\n", e->X_op); |
1111 | fprintf (stdout(&__sF[1]), " add_number %ld (%lx)\n", |
1112 | (long) e->X_add_number, (long) e->X_add_number); |
1113 | if (e->X_add_symbol) |
1114 | { |
1115 | fprintf (stdout(&__sF[1]), " add_symbol "); |
1116 | ps (e->X_add_symbol); |
1117 | fprintf (stdout(&__sF[1]), "\n"); |
1118 | } |
1119 | if (e->X_op_symbol) |
1120 | { |
1121 | fprintf (stdout(&__sF[1]), " op_symbol "); |
1122 | ps (e->X_op_symbol); |
1123 | fprintf (stdout(&__sF[1]), "\n"); |
1124 | } |
1125 | } |
1126 | |
1127 | static void |
1128 | ps (s) |
1129 | symbolS *s; |
1130 | { |
1131 | fprintf (stdout(&__sF[1]), "%s type %s%s", |
1132 | S_GET_NAME (s), |
1133 | S_IS_EXTERNAL (s) ? "EXTERNAL " : "", |
1134 | segment_name (S_GET_SEGMENT (s))((S_GET_SEGMENT (s))->name + 0)); |
1135 | } |
1136 | |
1137 | static struct type_name |
1138 | { |
1139 | unsigned int mask; |
1140 | char *tname; |
1141 | } |
1142 | const type_names[] = |
1143 | { |
1144 | { Reg80x1, "r8" }, |
1145 | { Reg160x2, "r16" }, |
1146 | { Reg320x4, "r32" }, |
1147 | { Reg640x8, "r64" }, |
1148 | { Imm80x10, "i8" }, |
1149 | { Imm8S0x20, "i8s" }, |
1150 | { Imm160x40, "i16" }, |
1151 | { Imm320x80, "i32" }, |
1152 | { Imm32S0x100, "i32s" }, |
1153 | { Imm640x200, "i64" }, |
1154 | { Imm10x400, "i1" }, |
1155 | { BaseIndex0x800, "BaseIndex" }, |
1156 | { Disp80x1000, "d8" }, |
1157 | { Disp160x2000, "d16" }, |
1158 | { Disp320x4000, "d32" }, |
1159 | { Disp32S0x8000, "d32s" }, |
1160 | { Disp640x10000, "d64" }, |
1161 | { InOutPortReg0x20000, "InOutPortReg" }, |
1162 | { ShiftCount0x40000, "ShiftCount" }, |
1163 | { Control0x80000, "control reg" }, |
1164 | { Test0x200000, "test reg" }, |
1165 | { Debug0x100000, "debug reg" }, |
1166 | { FloatReg0x400000, "FReg" }, |
1167 | { FloatAcc0x800000, "FAcc" }, |
1168 | { SReg20x1000000, "SReg2" }, |
1169 | { SReg30x2000000, "SReg3" }, |
1170 | { Acc0x4000000, "Acc" }, |
1171 | { JumpAbsolute0x8000000, "Jump Absolute" }, |
1172 | { RegMMX0x10000000, "rMMX" }, |
1173 | { RegXMM0x20000000, "rXMM" }, |
1174 | { EsSeg0x40000000, "es" }, |
1175 | { 0, "" } |
1176 | }; |
1177 | |
1178 | static void |
1179 | pt (t) |
1180 | unsigned int t; |
1181 | { |
1182 | const struct type_name *ty; |
1183 | |
1184 | for (ty = type_names; ty->mask; ty++) |
1185 | if (t & ty->mask) |
1186 | fprintf (stdout(&__sF[1]), "%s, ", ty->tname); |
1187 | fflush (stdout(&__sF[1])); |
1188 | } |
1189 | |
1190 | #endif /* DEBUG386 */ |
1191 | |
1192 | static bfd_reloc_code_real_type |
1193 | reloc (unsigned int size, |
1194 | int pcrel, |
1195 | int sign, |
1196 | bfd_reloc_code_real_type other) |
1197 | { |
1198 | if (other != NO_RELOCBFD_RELOC_NONE) |
1199 | { |
1200 | reloc_howto_type *reloc; |
1201 | |
1202 | if (size == 8) |
1203 | switch (other) |
1204 | { |
1205 | case BFD_RELOC_X86_64_GOT32: |
1206 | return BFD_RELOC_X86_64_GOT64; |
1207 | break; |
1208 | case BFD_RELOC_X86_64_PLTOFF64: |
1209 | return BFD_RELOC_X86_64_PLTOFF64; |
1210 | break; |
1211 | case BFD_RELOC_X86_64_GOTPC32: |
1212 | other = BFD_RELOC_X86_64_GOTPC64; |
1213 | break; |
1214 | case BFD_RELOC_X86_64_GOTPCREL: |
1215 | other = BFD_RELOC_X86_64_GOTPCREL64; |
1216 | break; |
1217 | case BFD_RELOC_X86_64_TPOFF32: |
1218 | other = BFD_RELOC_X86_64_TPOFF64; |
1219 | break; |
1220 | case BFD_RELOC_X86_64_DTPOFF32: |
1221 | other = BFD_RELOC_X86_64_DTPOFF64; |
1222 | break; |
1223 | default: |
1224 | break; |
1225 | } |
1226 | |
1227 | /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */ |
1228 | if (size == 4 && flag_code != CODE_64BIT) |
1229 | sign = -1; |
1230 | |
1231 | reloc = bfd_reloc_type_lookup (stdoutput, other); |
1232 | if (!reloc) |
1233 | as_bad (_("unknown relocation (%u)")("unknown relocation (%u)"), other); |
1234 | else if (size != bfd_get_reloc_size (reloc)) |
1235 | as_bad (_("%u-byte relocation cannot be applied to %u-byte field")("%u-byte relocation cannot be applied to %u-byte field"), |
1236 | bfd_get_reloc_size (reloc), |
1237 | size); |
1238 | else if (pcrel && !reloc->pc_relative) |
1239 | as_bad (_("non-pc-relative relocation for pc-relative field")("non-pc-relative relocation for pc-relative field")); |
1240 | else if ((reloc->complain_on_overflow == complain_overflow_signed |
1241 | && !sign) |
1242 | || (reloc->complain_on_overflow == complain_overflow_unsigned |
1243 | && sign > 0)) |
1244 | as_bad (_("relocated field and relocation type differ in signedness")("relocated field and relocation type differ in signedness")); |
1245 | else |
1246 | return other; |
1247 | return NO_RELOCBFD_RELOC_NONE; |
1248 | } |
1249 | |
1250 | if (pcrel) |
1251 | { |
1252 | if (!sign) |
1253 | as_bad (_("there are no unsigned pc-relative relocations")("there are no unsigned pc-relative relocations")); |
1254 | switch (size) |
1255 | { |
1256 | case 1: return BFD_RELOC_8_PCREL; |
1257 | case 2: return BFD_RELOC_16_PCREL; |
1258 | case 4: return BFD_RELOC_32_PCREL; |
1259 | case 8: return BFD_RELOC_64_PCREL; |
1260 | } |
1261 | as_bad (_("cannot do %u byte pc-relative relocation")("cannot do %u byte pc-relative relocation"), size); |
1262 | } |
1263 | else |
1264 | { |
1265 | if (sign > 0) |
1266 | switch (size) |
1267 | { |
1268 | case 4: return BFD_RELOC_X86_64_32S; |
1269 | } |
1270 | else |
1271 | switch (size) |
1272 | { |
1273 | case 1: return BFD_RELOC_8; |
1274 | case 2: return BFD_RELOC_16; |
1275 | case 4: return BFD_RELOC_32; |
1276 | case 8: return BFD_RELOC_64; |
1277 | } |
1278 | as_bad (_("cannot do %s %u byte relocation")("cannot do %s %u byte relocation"), |
1279 | sign > 0 ? "signed" : "unsigned", size); |
1280 | } |
1281 | |
1282 | abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 1282, __PRETTY_FUNCTION__); |
1283 | return BFD_RELOC_NONE; |
1284 | } |
1285 | |
1286 | /* Here we decide which fixups can be adjusted to make them relative to |
1287 | the beginning of the section instead of the symbol. Basically we need |
1288 | to make sure that the dynamic relocations are done correctly, so in |
1289 | some cases we force the original symbol to be used. */ |
1290 | |
1291 | int |
1292 | tc_i386_fix_adjustable (fixP) |
1293 | fixS *fixP ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
1294 | { |
1295 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
1296 | if (!IS_ELF1) |
1297 | return 1; |
1298 | |
1299 | /* Don't adjust pc-relative references to merge sections in 64-bit |
1300 | mode. */ |
1301 | if (use_rela_relocations |
1302 | && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE0x1000000) != 0 |
1303 | && fixP->fx_pcrel) |
1304 | return 0; |
1305 | |
1306 | /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations |
1307 | and changed later by validate_fix. */ |
1308 | if (GOT_symbol && fixP->fx_subsy == GOT_symbol |
1309 | && fixP->fx_r_type == BFD_RELOC_32_PCREL) |
1310 | return 0; |
1311 | |
1312 | /* adjust_reloc_syms doesn't know about the GOT. */ |
1313 | if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF |
1314 | || fixP->fx_r_type == BFD_RELOC_386_PLT32 |
1315 | || fixP->fx_r_type == BFD_RELOC_386_GOT32 |
1316 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GD |
1317 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM |
1318 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32 |
1319 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32 |
1320 | || fixP->fx_r_type == BFD_RELOC_386_TLS_IE |
1321 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE |
1322 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32 |
1323 | || fixP->fx_r_type == BFD_RELOC_386_TLS_LE |
1324 | || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTDESC |
1325 | || fixP->fx_r_type == BFD_RELOC_386_TLS_DESC_CALL |
1326 | || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32 |
1327 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32 |
1328 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL |
1329 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD |
1330 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD |
1331 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32 |
1332 | || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF64 |
1333 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF |
1334 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32 |
1335 | || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF64 |
1336 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTOFF64 |
1337 | || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPC32_TLSDESC |
1338 | || fixP->fx_r_type == BFD_RELOC_X86_64_TLSDESC_CALL |
1339 | || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT |
1340 | || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
1341 | return 0; |
1342 | #endif |
1343 | return 1; |
1344 | } |
1345 | |
1346 | static int intel_float_operand PARAMS ((const char *mnemonic))(const char *mnemonic); |
1347 | |
1348 | static int |
1349 | intel_float_operand (mnemonic) |
1350 | const char *mnemonic; |
1351 | { |
1352 | /* Note that the value returned is meaningful only for opcodes with (memory) |
1353 | operands, hence the code here is free to improperly handle opcodes that |
1354 | have no operands (for better performance and smaller code). */ |
1355 | |
1356 | if (mnemonic[0] != 'f') |
1357 | return 0; /* non-math */ |
1358 | |
1359 | switch (mnemonic[1]) |
1360 | { |
1361 | /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and |
1362 | the fs segment override prefix not currently handled because no |
1363 | call path can make opcodes without operands get here */ |
1364 | case 'i': |
1365 | return 2 /* integer op */; |
1366 | case 'l': |
1367 | if (mnemonic[2] == 'd' && (mnemonic[3] == 'c' || mnemonic[3] == 'e')) |
1368 | return 3; /* fldcw/fldenv */ |
1369 | break; |
1370 | case 'n': |
1371 | if (mnemonic[2] != 'o' /* fnop */) |
1372 | return 3; /* non-waiting control op */ |
1373 | break; |
1374 | case 'r': |
1375 | if (mnemonic[2] == 's') |
1376 | return 3; /* frstor/frstpm */ |
1377 | break; |
1378 | case 's': |
1379 | if (mnemonic[2] == 'a') |
1380 | return 3; /* fsave */ |
1381 | if (mnemonic[2] == 't') |
1382 | { |
1383 | switch (mnemonic[3]) |
1384 | { |
1385 | case 'c': /* fstcw */ |
1386 | case 'd': /* fstdw */ |
1387 | case 'e': /* fstenv */ |
1388 | case 's': /* fsts[gw] */ |
1389 | return 3; |
1390 | } |
1391 | } |
1392 | break; |
1393 | case 'x': |
1394 | if (mnemonic[2] == 'r' || mnemonic[2] == 's') |
1395 | return 0; /* fxsave/fxrstor are not really math ops */ |
1396 | break; |
1397 | } |
1398 | |
1399 | return 1; |
1400 | } |
1401 | |
1402 | /* This is the guts of the machine-dependent assembler. LINE points to a |
1403 | machine dependent instruction. This function is supposed to emit |
1404 | the frags/bytes it assembles to. */ |
1405 | |
1406 | void |
1407 | md_assemble (line) |
1408 | char *line; |
1409 | { |
1410 | int j; |
1411 | char mnemonic[MAX_MNEM_SIZE16]; |
1412 | |
1413 | /* Initialize globals. */ |
1414 | memset (&i, '\0', sizeof (i)); |
1415 | for (j = 0; j < MAX_OPERANDS3; j++) |
1416 | i.reloc[j] = NO_RELOCBFD_RELOC_NONE; |
1417 | memset (disp_expressions, '\0', sizeof (disp_expressions)); |
1418 | memset (im_expressions, '\0', sizeof (im_expressions)); |
1419 | save_stack_p = save_stack; |
1420 | |
1421 | /* First parse an instruction mnemonic & call i386_operand for the operands. |
1422 | We assume that the scrubber has arranged it so that line[0] is the valid |
1423 | start of a (possibly prefixed) mnemonic. */ |
1424 | |
1425 | line = parse_insn (line, mnemonic); |
1426 | if (line == NULL((void*)0)) |
1427 | return; |
1428 | |
1429 | line = parse_operands (line, mnemonic); |
1430 | if (line == NULL((void*)0)) |
1431 | return; |
1432 | |
1433 | /* Now we've parsed the mnemonic into a set of templates, and have the |
1434 | operands at hand. */ |
1435 | |
1436 | /* All intel opcodes have reversed operands except for "bound" and |
1437 | "enter". We also don't reverse intersegment "jmp" and "call" |
1438 | instructions with 2 immediate operands so that the immediate segment |
1439 | precedes the offset, as it does when in AT&T mode. "enter" and the |
1440 | intersegment "jmp" and "call" instructions are the only ones that |
1441 | have two immediate operands. */ |
1442 | if (intel_syntax && i.operands > 1 |
1443 | && (strcmp (mnemonic, "bound") != 0) |
1444 | && (strcmp (mnemonic, "invlpga") != 0) |
1445 | && !((i.types[0] & Imm(0x10|0x20|0x40|0x100|0x80|0x200)) && (i.types[1] & Imm(0x10|0x20|0x40|0x100|0x80|0x200)))) |
1446 | swap_operands (); |
1447 | |
1448 | if (i.imm_operands) |
1449 | optimize_imm (); |
1450 | |
1451 | /* Don't optimize displacement for movabs since it only takes 64bit |
1452 | displacement. */ |
1453 | if (i.disp_operands |
1454 | && (flag_code != CODE_64BIT |
1455 | || strcmp (mnemonic, "movabs") != 0)) |
1456 | optimize_disp (); |
1457 | |
1458 | /* Next, we find a template that matches the given insn, |
1459 | making sure the overlap of the given operands types is consistent |
1460 | with the template operand types. */ |
1461 | |
1462 | if (!match_template ()) |
1463 | return; |
1464 | |
1465 | if (intel_syntax) |
1466 | { |
1467 | /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */ |
1468 | if (SYSV386_COMPAT1 |
1469 | && (i.tm.base_opcode & 0xfffffde0) == 0xdce0) |
1470 | i.tm.base_opcode ^= FloatR0x8; |
1471 | |
1472 | /* Zap movzx and movsx suffix. The suffix may have been set from |
1473 | "word ptr" or "byte ptr" on the source operand, but we'll use |
1474 | the suffix later to choose the destination register. */ |
1475 | if ((i.tm.base_opcode & ~9) == 0x0fb6) |
1476 | { |
1477 | if (i.reg_operands < 2 |
1478 | && !i.suffix |
1479 | && (~i.tm.opcode_modifier |
1480 | & (No_bSuf0x40000 |
1481 | | No_wSuf0x80000 |
1482 | | No_lSuf0x100000 |
1483 | | No_sSuf0x200000 |
1484 | | No_xSuf0x800000 |
1485 | | No_qSuf0x400000))) |
1486 | as_bad (_("ambiguous operand size for `%s'")("ambiguous operand size for `%s'"), i.tm.name); |
1487 | |
1488 | i.suffix = 0; |
1489 | } |
1490 | } |
1491 | |
1492 | if (i.tm.opcode_modifier & FWait0x1000000) |
1493 | if (!add_prefix (FWAIT_OPCODE0x9b)) |
1494 | return; |
1495 | |
1496 | /* Check string instruction segment overrides. */ |
1497 | if ((i.tm.opcode_modifier & IsString0x2000000) != 0 && i.mem_operands != 0) |
1498 | { |
1499 | if (!check_string ()) |
1500 | return; |
1501 | } |
1502 | |
1503 | if (!process_suffix ()) |
1504 | return; |
1505 | |
1506 | /* Make still unresolved immediate matches conform to size of immediate |
1507 | given in i.suffix. */ |
1508 | if (!finalize_imm ()) |
1509 | return; |
1510 | |
1511 | if (i.types[0] & Imm10x400) |
1512 | i.imm_operands = 0; /* kludge for shift insns. */ |
1513 | if (i.types[0] & ImplicitRegister(0x20000|0x40000|0x4000000|0x800000)) |
1514 | i.reg_operands--; |
1515 | if (i.types[1] & ImplicitRegister(0x20000|0x40000|0x4000000|0x800000)) |
1516 | i.reg_operands--; |
1517 | if (i.types[2] & ImplicitRegister(0x20000|0x40000|0x4000000|0x800000)) |
1518 | i.reg_operands--; |
1519 | |
1520 | if (i.tm.opcode_modifier & ImmExt0x10000000) |
1521 | { |
1522 | expressionS *exp; |
1523 | |
1524 | if ((i.tm.cpu_flags & (CpuPNI0x20000|CpuXSAVE0x400000|CpuSMAP0x4000000)) && i.operands > 0) |
1525 | { |
1526 | /* These Intel Prescott New Instructions have the fixed |
1527 | operands with an opcode suffix which is coded in the same |
1528 | place as an 8-bit immediate field would be. Here we check |
1529 | those operands and remove them afterwards. */ |
1530 | unsigned int x; |
1531 | |
1532 | for (x = 0; x < i.operands; x++) |
1533 | if (i.op[x].regs->reg_num != x) |
1534 | as_bad (_("can't use register '%%%s' as operand %d in '%s'.")("can't use register '%%%s' as operand %d in '%s'."), |
1535 | i.op[x].regs->reg_name, x + 1, i.tm.name); |
1536 | i.operands = 0; |
1537 | } |
1538 | |
1539 | /* These AMD 3DNow! and Intel Katmai New Instructions have an |
1540 | opcode suffix which is coded in the same place as an 8-bit |
1541 | immediate field would be. Here we fake an 8-bit immediate |
1542 | operand from the opcode suffix stored in tm.extension_opcode. */ |
1543 | |
1544 | assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS)((void) ((i.imm_operands == 0 && i.operands <= 2 && 2 < 3) ? 0 : (as_assert ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 1544, __PRETTY_FUNCTION__), 0))); |
1545 | |
1546 | exp = &im_expressions[i.imm_operands++]; |
1547 | i.op[i.operands].imms = exp; |
1548 | i.types[i.operands++] = Imm80x10; |
1549 | exp->X_op = O_constant; |
1550 | exp->X_add_number = i.tm.extension_opcode; |
1551 | i.tm.extension_opcode = None0xffff; |
1552 | } |
1553 | |
1554 | /* For insns with operands there are more diddles to do to the opcode. */ |
1555 | if (i.operands) |
1556 | { |
1557 | if (!process_operands ()) |
1558 | return; |
1559 | } |
1560 | else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh0x80000000) != 0) |
1561 | { |
1562 | /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */ |
1563 | as_warn (_("translating to `%sp'")("translating to `%sp'"), i.tm.name); |
1564 | } |
1565 | |
1566 | /* Handle conversion of 'int $3' --> special int3 insn. */ |
1567 | if (i.tm.base_opcode == INT_OPCODE0xcd && i.op[0].imms->X_add_number == 3) |
1568 | { |
1569 | i.tm.base_opcode = INT3_OPCODE0xcc; |
1570 | i.imm_operands = 0; |
1571 | } |
1572 | |
1573 | if ((i.tm.opcode_modifier & (Jump0x40 | JumpByte0x100 | JumpDword0x80)) |
1574 | && i.op[0].disps->X_op == O_constant) |
1575 | { |
1576 | /* Convert "jmp constant" (and "call constant") to a jump (call) to |
1577 | the absolute address given by the constant. Since ix86 jumps and |
1578 | calls are pc relative, we need to generate a reloc. */ |
1579 | i.op[0].disps->X_add_symbol = &abs_symbol; |
1580 | i.op[0].disps->X_op = O_symbol; |
1581 | } |
1582 | |
1583 | if ((i.tm.opcode_modifier & Rex640x40000000) != 0) |
1584 | i.rex |= REX_MODE648; |
1585 | |
1586 | /* For 8 bit registers we need an empty rex prefix. Also if the |
1587 | instruction already has a prefix, we need to convert old |
1588 | registers to new ones. */ |
1589 | |
1590 | if (((i.types[0] & Reg80x1) != 0 |
1591 | && (i.op[0].regs->reg_flags & RegRex640x2) != 0) |
1592 | || ((i.types[1] & Reg80x1) != 0 |
1593 | && (i.op[1].regs->reg_flags & RegRex640x2) != 0) |
1594 | || (((i.types[0] & Reg80x1) != 0 || (i.types[1] & Reg80x1) != 0) |
1595 | && i.rex != 0)) |
1596 | { |
1597 | int x; |
1598 | |
1599 | i.rex |= REX_OPCODE0x40; |
1600 | for (x = 0; x < 2; x++) |
1601 | { |
1602 | /* Look for 8 bit operand that uses old registers. */ |
1603 | if ((i.types[x] & Reg80x1) != 0 |
1604 | && (i.op[x].regs->reg_flags & RegRex640x2) == 0) |
1605 | { |
1606 | /* In case it is "hi" register, give up. */ |
1607 | if (i.op[x].regs->reg_num > 3) |
1608 | as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.")("can't encode register '%%%s' in an instruction requiring REX prefix." ), |
1609 | i.op[x].regs->reg_name); |
1610 | |
1611 | /* Otherwise it is equivalent to the extended register. |
1612 | Since the encoding doesn't change this is merely |
1613 | cosmetic cleanup for debug output. */ |
1614 | |
1615 | i.op[x].regs = i.op[x].regs + 8; |
1616 | } |
1617 | } |
1618 | } |
1619 | |
1620 | if (i.rex != 0) |
1621 | add_prefix (REX_OPCODE0x40 | i.rex); |
1622 | |
1623 | /* We are ready to output the insn. */ |
1624 | output_insn (); |
1625 | } |
1626 | |
1627 | static char * |
1628 | parse_insn (line, mnemonic) |
1629 | char *line; |
1630 | char *mnemonic; |
1631 | { |
1632 | char *l = line; |
1633 | char *token_start = l; |
1634 | char *mnem_p; |
1635 | int supported; |
1636 | const template *t; |
1637 | |
1638 | /* Non-zero if we found a prefix only acceptable with string insns. */ |
1639 | const char *expecting_string_instruction = NULL((void*)0); |
1640 | |
1641 | while (1) |
1642 | { |
1643 | mnem_p = mnemonic; |
1644 | while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0) |
1645 | { |
1646 | mnem_p++; |
1647 | if (mnem_p >= mnemonic + MAX_MNEM_SIZE16) |
1648 | { |
1649 | as_bad (_("no such instruction: `%s'")("no such instruction: `%s'"), token_start); |
1650 | return NULL((void*)0); |
1651 | } |
1652 | l++; |
1653 | } |
1654 | if (!is_space_char (*l)((*l) == ' ') |
1655 | && *l != END_OF_INSN'\0' |
1656 | && (intel_syntax |
1657 | || (*l != PREFIX_SEPARATOR'/' |
1658 | && *l != ','))) |
1659 | { |
1660 | as_bad (_("invalid character %s in mnemonic")("invalid character %s in mnemonic"), |
1661 | output_invalid (*l)); |
1662 | return NULL((void*)0); |
1663 | } |
1664 | if (token_start == l) |
1665 | { |
1666 | if (!intel_syntax && *l == PREFIX_SEPARATOR'/') |
1667 | as_bad (_("expecting prefix; got nothing")("expecting prefix; got nothing")); |
1668 | else |
1669 | as_bad (_("expecting mnemonic; got nothing")("expecting mnemonic; got nothing")); |
1670 | return NULL((void*)0); |
1671 | } |
1672 | |
1673 | /* Look up instruction (or prefix) via hash table. */ |
1674 | current_templates = hash_find (op_hash, mnemonic); |
1675 | |
1676 | if (*l != END_OF_INSN'\0' |
1677 | && (!is_space_char (*l)((*l) == ' ') || l[1] != END_OF_INSN'\0') |
1678 | && current_templates |
1679 | && (current_templates->start->opcode_modifier & IsPrefix0x8000000)) |
1680 | { |
1681 | if (current_templates->start->cpu_flags |
1682 | & (flag_code != CODE_64BIT ? Cpu640x8000000 : CpuNo640x10000000)) |
1683 | { |
1684 | as_bad ((flag_code != CODE_64BIT |
1685 | ? _("`%s' is only supported in 64-bit mode")("`%s' is only supported in 64-bit mode") |
1686 | : _("`%s' is not supported in 64-bit mode")("`%s' is not supported in 64-bit mode")), |
1687 | current_templates->start->name); |
1688 | return NULL((void*)0); |
1689 | } |
1690 | /* If we are in 16-bit mode, do not allow addr16 or data16. |
1691 | Similarly, in 32-bit mode, do not allow addr32 or data32. */ |
1692 | if ((current_templates->start->opcode_modifier & (Size160x2000 | Size320x4000)) |
1693 | && flag_code != CODE_64BIT |
1694 | && (((current_templates->start->opcode_modifier & Size320x4000) != 0) |
1695 | ^ (flag_code == CODE_16BIT))) |
1696 | { |
1697 | as_bad (_("redundant %s prefix")("redundant %s prefix"), |
1698 | current_templates->start->name); |
1699 | return NULL((void*)0); |
1700 | } |
1701 | /* Add prefix, checking for repeated prefixes. */ |
1702 | switch (add_prefix (current_templates->start->base_opcode)) |
1703 | { |
1704 | case 0: |
1705 | return NULL((void*)0); |
1706 | case 2: |
1707 | expecting_string_instruction = current_templates->start->name; |
1708 | break; |
1709 | } |
1710 | /* Skip past PREFIX_SEPARATOR and reset token_start. */ |
1711 | token_start = ++l; |
1712 | } |
1713 | else |
1714 | break; |
1715 | } |
1716 | |
1717 | if (!current_templates) |
1718 | { |
1719 | /* See if we can get a match by trimming off a suffix. */ |
1720 | switch (mnem_p[-1]) |
1721 | { |
1722 | case WORD_MNEM_SUFFIX'w': |
1723 | if (intel_syntax && (intel_float_operand (mnemonic) & 2)) |
1724 | i.suffix = SHORT_MNEM_SUFFIX's'; |
1725 | else |
1726 | case BYTE_MNEM_SUFFIX'b': |
1727 | case QWORD_MNEM_SUFFIX'q': |
1728 | i.suffix = mnem_p[-1]; |
1729 | mnem_p[-1] = '\0'; |
1730 | current_templates = hash_find (op_hash, mnemonic); |
1731 | break; |
1732 | case SHORT_MNEM_SUFFIX's': |
1733 | case LONG_MNEM_SUFFIX'l': |
1734 | if (!intel_syntax) |
1735 | { |
1736 | i.suffix = mnem_p[-1]; |
1737 | mnem_p[-1] = '\0'; |
1738 | current_templates = hash_find (op_hash, mnemonic); |
1739 | } |
1740 | break; |
1741 | |
1742 | /* Intel Syntax. */ |
1743 | case 'd': |
1744 | if (intel_syntax) |
1745 | { |
1746 | if (intel_float_operand (mnemonic) == 1) |
1747 | i.suffix = SHORT_MNEM_SUFFIX's'; |
1748 | else |
1749 | i.suffix = LONG_MNEM_SUFFIX'l'; |
1750 | mnem_p[-1] = '\0'; |
1751 | current_templates = hash_find (op_hash, mnemonic); |
1752 | } |
1753 | break; |
1754 | } |
1755 | if (!current_templates) |
1756 | { |
1757 | as_bad (_("no such instruction: `%s'")("no such instruction: `%s'"), token_start); |
1758 | return NULL((void*)0); |
1759 | } |
1760 | } |
1761 | |
1762 | if (current_templates->start->opcode_modifier & (Jump0x40 | JumpByte0x100)) |
1763 | { |
1764 | /* Check for a branch hint. We allow ",pt" and ",pn" for |
1765 | predict taken and predict not taken respectively. |
1766 | I'm not sure that branch hints actually do anything on loop |
1767 | and jcxz insns (JumpByte) for current Pentium4 chips. They |
1768 | may work in the future and it doesn't hurt to accept them |
1769 | now. */ |
1770 | if (l[0] == ',' && l[1] == 'p') |
1771 | { |
1772 | if (l[2] == 't') |
1773 | { |
1774 | if (!add_prefix (DS_PREFIX_OPCODE0x3e)) |
1775 | return NULL((void*)0); |
1776 | l += 3; |
1777 | } |
1778 | else if (l[2] == 'n') |
1779 | { |
1780 | if (!add_prefix (CS_PREFIX_OPCODE0x2e)) |
1781 | return NULL((void*)0); |
1782 | l += 3; |
1783 | } |
1784 | } |
1785 | } |
1786 | /* Any other comma loses. */ |
1787 | if (*l == ',') |
1788 | { |
1789 | as_bad (_("invalid character %s in mnemonic")("invalid character %s in mnemonic"), |
1790 | output_invalid (*l)); |
1791 | return NULL((void*)0); |
1792 | } |
1793 | |
1794 | /* Check if instruction is supported on specified architecture. */ |
1795 | supported = 0; |
1796 | for (t = current_templates->start; t < current_templates->end; ++t) |
1797 | { |
1798 | if (!((t->cpu_flags & ~(Cpu640x8000000 | CpuNo640x10000000)) |
1799 | & ~(cpu_arch_flags & ~(Cpu640x8000000 | CpuNo640x10000000)))) |
1800 | supported |= 1; |
1801 | if (!(t->cpu_flags & (flag_code == CODE_64BIT ? CpuNo640x10000000 : Cpu640x8000000))) |
1802 | supported |= 2; |
1803 | } |
1804 | if (!(supported & 2)) |
1805 | { |
1806 | as_bad (flag_code == CODE_64BIT |
1807 | ? _("`%s' is not supported in 64-bit mode")("`%s' is not supported in 64-bit mode") |
1808 | : _("`%s' is only supported in 64-bit mode")("`%s' is only supported in 64-bit mode"), |
1809 | current_templates->start->name); |
1810 | return NULL((void*)0); |
1811 | } |
1812 | if (!(supported & 1)) |
1813 | { |
1814 | as_warn (_("`%s' is not supported on `%s%s'")("`%s' is not supported on `%s%s'"), |
1815 | current_templates->start->name, |
1816 | cpu_arch_name, |
1817 | cpu_sub_arch_name ? cpu_sub_arch_name : ""); |
1818 | } |
1819 | else if ((Cpu3860x8 & ~cpu_arch_flags) && (flag_code != CODE_16BIT)) |
1820 | { |
1821 | as_warn (_("use .code16 to ensure correct addressing mode")("use .code16 to ensure correct addressing mode")); |
1822 | } |
1823 | |
1824 | /* Check for rep/repne without a string instruction. */ |
1825 | if (expecting_string_instruction) |
1826 | { |
1827 | static templates override; |
1828 | |
1829 | for (t = current_templates->start; t < current_templates->end; ++t) |
1830 | if (t->opcode_modifier & IsString0x2000000) |
1831 | break; |
1832 | if (t >= current_templates->end) |
1833 | { |
1834 | as_bad (_("expecting string instruction after `%s'")("expecting string instruction after `%s'"), |
1835 | expecting_string_instruction); |
1836 | return NULL((void*)0); |
1837 | } |
1838 | for (override.start = t; t < current_templates->end; ++t) |
1839 | if (!(t->opcode_modifier & IsString0x2000000)) |
1840 | break; |
1841 | override.end = t; |
1842 | current_templates = &override; |
1843 | } |
1844 | |
1845 | return l; |
1846 | } |
1847 | |
1848 | static char * |
1849 | parse_operands (l, mnemonic) |
1850 | char *l; |
1851 | const char *mnemonic; |
1852 | { |
1853 | char *token_start; |
1854 | |
1855 | /* 1 if operand is pending after ','. */ |
1856 | unsigned int expecting_operand = 0; |
1857 | |
1858 | /* Non-zero if operand parens not balanced. */ |
1859 | unsigned int paren_not_balanced; |
1860 | |
1861 | while (*l != END_OF_INSN'\0') |
1862 | { |
1863 | /* Skip optional white space before operand. */ |
1864 | if (is_space_char (*l)((*l) == ' ')) |
1865 | ++l; |
1866 | if (!is_operand_char (*l)(operand_chars[(unsigned char) *l]) && *l != END_OF_INSN'\0') |
1867 | { |
1868 | as_bad (_("invalid character %s before operand %d")("invalid character %s before operand %d"), |
1869 | output_invalid (*l), |
1870 | i.operands + 1); |
1871 | return NULL((void*)0); |
1872 | } |
1873 | token_start = l; /* after white space */ |
1874 | paren_not_balanced = 0; |
1875 | while (paren_not_balanced || *l != ',') |
1876 | { |
1877 | if (*l == END_OF_INSN'\0') |
1878 | { |
1879 | if (paren_not_balanced) |
1880 | { |
1881 | if (!intel_syntax) |
1882 | as_bad (_("unbalanced parenthesis in operand %d.")("unbalanced parenthesis in operand %d."), |
1883 | i.operands + 1); |
1884 | else |
1885 | as_bad (_("unbalanced brackets in operand %d.")("unbalanced brackets in operand %d."), |
1886 | i.operands + 1); |
1887 | return NULL((void*)0); |
1888 | } |
1889 | else |
1890 | break; /* we are done */ |
1891 | } |
1892 | else if (!is_operand_char (*l)(operand_chars[(unsigned char) *l]) && !is_space_char (*l)((*l) == ' ')) |
1893 | { |
1894 | as_bad (_("invalid character %s in operand %d")("invalid character %s in operand %d"), |
1895 | output_invalid (*l), |
1896 | i.operands + 1); |
1897 | return NULL((void*)0); |
1898 | } |
1899 | if (!intel_syntax) |
1900 | { |
1901 | if (*l == '(') |
1902 | ++paren_not_balanced; |
1903 | if (*l == ')') |
1904 | --paren_not_balanced; |
1905 | } |
1906 | else |
1907 | { |
1908 | if (*l == '[') |
1909 | ++paren_not_balanced; |
1910 | if (*l == ']') |
1911 | --paren_not_balanced; |
1912 | } |
1913 | l++; |
1914 | } |
1915 | if (l != token_start) |
1916 | { /* Yes, we've read in another operand. */ |
1917 | unsigned int operand_ok; |
1918 | this_operand = i.operands++; |
1919 | if (i.operands > MAX_OPERANDS3) |
1920 | { |
1921 | as_bad (_("spurious operands; (%d operands/instruction max)")("spurious operands; (%d operands/instruction max)"), |
1922 | MAX_OPERANDS3); |
1923 | return NULL((void*)0); |
1924 | } |
1925 | /* Now parse operand adding info to 'i' as we go along. */ |
1926 | END_STRING_AND_SAVE (l)do { *save_stack_p++ = *(l); *(l) = '\0'; } while (0); |
1927 | |
1928 | if (intel_syntax) |
1929 | operand_ok = |
1930 | i386_intel_operand (token_start, |
1931 | intel_float_operand (mnemonic)); |
1932 | else |
1933 | operand_ok = i386_operand (token_start); |
1934 | |
1935 | RESTORE_END_STRING (l)do { *(l) = *--save_stack_p; } while (0); |
1936 | if (!operand_ok) |
1937 | return NULL((void*)0); |
1938 | } |
1939 | else |
1940 | { |
1941 | if (expecting_operand) |
1942 | { |
1943 | expecting_operand_after_comma: |
1944 | as_bad (_("expecting operand after ','; got nothing")("expecting operand after ','; got nothing")); |
1945 | return NULL((void*)0); |
1946 | } |
1947 | if (*l == ',') |
1948 | { |
1949 | as_bad (_("expecting operand before ','; got nothing")("expecting operand before ','; got nothing")); |
1950 | return NULL((void*)0); |
1951 | } |
1952 | } |
1953 | |
1954 | /* Now *l must be either ',' or END_OF_INSN. */ |
1955 | if (*l == ',') |
1956 | { |
1957 | if (*++l == END_OF_INSN'\0') |
1958 | { |
1959 | /* Just skip it, if it's \n complain. */ |
1960 | goto expecting_operand_after_comma; |
1961 | } |
1962 | expecting_operand = 1; |
1963 | } |
1964 | } |
1965 | return l; |
1966 | } |
1967 | |
1968 | static void |
1969 | swap_operands () |
1970 | { |
1971 | union i386_op temp_op; |
1972 | unsigned int temp_type; |
1973 | enum bfd_reloc_code_real temp_reloc; |
1974 | int xchg1 = 0; |
1975 | int xchg2 = 0; |
1976 | |
1977 | if (i.operands == 2) |
1978 | { |
1979 | xchg1 = 0; |
1980 | xchg2 = 1; |
1981 | } |
1982 | else if (i.operands == 3) |
1983 | { |
1984 | xchg1 = 0; |
1985 | xchg2 = 2; |
1986 | } |
1987 | temp_type = i.types[xchg2]; |
1988 | i.types[xchg2] = i.types[xchg1]; |
1989 | i.types[xchg1] = temp_type; |
1990 | temp_op = i.op[xchg2]; |
1991 | i.op[xchg2] = i.op[xchg1]; |
1992 | i.op[xchg1] = temp_op; |
1993 | temp_reloc = i.reloc[xchg2]; |
1994 | i.reloc[xchg2] = i.reloc[xchg1]; |
1995 | i.reloc[xchg1] = temp_reloc; |
1996 | |
1997 | if (i.mem_operands == 2) |
1998 | { |
1999 | const seg_entry *temp_seg; |
2000 | temp_seg = i.seg[0]; |
2001 | i.seg[0] = i.seg[1]; |
2002 | i.seg[1] = temp_seg; |
2003 | } |
2004 | } |
2005 | |
2006 | /* Try to ensure constant immediates are represented in the smallest |
2007 | opcode possible. */ |
2008 | static void |
2009 | optimize_imm () |
2010 | { |
2011 | char guess_suffix = 0; |
2012 | int op; |
2013 | |
2014 | if (i.suffix) |
2015 | guess_suffix = i.suffix; |
2016 | else if (i.reg_operands) |
2017 | { |
2018 | /* Figure out a suffix from the last register operand specified. |
2019 | We can't do this properly yet, ie. excluding InOutPortReg, |
2020 | but the following works for instructions with immediates. |
2021 | In any case, we can't set i.suffix yet. */ |
2022 | for (op = i.operands; --op >= 0;) |
2023 | if (i.types[op] & Reg(0x1|0x2|0x4|0x8)) |
2024 | { |
2025 | if (i.types[op] & Reg80x1) |
2026 | guess_suffix = BYTE_MNEM_SUFFIX'b'; |
2027 | else if (i.types[op] & Reg160x2) |
2028 | guess_suffix = WORD_MNEM_SUFFIX'w'; |
2029 | else if (i.types[op] & Reg320x4) |
2030 | guess_suffix = LONG_MNEM_SUFFIX'l'; |
2031 | else if (i.types[op] & Reg640x8) |
2032 | guess_suffix = QWORD_MNEM_SUFFIX'q'; |
2033 | break; |
2034 | } |
2035 | } |
2036 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX3] != 0)) |
2037 | guess_suffix = WORD_MNEM_SUFFIX'w'; |
2038 | |
2039 | for (op = i.operands; --op >= 0;) |
2040 | if (i.types[op] & Imm(0x10|0x20|0x40|0x100|0x80|0x200)) |
2041 | { |
2042 | switch (i.op[op].imms->X_op) |
2043 | { |
2044 | case O_constant: |
2045 | /* If a suffix is given, this operand may be shortened. */ |
2046 | switch (guess_suffix) |
2047 | { |
2048 | case LONG_MNEM_SUFFIX'l': |
2049 | i.types[op] |= Imm320x80 | Imm640x200; |
2050 | break; |
2051 | case WORD_MNEM_SUFFIX'w': |
2052 | i.types[op] |= Imm160x40 | Imm32S0x100 | Imm320x80 | Imm640x200; |
2053 | break; |
2054 | case BYTE_MNEM_SUFFIX'b': |
2055 | i.types[op] |= Imm160x40 | Imm80x10 | Imm8S0x20 | Imm32S0x100 | Imm320x80 | Imm640x200; |
2056 | break; |
2057 | } |
2058 | |
2059 | /* If this operand is at most 16 bits, convert it |
2060 | to a signed 16 bit number before trying to see |
2061 | whether it will fit in an even smaller size. |
2062 | This allows a 16-bit operand such as $0xffe0 to |
2063 | be recognised as within Imm8S range. */ |
2064 | if ((i.types[op] & Imm160x40) |
2065 | && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0) |
2066 | { |
2067 | i.op[op].imms->X_add_number = |
2068 | (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000); |
2069 | } |
2070 | if ((i.types[op] & Imm320x80) |
2071 | && ((i.op[op].imms->X_add_number & ~(offsetT) 0xffffffffL) |
2072 | == 0)) |
2073 | { |
2074 | i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number |
2075 | ^ ((offsetT) 1 << 31)) |
2076 | - ((offsetT) 1 << 31)); |
2077 | } |
2078 | i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number); |
2079 | |
2080 | /* We must avoid matching of Imm32 templates when 64bit |
2081 | only immediate is available. */ |
2082 | if (guess_suffix == QWORD_MNEM_SUFFIX'q') |
2083 | i.types[op] &= ~Imm320x80; |
2084 | break; |
2085 | |
2086 | case O_absent: |
2087 | case O_register: |
2088 | abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 2088, __PRETTY_FUNCTION__); |
2089 | |
2090 | /* Symbols and expressions. */ |
2091 | default: |
2092 | /* Convert symbolic operand to proper sizes for matching, but don't |
2093 | prevent matching a set of insns that only supports sizes other |
2094 | than those matching the insn suffix. */ |
2095 | { |
2096 | unsigned int mask, allowed = 0; |
2097 | const template *t; |
2098 | |
2099 | for (t = current_templates->start; t < current_templates->end; ++t) |
2100 | allowed |= t->operand_types[op]; |
2101 | switch (guess_suffix) |
2102 | { |
2103 | case QWORD_MNEM_SUFFIX'q': |
2104 | mask = Imm640x200 | Imm32S0x100; |
2105 | break; |
2106 | case LONG_MNEM_SUFFIX'l': |
2107 | mask = Imm320x80; |
2108 | break; |
2109 | case WORD_MNEM_SUFFIX'w': |
2110 | mask = Imm160x40; |
2111 | break; |
2112 | case BYTE_MNEM_SUFFIX'b': |
2113 | mask = Imm80x10; |
2114 | break; |
2115 | default: |
2116 | mask = 0; |
2117 | break; |
2118 | } |
2119 | if (mask & allowed) |
2120 | i.types[op] &= mask; |
2121 | } |
2122 | break; |
2123 | } |
2124 | } |
2125 | } |
2126 | |
2127 | /* Try to use the smallest displacement type too. */ |
2128 | static void |
2129 | optimize_disp () |
2130 | { |
2131 | int op; |
2132 | |
2133 | for (op = i.operands; --op >= 0;) |
2134 | if (i.types[op] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000)) |
2135 | { |
2136 | if (i.op[op].disps->X_op == O_constant) |
2137 | { |
2138 | offsetT disp = i.op[op].disps->X_add_number; |
2139 | |
2140 | if ((i.types[op] & Disp160x2000) |
2141 | && (disp & ~(offsetT) 0xffff) == 0) |
2142 | { |
2143 | /* If this operand is at most 16 bits, convert |
2144 | to a signed 16 bit number and don't use 64bit |
2145 | displacement. */ |
2146 | disp = (((disp & 0xffff) ^ 0x8000) - 0x8000); |
2147 | i.types[op] &= ~Disp640x10000; |
2148 | } |
2149 | if ((i.types[op] & Disp320x4000) |
2150 | && (disp & ~(offsetT) 0xffffffffL) == 0) |
2151 | { |
2152 | /* If this operand is at most 32 bits, convert |
2153 | to a signed 32 bit number and don't use 64bit |
2154 | displacement. */ |
2155 | disp &= (offsetT) 0xffffffffL; |
2156 | disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31); |
2157 | i.types[op] &= ~Disp640x10000; |
2158 | } |
2159 | if (!disp && (i.types[op] & BaseIndex0x800)) |
2160 | { |
2161 | i.types[op] &= ~Disp(0x1000|0x2000|0x4000|0x8000|0x10000); |
2162 | i.op[op].disps = 0; |
2163 | i.disp_operands--; |
2164 | } |
2165 | else if (flag_code == CODE_64BIT) |
2166 | { |
2167 | if (fits_in_signed_long (disp)) |
2168 | { |
2169 | i.types[op] &= ~Disp640x10000; |
2170 | i.types[op] |= Disp32S0x8000; |
2171 | } |
2172 | if (fits_in_unsigned_long (disp)) |
2173 | i.types[op] |= Disp320x4000; |
2174 | } |
2175 | if ((i.types[op] & (Disp320x4000 | Disp32S0x8000 | Disp160x2000)) |
2176 | && fits_in_signed_byte (disp)) |
2177 | i.types[op] |= Disp80x1000; |
2178 | } |
2179 | else if (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
2180 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL) |
2181 | { |
2182 | fix_new_exp (frag_now, frag_more (0) - frag_now->fr_literal, 0, |
2183 | i.op[op].disps, 0, i.reloc[op]); |
2184 | i.types[op] &= ~Disp(0x1000|0x2000|0x4000|0x8000|0x10000); |
2185 | } |
2186 | else |
2187 | /* We only support 64bit displacement on constants. */ |
2188 | i.types[op] &= ~Disp640x10000; |
2189 | } |
2190 | } |
2191 | |
2192 | static int |
2193 | match_template () |
2194 | { |
2195 | /* Points to template once we've found it. */ |
2196 | const template *t; |
2197 | unsigned int overlap0, overlap1, overlap2; |
2198 | unsigned int found_reverse_match; |
2199 | int suffix_check; |
2200 | |
2201 | #define MATCH(overlap, given, template)((overlap & ~0x8000000) && (((given) & (0x800 | 0x8000000)) == ((overlap) & (0x800 | 0x8000000)))) \ |
2202 | ((overlap & ~JumpAbsolute0x8000000) \ |
2203 | && (((given) & (BaseIndex0x800 | JumpAbsolute0x8000000)) \ |
2204 | == ((overlap) & (BaseIndex0x800 | JumpAbsolute0x8000000)))) |
2205 | |
2206 | /* If given types r0 and r1 are registers they must be of the same type |
2207 | unless the expected operand type register overlap is null. |
2208 | Note that Acc in a template matches every size of reg. */ |
2209 | #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1)(((g0) & (0x1|0x2|0x4|0x8)) == 0 || ((g1) & (0x1|0x2| 0x4|0x8)) == 0 || ((g0) & (0x1|0x2|0x4|0x8)) == ((g1) & (0x1|0x2|0x4|0x8)) || ((((m0) & 0x4000000) ? (0x1|0x2|0x4 |0x8) : (t0)) & (((m1) & 0x4000000) ? (0x1|0x2|0x4|0x8 ) : (t1)) & (0x1|0x2|0x4|0x8)) == 0 ) \ |
2210 | (((g0) & Reg(0x1|0x2|0x4|0x8)) == 0 || ((g1) & Reg(0x1|0x2|0x4|0x8)) == 0 \ |
2211 | || ((g0) & Reg(0x1|0x2|0x4|0x8)) == ((g1) & Reg(0x1|0x2|0x4|0x8)) \ |
2212 | || ((((m0) & Acc0x4000000) ? Reg(0x1|0x2|0x4|0x8) : (t0)) & (((m1) & Acc0x4000000) ? Reg(0x1|0x2|0x4|0x8) : (t1)) & Reg(0x1|0x2|0x4|0x8)) == 0 ) |
2213 | |
2214 | overlap0 = 0; |
2215 | overlap1 = 0; |
2216 | overlap2 = 0; |
2217 | found_reverse_match = 0; |
2218 | suffix_check = (i.suffix == BYTE_MNEM_SUFFIX'b' |
2219 | ? No_bSuf0x40000 |
2220 | : (i.suffix == WORD_MNEM_SUFFIX'w' |
2221 | ? No_wSuf0x80000 |
2222 | : (i.suffix == SHORT_MNEM_SUFFIX's' |
2223 | ? No_sSuf0x200000 |
2224 | : (i.suffix == LONG_MNEM_SUFFIX'l' |
2225 | ? No_lSuf0x100000 |
2226 | : (i.suffix == QWORD_MNEM_SUFFIX'q' |
2227 | ? No_qSuf0x400000 |
2228 | : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX'x' |
2229 | ? No_xSuf0x800000 : 0)))))); |
2230 | |
2231 | for (t = current_templates->start; t < current_templates->end; t++) |
2232 | { |
2233 | /* Must have right number of operands. */ |
2234 | if (i.operands != t->operands) |
2235 | continue; |
2236 | |
2237 | /* Check the suffix, except for some instructions in intel mode. */ |
2238 | if ((t->opcode_modifier & suffix_check) |
2239 | && !(intel_syntax |
2240 | && (t->opcode_modifier & IgnoreSize0x10000))) |
2241 | continue; |
2242 | |
2243 | /* In general, don't allow 64-bit operands in 32-bit mode. */ |
2244 | if (i.suffix == QWORD_MNEM_SUFFIX'q' |
2245 | && flag_code != CODE_64BIT |
2246 | && (intel_syntax |
2247 | ? (!(t->opcode_modifier & IgnoreSize0x10000) |
2248 | && !intel_float_operand (t->name)) |
2249 | : intel_float_operand (t->name) != 2) |
2250 | && (!(t->operand_types[0] & (RegMMX0x10000000 | RegXMM0x20000000)) |
2251 | || !(t->operand_types[t->operands > 1] & (RegMMX0x10000000 | RegXMM0x20000000))) |
2252 | && (t->base_opcode != 0x0fc7 |
2253 | || t->extension_opcode != 1 /* cmpxchg8b */)) |
2254 | continue; |
2255 | |
2256 | /* Do not verify operands when there are none. */ |
2257 | else if (!t->operands) |
2258 | { |
2259 | if (t->cpu_flags & ~cpu_arch_flags) |
2260 | continue; |
2261 | /* We've found a match; break out of loop. */ |
2262 | break; |
2263 | } |
2264 | |
2265 | overlap0 = i.types[0] & t->operand_types[0]; |
2266 | switch (t->operands) |
2267 | { |
2268 | case 1: |
2269 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])((overlap0 & ~0x8000000) && (((i.types[0]) & ( 0x800 | 0x8000000)) == ((overlap0) & (0x800 | 0x8000000)) ))) |
2270 | continue; |
2271 | break; |
2272 | case 2: |
2273 | case 3: |
2274 | overlap1 = i.types[1] & t->operand_types[1]; |
2275 | if (!MATCH (overlap0, i.types[0], t->operand_types[0])((overlap0 & ~0x8000000) && (((i.types[0]) & ( 0x800 | 0x8000000)) == ((overlap0) & (0x800 | 0x8000000)) )) |
2276 | || !MATCH (overlap1, i.types[1], t->operand_types[1])((overlap1 & ~0x8000000) && (((i.types[1]) & ( 0x800 | 0x8000000)) == ((overlap1) & (0x800 | 0x8000000)) )) |
2277 | /* monitor in SSE3 is a very special case. The first |
2278 | register and the second register may have differnet |
2279 | sizes. */ |
2280 | || !((t->base_opcode == 0x0f01 |
2281 | && t->extension_opcode == 0xc8) |
2282 | || CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2 |0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0 ) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types [0])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types[1])) & (0x1|0x2|0x4|0x8)) == 0 ) |
2283 | t->operand_types[0],(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2 |0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0 ) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types [0])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types[1])) & (0x1|0x2|0x4|0x8)) == 0 ) |
2284 | overlap1, i.types[1],(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2 |0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0 ) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types [0])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types[1])) & (0x1|0x2|0x4|0x8)) == 0 ) |
2285 | t->operand_types[1])(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2 |0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0 ) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types [0])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types[1])) & (0x1|0x2|0x4|0x8)) == 0 ))) |
2286 | { |
2287 | /* Check if other direction is valid ... */ |
2288 | if ((t->opcode_modifier & (D0x2 | FloatD0x400)) == 0) |
2289 | continue; |
2290 | |
2291 | /* Try reversing direction of operands. */ |
2292 | overlap0 = i.types[0] & t->operand_types[1]; |
2293 | overlap1 = i.types[1] & t->operand_types[0]; |
2294 | if (!MATCH (overlap0, i.types[0], t->operand_types[1])((overlap0 & ~0x8000000) && (((i.types[0]) & ( 0x800 | 0x8000000)) == ((overlap0) & (0x800 | 0x8000000)) )) |
2295 | || !MATCH (overlap1, i.types[1], t->operand_types[0])((overlap1 & ~0x8000000) && (((i.types[1]) & ( 0x800 | 0x8000000)) == ((overlap1) & (0x800 | 0x8000000)) )) |
2296 | || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2 |0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0 ) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types [1])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types[0])) & (0x1|0x2|0x4|0x8)) == 0 ) |
2297 | t->operand_types[1],(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2 |0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0 ) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types [1])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types[0])) & (0x1|0x2|0x4|0x8)) == 0 ) |
2298 | overlap1, i.types[1],(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2 |0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0 ) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types [1])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types[0])) & (0x1|0x2|0x4|0x8)) == 0 ) |
2299 | t->operand_types[0])(((i.types[0]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[0]) & (0x1|0x2 |0x4|0x8)) == ((i.types[1]) & (0x1|0x2|0x4|0x8)) || ((((overlap0 ) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types [1])) & (((overlap1) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types[0])) & (0x1|0x2|0x4|0x8)) == 0 )) |
2300 | { |
2301 | /* Does not match either direction. */ |
2302 | continue; |
2303 | } |
2304 | /* found_reverse_match holds which of D or FloatDR |
2305 | we've found. */ |
2306 | found_reverse_match = t->opcode_modifier & (D0x2 | FloatDR0x400); |
2307 | } |
2308 | /* Found a forward 2 operand match here. */ |
2309 | else if (t->operands == 3) |
2310 | { |
2311 | /* Here we make use of the fact that there are no |
2312 | reverse match 3 operand instructions, and all 3 |
2313 | operand instructions only need to be checked for |
2314 | register consistency between operands 2 and 3. */ |
2315 | overlap2 = i.types[2] & t->operand_types[2]; |
2316 | if (!MATCH (overlap2, i.types[2], t->operand_types[2])((overlap2 & ~0x8000000) && (((i.types[2]) & ( 0x800 | 0x8000000)) == ((overlap2) & (0x800 | 0x8000000)) )) |
2317 | || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],(((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[2]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2 |0x4|0x8)) == ((i.types[2]) & (0x1|0x2|0x4|0x8)) || ((((overlap1 ) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types [1])) & (((overlap2) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types[2])) & (0x1|0x2|0x4|0x8)) == 0 ) |
2318 | t->operand_types[1],(((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[2]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2 |0x4|0x8)) == ((i.types[2]) & (0x1|0x2|0x4|0x8)) || ((((overlap1 ) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types [1])) & (((overlap2) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types[2])) & (0x1|0x2|0x4|0x8)) == 0 ) |
2319 | overlap2, i.types[2],(((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[2]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2 |0x4|0x8)) == ((i.types[2]) & (0x1|0x2|0x4|0x8)) || ((((overlap1 ) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types [1])) & (((overlap2) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types[2])) & (0x1|0x2|0x4|0x8)) == 0 ) |
2320 | t->operand_types[2])(((i.types[1]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[2]) & (0x1|0x2|0x4|0x8)) == 0 || ((i.types[1]) & (0x1|0x2 |0x4|0x8)) == ((i.types[2]) & (0x1|0x2|0x4|0x8)) || ((((overlap1 ) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types [1])) & (((overlap2) & 0x4000000) ? (0x1|0x2|0x4|0x8) : (t->operand_types[2])) & (0x1|0x2|0x4|0x8)) == 0 )) |
2321 | |
2322 | continue; |
2323 | } |
2324 | /* Found either forward/reverse 2 or 3 operand match here: |
2325 | slip through to break. */ |
2326 | } |
2327 | if (t->cpu_flags & ~cpu_arch_flags) |
2328 | { |
2329 | found_reverse_match = 0; |
2330 | continue; |
2331 | } |
2332 | /* We've found a match; break out of loop. */ |
2333 | break; |
2334 | } |
2335 | |
2336 | if (t == current_templates->end) |
2337 | { |
2338 | /* We found no match. */ |
2339 | as_bad (_("suffix or operands invalid for `%s'")("suffix or operands invalid for `%s'"), |
2340 | current_templates->start->name); |
2341 | return 0; |
2342 | } |
2343 | |
2344 | if (!quiet_warnings) |
2345 | { |
2346 | if (!intel_syntax |
2347 | && ((i.types[0] & JumpAbsolute0x8000000) |
2348 | != (t->operand_types[0] & JumpAbsolute0x8000000))) |
2349 | { |
2350 | as_warn (_("indirect %s without `*'")("indirect %s without `*'"), t->name); |
2351 | } |
2352 | |
2353 | if ((t->opcode_modifier & (IsPrefix0x8000000 | IgnoreSize0x10000)) |
2354 | == (IsPrefix0x8000000 | IgnoreSize0x10000)) |
2355 | { |
2356 | /* Warn them that a data or address size prefix doesn't |
2357 | affect assembly of the next line of code. */ |
2358 | as_warn (_("stand-alone `%s' prefix")("stand-alone `%s' prefix"), t->name); |
2359 | } |
2360 | } |
2361 | |
2362 | /* Copy the template we found. */ |
2363 | i.tm = *t; |
2364 | if (found_reverse_match) |
2365 | { |
2366 | /* If we found a reverse match we must alter the opcode |
2367 | direction bit. found_reverse_match holds bits to change |
2368 | (different for int & float insns). */ |
2369 | |
2370 | i.tm.base_opcode ^= found_reverse_match; |
2371 | |
2372 | i.tm.operand_types[0] = t->operand_types[1]; |
2373 | i.tm.operand_types[1] = t->operand_types[0]; |
2374 | } |
2375 | |
2376 | return 1; |
2377 | } |
2378 | |
2379 | static int |
2380 | check_string () |
2381 | { |
2382 | int mem_op = (i.types[0] & AnyMem(0x1000|0x2000|0x4000|0x8000|0x800|0x80000000)) ? 0 : 1; |
2383 | if ((i.tm.operand_types[mem_op] & EsSeg0x40000000) != 0) |
2384 | { |
2385 | if (i.seg[0] != NULL((void*)0) && i.seg[0] != &es) |
2386 | { |
2387 | as_bad (_("`%s' operand %d must use `%%es' segment")("`%s' operand %d must use `%%es' segment"), |
2388 | i.tm.name, |
2389 | mem_op + 1); |
2390 | return 0; |
2391 | } |
2392 | /* There's only ever one segment override allowed per instruction. |
2393 | This instruction possibly has a legal segment override on the |
2394 | second operand, so copy the segment to where non-string |
2395 | instructions store it, allowing common code. */ |
2396 | i.seg[0] = i.seg[1]; |
2397 | } |
2398 | else if ((i.tm.operand_types[mem_op + 1] & EsSeg0x40000000) != 0) |
2399 | { |
2400 | if (i.seg[1] != NULL((void*)0) && i.seg[1] != &es) |
2401 | { |
2402 | as_bad (_("`%s' operand %d must use `%%es' segment")("`%s' operand %d must use `%%es' segment"), |
2403 | i.tm.name, |
2404 | mem_op + 2); |
2405 | return 0; |
2406 | } |
2407 | } |
2408 | return 1; |
2409 | } |
2410 | |
2411 | static int |
2412 | process_suffix (void) |
2413 | { |
2414 | /* If matched instruction specifies an explicit instruction mnemonic |
2415 | suffix, use it. */ |
2416 | if (i.tm.opcode_modifier & (Size160x2000 | Size320x4000 | Size640x8000)) |
2417 | { |
2418 | if (i.tm.opcode_modifier & Size160x2000) |
2419 | i.suffix = WORD_MNEM_SUFFIX'w'; |
2420 | else if (i.tm.opcode_modifier & Size640x8000) |
2421 | i.suffix = QWORD_MNEM_SUFFIX'q'; |
2422 | else |
2423 | i.suffix = LONG_MNEM_SUFFIX'l'; |
2424 | } |
2425 | else if (i.reg_operands) |
2426 | { |
2427 | /* If there's no instruction mnemonic suffix we try to invent one |
2428 | based on register operands. */ |
2429 | if (!i.suffix) |
2430 | { |
2431 | /* We take i.suffix from the last register operand specified, |
2432 | Destination register type is more significant than source |
2433 | register type. */ |
2434 | int op; |
2435 | |
2436 | for (op = i.operands; --op >= 0;) |
2437 | if ((i.types[op] & Reg(0x1|0x2|0x4|0x8)) |
2438 | && !(i.tm.operand_types[op] & InOutPortReg0x20000)) |
2439 | { |
2440 | i.suffix = ((i.types[op] & Reg80x1) ? BYTE_MNEM_SUFFIX'b' : |
2441 | (i.types[op] & Reg160x2) ? WORD_MNEM_SUFFIX'w' : |
2442 | (i.types[op] & Reg640x8) ? QWORD_MNEM_SUFFIX'q' : |
2443 | LONG_MNEM_SUFFIX'l'); |
2444 | break; |
2445 | } |
2446 | } |
2447 | else if (i.suffix == BYTE_MNEM_SUFFIX'b') |
2448 | { |
2449 | if (!check_byte_reg ()) |
2450 | return 0; |
2451 | } |
2452 | else if (i.suffix == LONG_MNEM_SUFFIX'l') |
2453 | { |
2454 | if (!check_long_reg ()) |
2455 | return 0; |
2456 | } |
2457 | else if (i.suffix == QWORD_MNEM_SUFFIX'q') |
2458 | { |
2459 | if (!check_qword_reg ()) |
2460 | return 0; |
2461 | } |
2462 | else if (i.suffix == WORD_MNEM_SUFFIX'w') |
2463 | { |
2464 | if (!check_word_reg ()) |
2465 | return 0; |
2466 | } |
2467 | else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize0x10000)) |
2468 | /* Do nothing if the instruction is going to ignore the prefix. */ |
2469 | ; |
2470 | else |
2471 | abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 2471, __PRETTY_FUNCTION__); |
2472 | } |
2473 | else if ((i.tm.opcode_modifier & DefaultSize0x20000) |
2474 | && !i.suffix |
2475 | /* exclude fldenv/frstor/fsave/fstenv */ |
2476 | && (i.tm.opcode_modifier & No_sSuf0x200000)) |
2477 | { |
2478 | i.suffix = stackop_size; |
2479 | } |
2480 | else if (intel_syntax |
2481 | && !i.suffix |
2482 | && ((i.tm.operand_types[0] & JumpAbsolute0x8000000) |
2483 | || (i.tm.opcode_modifier & (JumpByte0x100|JumpInterSegment0x200)) |
2484 | || (i.tm.base_opcode == 0x0f01 /* [ls][gi]dt */ |
2485 | && i.tm.extension_opcode <= 3))) |
2486 | { |
2487 | switch (flag_code) |
2488 | { |
2489 | case CODE_64BIT: |
2490 | if (!(i.tm.opcode_modifier & No_qSuf0x400000)) |
2491 | { |
2492 | i.suffix = QWORD_MNEM_SUFFIX'q'; |
2493 | break; |
2494 | } |
2495 | case CODE_32BIT: |
2496 | if (!(i.tm.opcode_modifier & No_lSuf0x100000)) |
2497 | i.suffix = LONG_MNEM_SUFFIX'l'; |
2498 | break; |
2499 | case CODE_16BIT: |
2500 | if (!(i.tm.opcode_modifier & No_wSuf0x80000)) |
2501 | i.suffix = WORD_MNEM_SUFFIX'w'; |
2502 | break; |
2503 | } |
2504 | } |
2505 | |
2506 | if (!i.suffix) |
2507 | { |
2508 | if (!intel_syntax) |
2509 | { |
2510 | if (i.tm.opcode_modifier & W0x1) |
2511 | { |
2512 | as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction")("no instruction mnemonic suffix given and no register operands; can't size instruction" )); |
2513 | return 0; |
2514 | } |
2515 | } |
2516 | else |
2517 | { |
2518 | unsigned int suffixes = ~i.tm.opcode_modifier |
2519 | & (No_bSuf0x40000 |
2520 | | No_wSuf0x80000 |
2521 | | No_lSuf0x100000 |
2522 | | No_sSuf0x200000 |
2523 | | No_xSuf0x800000 |
2524 | | No_qSuf0x400000); |
2525 | |
2526 | if ((i.tm.opcode_modifier & W0x1) |
2527 | || ((suffixes & (suffixes - 1)) |
2528 | && !(i.tm.opcode_modifier & (DefaultSize0x20000 | IgnoreSize0x10000)))) |
2529 | { |
2530 | as_bad (_("ambiguous operand size for `%s'")("ambiguous operand size for `%s'"), i.tm.name); |
2531 | return 0; |
2532 | } |
2533 | } |
2534 | } |
2535 | |
2536 | /* Change the opcode based on the operand size given by i.suffix; |
2537 | We don't need to change things for byte insns. */ |
2538 | |
2539 | if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX'b') |
2540 | { |
2541 | /* It's not a byte, select word/dword operation. */ |
2542 | if (i.tm.opcode_modifier & W0x1) |
2543 | { |
2544 | if (i.tm.opcode_modifier & ShortForm0x10) |
2545 | i.tm.base_opcode |= 8; |
2546 | else |
2547 | i.tm.base_opcode |= 1; |
2548 | } |
2549 | |
2550 | /* Now select between word & dword operations via the operand |
2551 | size prefix, except for instructions that will ignore this |
2552 | prefix anyway. */ |
2553 | if (i.tm.base_opcode == 0x0f01 && i.tm.extension_opcode == 0xc8) |
2554 | { |
2555 | /* monitor in SSE3 is a very special case. The default size |
2556 | of AX is the size of mode. The address size override |
2557 | prefix will change the size of AX. */ |
2558 | if (i.op->regs[0].reg_type & |
2559 | (flag_code == CODE_32BIT ? Reg160x2 : Reg320x4)) |
2560 | if (!add_prefix (ADDR_PREFIX_OPCODE0x67)) |
2561 | return 0; |
2562 | } |
2563 | else if (i.suffix != QWORD_MNEM_SUFFIX'q' |
2564 | && i.suffix != LONG_DOUBLE_MNEM_SUFFIX'x' |
2565 | && !(i.tm.opcode_modifier & (IgnoreSize0x10000 | FloatMF0x20)) |
2566 | && ((i.suffix == LONG_MNEM_SUFFIX'l') == (flag_code == CODE_16BIT) |
2567 | || (flag_code == CODE_64BIT |
2568 | && (i.tm.opcode_modifier & JumpByte0x100)))) |
2569 | { |
2570 | unsigned int prefix = DATA_PREFIX_OPCODE0x66; |
2571 | |
2572 | if (i.tm.opcode_modifier & JumpByte0x100) /* jcxz, loop */ |
2573 | prefix = ADDR_PREFIX_OPCODE0x67; |
2574 | |
2575 | if (!add_prefix (prefix)) |
2576 | return 0; |
2577 | } |
2578 | |
2579 | /* Set mode64 for an operand. */ |
2580 | if (i.suffix == QWORD_MNEM_SUFFIX'q' |
2581 | && flag_code == CODE_64BIT |
2582 | && (i.tm.opcode_modifier & NoRex640x20000000) == 0) |
2583 | i.rex |= REX_MODE648; |
2584 | |
2585 | /* Size floating point instruction. */ |
2586 | if (i.suffix == LONG_MNEM_SUFFIX'l') |
2587 | if (i.tm.opcode_modifier & FloatMF0x20) |
2588 | i.tm.base_opcode ^= 4; |
2589 | } |
2590 | |
2591 | return 1; |
2592 | } |
2593 | |
2594 | static int |
2595 | check_byte_reg (void) |
2596 | { |
2597 | int op; |
2598 | |
2599 | for (op = i.operands; --op >= 0;) |
2600 | { |
2601 | /* If this is an eight bit register, it's OK. If it's the 16 or |
2602 | 32 bit version of an eight bit register, we will just use the |
2603 | low portion, and that's OK too. */ |
2604 | if (i.types[op] & Reg80x1) |
2605 | continue; |
2606 | |
2607 | /* movzx and movsx should not generate this warning. */ |
2608 | if (intel_syntax |
2609 | && (i.tm.base_opcode == 0xfb7 |
2610 | || i.tm.base_opcode == 0xfb6 |
2611 | || i.tm.base_opcode == 0x63 |
2612 | || i.tm.base_opcode == 0xfbe |
2613 | || i.tm.base_opcode == 0xfbf)) |
2614 | continue; |
2615 | |
2616 | if ((i.types[op] & WordReg(0x2|0x4|0x8)) && i.op[op].regs->reg_num < 4) |
2617 | { |
2618 | /* Prohibit these changes in the 64bit mode, since the |
2619 | lowering is more complicated. */ |
2620 | if (flag_code == CODE_64BIT |
2621 | && (i.tm.operand_types[op] & InOutPortReg0x20000) == 0) |
2622 | { |
2623 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix")("Incorrect register `%%%s' used with `%c' suffix"), |
2624 | i.op[op].regs->reg_name, |
2625 | i.suffix); |
2626 | return 0; |
2627 | } |
2628 | #if REGISTER_WARNINGS1 |
2629 | if (!quiet_warnings |
2630 | && (i.tm.operand_types[op] & InOutPortReg0x20000) == 0) |
2631 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix")("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
2632 | (i.op[op].regs + (i.types[op] & Reg160x2 |
2633 | ? REGNAM_AL1 - REGNAM_AX25 |
2634 | : REGNAM_AL1 - REGNAM_EAX41))->reg_name, |
2635 | i.op[op].regs->reg_name, |
2636 | i.suffix); |
2637 | #endif |
2638 | continue; |
2639 | } |
2640 | /* Any other register is bad. */ |
2641 | if (i.types[op] & (Reg(0x1|0x2|0x4|0x8) | RegMMX0x10000000 | RegXMM0x20000000 |
2642 | | SReg20x1000000 | SReg30x2000000 |
2643 | | Control0x80000 | Debug0x100000 | Test0x200000 |
2644 | | FloatReg0x400000 | FloatAcc0x800000)) |
2645 | { |
2646 | as_bad (_("`%%%s' not allowed with `%s%c'")("`%%%s' not allowed with `%s%c'"), |
2647 | i.op[op].regs->reg_name, |
2648 | i.tm.name, |
2649 | i.suffix); |
2650 | return 0; |
2651 | } |
2652 | } |
2653 | return 1; |
2654 | } |
2655 | |
2656 | static int |
2657 | check_long_reg () |
2658 | { |
2659 | int op; |
2660 | |
2661 | for (op = i.operands; --op >= 0;) |
2662 | /* Reject eight bit registers, except where the template requires |
2663 | them. (eg. movzb) */ |
2664 | if ((i.types[op] & Reg80x1) != 0 |
2665 | && (i.tm.operand_types[op] & (Reg160x2 | Reg320x4 | Acc0x4000000)) != 0) |
2666 | { |
2667 | as_bad (_("`%%%s' not allowed with `%s%c'")("`%%%s' not allowed with `%s%c'"), |
2668 | i.op[op].regs->reg_name, |
2669 | i.tm.name, |
2670 | i.suffix); |
2671 | return 0; |
2672 | } |
2673 | /* Warn if the e prefix on a general reg is missing. */ |
2674 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
2675 | && (i.types[op] & Reg160x2) != 0 |
2676 | && (i.tm.operand_types[op] & (Reg320x4 | Acc0x4000000)) != 0) |
2677 | { |
2678 | /* Prohibit these changes in the 64bit mode, since the |
2679 | lowering is more complicated. */ |
2680 | if (flag_code == CODE_64BIT) |
2681 | { |
2682 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix")("Incorrect register `%%%s' used with `%c' suffix"), |
2683 | i.op[op].regs->reg_name, |
2684 | i.suffix); |
2685 | return 0; |
2686 | } |
2687 | #if REGISTER_WARNINGS1 |
2688 | else |
2689 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix")("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
2690 | (i.op[op].regs + REGNAM_EAX41 - REGNAM_AX25)->reg_name, |
2691 | i.op[op].regs->reg_name, |
2692 | i.suffix); |
2693 | #endif |
2694 | } |
2695 | /* Warn if the r prefix on a general reg is missing. */ |
2696 | else if ((i.types[op] & Reg640x8) != 0 |
2697 | && (i.tm.operand_types[op] & (Reg320x4 | Acc0x4000000)) != 0) |
2698 | { |
2699 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix")("Incorrect register `%%%s' used with `%c' suffix"), |
2700 | i.op[op].regs->reg_name, |
2701 | i.suffix); |
2702 | return 0; |
2703 | } |
2704 | return 1; |
2705 | } |
2706 | |
2707 | static int |
2708 | check_qword_reg () |
2709 | { |
2710 | int op; |
2711 | |
2712 | for (op = i.operands; --op >= 0; ) |
2713 | /* Reject eight bit registers, except where the template requires |
2714 | them. (eg. movzb) */ |
2715 | if ((i.types[op] & Reg80x1) != 0 |
2716 | && (i.tm.operand_types[op] & (Reg160x2 | Reg320x4 | Acc0x4000000)) != 0) |
2717 | { |
2718 | as_bad (_("`%%%s' not allowed with `%s%c'")("`%%%s' not allowed with `%s%c'"), |
2719 | i.op[op].regs->reg_name, |
2720 | i.tm.name, |
2721 | i.suffix); |
2722 | return 0; |
2723 | } |
2724 | /* Warn if the e prefix on a general reg is missing. */ |
2725 | else if (((i.types[op] & Reg160x2) != 0 |
2726 | || (i.types[op] & Reg320x4) != 0) |
2727 | && (i.tm.operand_types[op] & (Reg320x4 | Acc0x4000000)) != 0) |
2728 | { |
2729 | /* Prohibit these changes in the 64bit mode, since the |
2730 | lowering is more complicated. */ |
2731 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix")("Incorrect register `%%%s' used with `%c' suffix"), |
2732 | i.op[op].regs->reg_name, |
2733 | i.suffix); |
2734 | return 0; |
2735 | } |
2736 | return 1; |
2737 | } |
2738 | |
2739 | static int |
2740 | check_word_reg () |
2741 | { |
2742 | int op; |
2743 | for (op = i.operands; --op >= 0;) |
2744 | /* Reject eight bit registers, except where the template requires |
2745 | them. (eg. movzb) */ |
2746 | if ((i.types[op] & Reg80x1) != 0 |
2747 | && (i.tm.operand_types[op] & (Reg160x2 | Reg320x4 | Acc0x4000000)) != 0) |
2748 | { |
2749 | as_bad (_("`%%%s' not allowed with `%s%c'")("`%%%s' not allowed with `%s%c'"), |
2750 | i.op[op].regs->reg_name, |
2751 | i.tm.name, |
2752 | i.suffix); |
2753 | return 0; |
2754 | } |
2755 | /* Warn if the e prefix on a general reg is present. */ |
2756 | else if ((!quiet_warnings || flag_code == CODE_64BIT) |
2757 | && (i.types[op] & Reg320x4) != 0 |
2758 | && (i.tm.operand_types[op] & (Reg160x2 | Acc0x4000000)) != 0) |
2759 | { |
2760 | /* Prohibit these changes in the 64bit mode, since the |
2761 | lowering is more complicated. */ |
2762 | if (flag_code == CODE_64BIT) |
2763 | { |
2764 | as_bad (_("Incorrect register `%%%s' used with `%c' suffix")("Incorrect register `%%%s' used with `%c' suffix"), |
2765 | i.op[op].regs->reg_name, |
2766 | i.suffix); |
2767 | return 0; |
2768 | } |
2769 | else |
2770 | #if REGISTER_WARNINGS1 |
2771 | as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix")("using `%%%s' instead of `%%%s' due to `%c' suffix"), |
2772 | (i.op[op].regs + REGNAM_AX25 - REGNAM_EAX41)->reg_name, |
2773 | i.op[op].regs->reg_name, |
2774 | i.suffix); |
2775 | #endif |
2776 | } |
2777 | return 1; |
2778 | } |
2779 | |
2780 | static int |
2781 | finalize_imm () |
2782 | { |
2783 | unsigned int overlap0, overlap1, overlap2; |
2784 | |
2785 | overlap0 = i.types[0] & i.tm.operand_types[0]; |
2786 | if ((overlap0 & (Imm80x10 | Imm8S0x20 | Imm160x40 | Imm320x80 | Imm32S0x100 | Imm640x200)) |
2787 | && overlap0 != Imm80x10 && overlap0 != Imm8S0x20 |
2788 | && overlap0 != Imm160x40 && overlap0 != Imm32S0x100 |
2789 | && overlap0 != Imm320x80 && overlap0 != Imm640x200) |
2790 | { |
2791 | if (i.suffix) |
2792 | { |
2793 | overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX'b' |
2794 | ? Imm80x10 | Imm8S0x20 |
2795 | : (i.suffix == WORD_MNEM_SUFFIX'w' |
2796 | ? Imm160x40 |
2797 | : (i.suffix == QWORD_MNEM_SUFFIX'q' |
2798 | ? Imm640x200 | Imm32S0x100 |
2799 | : Imm320x80))); |
2800 | } |
2801 | else if (overlap0 == (Imm160x40 | Imm32S0x100 | Imm320x80) |
2802 | || overlap0 == (Imm160x40 | Imm320x80) |
2803 | || overlap0 == (Imm160x40 | Imm32S0x100)) |
2804 | { |
2805 | overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX3] != 0) |
2806 | ? Imm160x40 : Imm32S0x100); |
2807 | } |
2808 | if (overlap0 != Imm80x10 && overlap0 != Imm8S0x20 |
2809 | && overlap0 != Imm160x40 && overlap0 != Imm32S0x100 |
2810 | && overlap0 != Imm320x80 && overlap0 != Imm640x200) |
2811 | { |
2812 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size")("no instruction mnemonic suffix given; can't determine immediate size" )); |
2813 | return 0; |
2814 | } |
2815 | } |
2816 | i.types[0] = overlap0; |
2817 | |
2818 | overlap1 = i.types[1] & i.tm.operand_types[1]; |
2819 | if ((overlap1 & (Imm80x10 | Imm8S0x20 | Imm160x40 | Imm32S0x100 | Imm320x80 | Imm640x200)) |
2820 | && overlap1 != Imm80x10 && overlap1 != Imm8S0x20 |
2821 | && overlap1 != Imm160x40 && overlap1 != Imm32S0x100 |
2822 | && overlap1 != Imm320x80 && overlap1 != Imm640x200) |
2823 | { |
2824 | if (i.suffix) |
2825 | { |
2826 | overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX'b' |
2827 | ? Imm80x10 | Imm8S0x20 |
2828 | : (i.suffix == WORD_MNEM_SUFFIX'w' |
2829 | ? Imm160x40 |
2830 | : (i.suffix == QWORD_MNEM_SUFFIX'q' |
2831 | ? Imm640x200 | Imm32S0x100 |
2832 | : Imm320x80))); |
2833 | } |
2834 | else if (overlap1 == (Imm160x40 | Imm320x80 | Imm32S0x100) |
2835 | || overlap1 == (Imm160x40 | Imm320x80) |
2836 | || overlap1 == (Imm160x40 | Imm32S0x100)) |
2837 | { |
2838 | overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX3] != 0) |
2839 | ? Imm160x40 : Imm32S0x100); |
2840 | } |
2841 | if (overlap1 != Imm80x10 && overlap1 != Imm8S0x20 |
2842 | && overlap1 != Imm160x40 && overlap1 != Imm32S0x100 |
2843 | && overlap1 != Imm320x80 && overlap1 != Imm640x200) |
2844 | { |
2845 | as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c")("no instruction mnemonic suffix given; can't determine immediate size %x %c" ),overlap1, i.suffix); |
2846 | return 0; |
2847 | } |
2848 | } |
2849 | i.types[1] = overlap1; |
2850 | |
2851 | overlap2 = i.types[2] & i.tm.operand_types[2]; |
2852 | assert ((overlap2 & Imm) == 0)((void) (((overlap2 & (0x10|0x20|0x40|0x100|0x80|0x200)) == 0) ? 0 : (as_assert ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 2852, __PRETTY_FUNCTION__), 0))); |
2853 | i.types[2] = overlap2; |
2854 | |
2855 | return 1; |
2856 | } |
2857 | |
2858 | static int |
2859 | process_operands () |
2860 | { |
2861 | /* Default segment register this instruction will use for memory |
2862 | accesses. 0 means unknown. This is only for optimizing out |
2863 | unnecessary segment overrides. */ |
2864 | const seg_entry *default_seg = 0; |
2865 | |
2866 | /* The imul $imm, %reg instruction is converted into |
2867 | imul $imm, %reg, %reg, and the clr %reg instruction |
2868 | is converted into xor %reg, %reg. */ |
2869 | if (i.tm.opcode_modifier & regKludge0x4000000) |
2870 | { |
2871 | unsigned int first_reg_op = (i.types[0] & Reg(0x1|0x2|0x4|0x8)) ? 0 : 1; |
2872 | /* Pretend we saw the extra register operand. */ |
2873 | assert (i.op[first_reg_op + 1].regs == 0)((void) ((i.op[first_reg_op + 1].regs == 0) ? 0 : (as_assert ( "/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c", 2873 , __PRETTY_FUNCTION__), 0))); |
2874 | i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs; |
2875 | i.types[first_reg_op + 1] = i.types[first_reg_op]; |
2876 | i.reg_operands = 2; |
2877 | } |
2878 | |
2879 | if (i.tm.opcode_modifier & ShortForm0x10) |
2880 | { |
2881 | /* The register or float register operand is in operand 0 or 1. */ |
2882 | unsigned int op = (i.types[0] & (Reg(0x1|0x2|0x4|0x8) | FloatReg0x400000)) ? 0 : 1; |
2883 | /* Register goes in low 3 bits of opcode. */ |
2884 | i.tm.base_opcode |= i.op[op].regs->reg_num; |
2885 | if ((i.op[op].regs->reg_flags & RegRex0x1) != 0) |
2886 | i.rex |= REX_EXTZ1; |
2887 | if (!quiet_warnings && (i.tm.opcode_modifier & Ugh0x80000000) != 0) |
2888 | { |
2889 | /* Warn about some common errors, but press on regardless. |
2890 | The first case can be generated by gcc (<= 2.8.1). */ |
2891 | if (i.operands == 2) |
2892 | { |
2893 | /* Reversed arguments on faddp, fsubp, etc. */ |
2894 | as_warn (_("translating to `%s %%%s,%%%s'")("translating to `%s %%%s,%%%s'"), i.tm.name, |
2895 | i.op[1].regs->reg_name, |
2896 | i.op[0].regs->reg_name); |
2897 | } |
2898 | else |
2899 | { |
2900 | /* Extraneous `l' suffix on fp insn. */ |
2901 | as_warn (_("translating to `%s %%%s'")("translating to `%s %%%s'"), i.tm.name, |
2902 | i.op[0].regs->reg_name); |
2903 | } |
2904 | } |
2905 | } |
2906 | else if (i.tm.opcode_modifier & Modrm0x4) |
2907 | { |
2908 | /* The opcode is completed (modulo i.tm.extension_opcode which |
2909 | must be put into the modrm byte). Now, we make the modrm and |
2910 | index base bytes based on all the info we've collected. */ |
2911 | |
2912 | default_seg = build_modrm_byte (); |
2913 | } |
2914 | else if (i.tm.opcode_modifier & (Seg2ShortForm0x800 | Seg3ShortForm0x1000)) |
2915 | { |
2916 | if (i.tm.base_opcode == POP_SEG_SHORT0x07 |
2917 | && i.op[0].regs->reg_num == 1) |
2918 | { |
2919 | as_bad (_("you can't `pop %%cs'")("you can't `pop %%cs'")); |
2920 | return 0; |
2921 | } |
2922 | i.tm.base_opcode |= (i.op[0].regs->reg_num << 3); |
2923 | if ((i.op[0].regs->reg_flags & RegRex0x1) != 0) |
2924 | i.rex |= REX_EXTZ1; |
2925 | } |
2926 | else if ((i.tm.base_opcode & ~(D0x2 | W0x1)) == MOV_AX_DISP320xa0) |
2927 | { |
2928 | default_seg = &ds; |
2929 | } |
2930 | else if ((i.tm.opcode_modifier & IsString0x2000000) != 0) |
2931 | { |
2932 | /* For the string instructions that allow a segment override |
2933 | on one of their operands, the default segment is ds. */ |
2934 | default_seg = &ds; |
2935 | } |
2936 | |
2937 | if ((i.tm.base_opcode == 0x8d /* lea */ |
2938 | || (i.tm.cpu_flags & CpuSVME0x80000)) |
2939 | && i.seg[0] && !quiet_warnings) |
2940 | as_warn (_("segment override on `%s' is ineffectual")("segment override on `%s' is ineffectual"), i.tm.name); |
2941 | |
2942 | /* If a segment was explicitly specified, and the specified segment |
2943 | is not the default, use an opcode prefix to select it. If we |
2944 | never figured out what the default segment is, then default_seg |
2945 | will be zero at this point, and the specified segment prefix will |
2946 | always be used. */ |
2947 | if ((i.seg[0]) && (i.seg[0] != default_seg)) |
2948 | { |
2949 | if (!add_prefix (i.seg[0]->seg_prefix)) |
2950 | return 0; |
2951 | } |
2952 | return 1; |
2953 | } |
2954 | |
2955 | static const seg_entry * |
2956 | build_modrm_byte () |
2957 | { |
2958 | const seg_entry *default_seg = 0; |
2959 | |
2960 | /* i.reg_operands MUST be the number of real register operands; |
2961 | implicit registers do not count. */ |
2962 | if (i.reg_operands == 2) |
2963 | { |
2964 | unsigned int source, dest; |
2965 | source = ((i.types[0] |
2966 | & (Reg(0x1|0x2|0x4|0x8) | RegMMX0x10000000 | RegXMM0x20000000 |
2967 | | SReg20x1000000 | SReg30x2000000 |
2968 | | Control0x80000 | Debug0x100000 | Test0x200000)) |
2969 | ? 0 : 1); |
2970 | dest = source + 1; |
2971 | |
2972 | i.rm.mode = 3; |
2973 | /* One of the register operands will be encoded in the i.tm.reg |
2974 | field, the other in the combined i.tm.mode and i.tm.regmem |
2975 | fields. If no form of this instruction supports a memory |
2976 | destination operand, then we assume the source operand may |
2977 | sometimes be a memory operand and so we need to store the |
2978 | destination in the i.rm.reg field. */ |
2979 | if ((i.tm.operand_types[dest] & AnyMem(0x1000|0x2000|0x4000|0x8000|0x800|0x80000000)) == 0) |
2980 | { |
2981 | i.rm.reg = i.op[dest].regs->reg_num; |
2982 | i.rm.regmem = i.op[source].regs->reg_num; |
2983 | if ((i.op[dest].regs->reg_flags & RegRex0x1) != 0) |
2984 | i.rex |= REX_EXTX4; |
2985 | if ((i.op[source].regs->reg_flags & RegRex0x1) != 0) |
2986 | i.rex |= REX_EXTZ1; |
2987 | } |
2988 | else |
2989 | { |
2990 | i.rm.reg = i.op[source].regs->reg_num; |
2991 | i.rm.regmem = i.op[dest].regs->reg_num; |
2992 | if ((i.op[dest].regs->reg_flags & RegRex0x1) != 0) |
2993 | i.rex |= REX_EXTZ1; |
2994 | if ((i.op[source].regs->reg_flags & RegRex0x1) != 0) |
2995 | i.rex |= REX_EXTX4; |
2996 | } |
2997 | if (flag_code != CODE_64BIT && (i.rex & (REX_EXTX4 | REX_EXTZ1))) |
2998 | { |
2999 | if (!((i.types[0] | i.types[1]) & Control0x80000)) |
3000 | abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 3000, __PRETTY_FUNCTION__); |
3001 | i.rex &= ~(REX_EXTX4 | REX_EXTZ1); |
3002 | add_prefix (LOCK_PREFIX_OPCODE0xf0); |
3003 | } |
3004 | } |
3005 | else |
3006 | { /* If it's not 2 reg operands... */ |
3007 | if (i.mem_operands) |
3008 | { |
3009 | unsigned int fake_zero_displacement = 0; |
3010 | unsigned int op = ((i.types[0] & AnyMem(0x1000|0x2000|0x4000|0x8000|0x800|0x80000000)) |
3011 | ? 0 |
3012 | : (i.types[1] & AnyMem(0x1000|0x2000|0x4000|0x8000|0x800|0x80000000)) ? 1 : 2); |
3013 | |
3014 | default_seg = &ds; |
3015 | |
3016 | if (i.base_reg == 0) |
3017 | { |
3018 | i.rm.mode = 0; |
3019 | if (!i.disp_operands) |
3020 | fake_zero_displacement = 1; |
3021 | if (i.index_reg == 0) |
3022 | { |
3023 | /* Operand is just <disp> */ |
3024 | if (flag_code == CODE_64BIT) |
3025 | { |
3026 | /* 64bit mode overwrites the 32bit absolute |
3027 | addressing by RIP relative addressing and |
3028 | absolute addressing is encoded by one of the |
3029 | redundant SIB forms. */ |
3030 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING4; |
3031 | i.sib.base = NO_BASE_REGISTER5; |
3032 | i.sib.index = NO_INDEX_REGISTER4; |
3033 | i.types[op] = ((i.prefix[ADDR_PREFIX2] == 0) ? Disp32S0x8000 : Disp320x4000); |
3034 | } |
3035 | else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX2] != 0)) |
3036 | { |
3037 | i.rm.regmem = NO_BASE_REGISTER_166; |
3038 | i.types[op] = Disp160x2000; |
3039 | } |
3040 | else |
3041 | { |
3042 | i.rm.regmem = NO_BASE_REGISTER5; |
3043 | i.types[op] = Disp320x4000; |
3044 | } |
3045 | } |
3046 | else /* !i.base_reg && i.index_reg */ |
3047 | { |
3048 | i.sib.index = i.index_reg->reg_num; |
3049 | i.sib.base = NO_BASE_REGISTER5; |
3050 | i.sib.scale = i.log2_scale_factor; |
3051 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING4; |
3052 | i.types[op] &= ~Disp(0x1000|0x2000|0x4000|0x8000|0x10000); |
3053 | if (flag_code != CODE_64BIT) |
3054 | i.types[op] |= Disp320x4000; /* Must be 32 bit */ |
3055 | else |
3056 | i.types[op] |= Disp32S0x8000; |
3057 | if ((i.index_reg->reg_flags & RegRex0x1) != 0) |
3058 | i.rex |= REX_EXTY2; |
3059 | } |
3060 | } |
3061 | /* RIP addressing for 64bit mode. */ |
3062 | else if (i.base_reg->reg_type == BaseIndex0x800) |
3063 | { |
3064 | i.rm.regmem = NO_BASE_REGISTER5; |
3065 | i.types[op] &= ~ Disp(0x1000|0x2000|0x4000|0x8000|0x10000); |
3066 | i.types[op] |= Disp32S0x8000; |
3067 | i.flags[op] = Operand_PCrel1; |
3068 | if (! i.disp_operands) |
3069 | fake_zero_displacement = 1; |
3070 | } |
3071 | else if (i.base_reg->reg_type & Reg160x2) |
3072 | { |
3073 | switch (i.base_reg->reg_num) |
3074 | { |
3075 | case 3: /* (%bx) */ |
3076 | if (i.index_reg == 0) |
3077 | i.rm.regmem = 7; |
3078 | else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */ |
3079 | i.rm.regmem = i.index_reg->reg_num - 6; |
3080 | break; |
3081 | case 5: /* (%bp) */ |
3082 | default_seg = &ss; |
3083 | if (i.index_reg == 0) |
3084 | { |
3085 | i.rm.regmem = 6; |
3086 | if ((i.types[op] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000)) == 0) |
3087 | { |
3088 | /* fake (%bp) into 0(%bp) */ |
3089 | i.types[op] |= Disp80x1000; |
3090 | fake_zero_displacement = 1; |
3091 | } |
3092 | } |
3093 | else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */ |
3094 | i.rm.regmem = i.index_reg->reg_num - 6 + 2; |
3095 | break; |
3096 | default: /* (%si) -> 4 or (%di) -> 5 */ |
3097 | i.rm.regmem = i.base_reg->reg_num - 6 + 4; |
3098 | } |
3099 | i.rm.mode = mode_from_disp_size (i.types[op]); |
3100 | } |
3101 | else /* i.base_reg and 32/64 bit mode */ |
3102 | { |
3103 | if (flag_code == CODE_64BIT |
3104 | && (i.types[op] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000))) |
3105 | i.types[op] = (i.types[op] & Disp80x1000) | (i.prefix[ADDR_PREFIX2] == 0 ? Disp32S0x8000 : Disp320x4000); |
3106 | |
3107 | i.rm.regmem = i.base_reg->reg_num; |
3108 | if ((i.base_reg->reg_flags & RegRex0x1) != 0) |
3109 | i.rex |= REX_EXTZ1; |
3110 | i.sib.base = i.base_reg->reg_num; |
3111 | /* x86-64 ignores REX prefix bit here to avoid decoder |
3112 | complications. */ |
3113 | if ((i.base_reg->reg_num & 7) == EBP_REG_NUM5) |
3114 | { |
3115 | default_seg = &ss; |
3116 | if (i.disp_operands == 0) |
3117 | { |
3118 | fake_zero_displacement = 1; |
3119 | i.types[op] |= Disp80x1000; |
3120 | } |
3121 | } |
3122 | else if (i.base_reg->reg_num == ESP_REG_NUM4) |
3123 | { |
3124 | default_seg = &ss; |
3125 | } |
3126 | i.sib.scale = i.log2_scale_factor; |
3127 | if (i.index_reg == 0) |
3128 | { |
3129 | /* <disp>(%esp) becomes two byte modrm with no index |
3130 | register. We've already stored the code for esp |
3131 | in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. |
3132 | Any base register besides %esp will not use the |
3133 | extra modrm byte. */ |
3134 | i.sib.index = NO_INDEX_REGISTER4; |
3135 | #if !SCALE1_WHEN_NO_INDEX1 |
3136 | /* Another case where we force the second modrm byte. */ |
3137 | if (i.log2_scale_factor) |
3138 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING4; |
3139 | #endif |
3140 | } |
3141 | else |
3142 | { |
3143 | i.sib.index = i.index_reg->reg_num; |
3144 | i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING4; |
3145 | if ((i.index_reg->reg_flags & RegRex0x1) != 0) |
3146 | i.rex |= REX_EXTY2; |
3147 | } |
3148 | |
3149 | if (i.disp_operands |
3150 | && (i.reloc[op] == BFD_RELOC_386_TLS_DESC_CALL |
3151 | || i.reloc[op] == BFD_RELOC_X86_64_TLSDESC_CALL)) |
3152 | i.rm.mode = 0; |
3153 | else |
3154 | i.rm.mode = mode_from_disp_size (i.types[op]); |
3155 | } |
3156 | |
3157 | if (fake_zero_displacement) |
3158 | { |
3159 | /* Fakes a zero displacement assuming that i.types[op] |
3160 | holds the correct displacement size. */ |
3161 | expressionS *exp; |
3162 | |
3163 | assert (i.op[op].disps == 0)((void) ((i.op[op].disps == 0) ? 0 : (as_assert ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 3163, __PRETTY_FUNCTION__), 0))); |
3164 | exp = &disp_expressions[i.disp_operands++]; |
3165 | i.op[op].disps = exp; |
3166 | exp->X_op = O_constant; |
3167 | exp->X_add_number = 0; |
3168 | exp->X_add_symbol = (symbolS *) 0; |
3169 | exp->X_op_symbol = (symbolS *) 0; |
3170 | } |
3171 | } |
3172 | |
3173 | /* Fill in i.rm.reg or i.rm.regmem field with register operand |
3174 | (if any) based on i.tm.extension_opcode. Again, we must be |
3175 | careful to make sure that segment/control/debug/test/MMX |
3176 | registers are coded into the i.rm.reg field. */ |
3177 | if (i.reg_operands) |
3178 | { |
3179 | unsigned int op = |
3180 | ((i.types[0] |
3181 | & (Reg(0x1|0x2|0x4|0x8) | RegMMX0x10000000 | RegXMM0x20000000 |
3182 | | SReg20x1000000 | SReg30x2000000 |
3183 | | Control0x80000 | Debug0x100000 | Test0x200000)) |
3184 | ? 0 |
3185 | : ((i.types[1] |
3186 | & (Reg(0x1|0x2|0x4|0x8) | RegMMX0x10000000 | RegXMM0x20000000 |
3187 | | SReg20x1000000 | SReg30x2000000 |
3188 | | Control0x80000 | Debug0x100000 | Test0x200000)) |
3189 | ? 1 |
3190 | : 2)); |
3191 | /* If there is an extension opcode to put here, the register |
3192 | number must be put into the regmem field. */ |
3193 | if (i.tm.extension_opcode != None0xffff) |
3194 | { |
3195 | i.rm.regmem = i.op[op].regs->reg_num; |
3196 | if ((i.op[op].regs->reg_flags & RegRex0x1) != 0) |
3197 | i.rex |= REX_EXTZ1; |
3198 | } |
3199 | else |
3200 | { |
3201 | i.rm.reg = i.op[op].regs->reg_num; |
3202 | if ((i.op[op].regs->reg_flags & RegRex0x1) != 0) |
3203 | i.rex |= REX_EXTX4; |
3204 | } |
3205 | |
3206 | /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we |
3207 | must set it to 3 to indicate this is a register operand |
3208 | in the regmem field. */ |
3209 | if (!i.mem_operands) |
3210 | i.rm.mode = 3; |
3211 | } |
3212 | |
3213 | /* Fill in i.rm.reg field with extension opcode (if any). */ |
3214 | if (i.tm.extension_opcode != None0xffff) |
3215 | i.rm.reg = i.tm.extension_opcode; |
3216 | } |
3217 | return default_seg; |
3218 | } |
3219 | |
3220 | static void |
3221 | output_branch () |
3222 | { |
3223 | char *p; |
3224 | int code16; |
3225 | int prefix; |
3226 | relax_substateT subtype; |
3227 | symbolS *sym; |
3228 | offsetT off; |
3229 | |
3230 | code16 = 0; |
3231 | if (flag_code == CODE_16BIT) |
3232 | code16 = CODE161; |
3233 | |
3234 | prefix = 0; |
3235 | if (i.prefix[DATA_PREFIX3] != 0) |
3236 | { |
3237 | prefix = 1; |
3238 | i.prefixes -= 1; |
3239 | code16 ^= CODE161; |
3240 | } |
3241 | /* Pentium4 branch hints. */ |
3242 | if (i.prefix[SEG_PREFIX4] == CS_PREFIX_OPCODE0x2e /* not taken */ |
3243 | || i.prefix[SEG_PREFIX4] == DS_PREFIX_OPCODE0x3e /* taken */) |
3244 | { |
3245 | prefix++; |
3246 | i.prefixes--; |
3247 | } |
3248 | if (i.prefix[REX_PREFIX5] != 0) |
3249 | { |
3250 | prefix++; |
3251 | i.prefixes--; |
3252 | } |
3253 | |
3254 | if (i.prefixes != 0 && !intel_syntax) |
3255 | as_warn (_("skipping prefixes on this instruction")("skipping prefixes on this instruction")); |
3256 | |
3257 | /* It's always a symbol; End frag & setup for relax. |
3258 | Make sure there is enough room in this frag for the largest |
3259 | instruction we may generate in md_convert_frag. This is 2 |
3260 | bytes for the opcode and room for the prefix and largest |
3261 | displacement. */ |
3262 | frag_grow (prefix + 2 + 4); |
3263 | /* Prefix and 1 opcode byte go in fr_fix. */ |
3264 | p = frag_more (prefix + 1); |
3265 | if (i.prefix[DATA_PREFIX3] != 0) |
3266 | *p++ = DATA_PREFIX_OPCODE0x66; |
3267 | if (i.prefix[SEG_PREFIX4] == CS_PREFIX_OPCODE0x2e |
3268 | || i.prefix[SEG_PREFIX4] == DS_PREFIX_OPCODE0x3e) |
3269 | *p++ = i.prefix[SEG_PREFIX4]; |
3270 | if (i.prefix[REX_PREFIX5] != 0) |
3271 | *p++ = i.prefix[REX_PREFIX5]; |
3272 | *p = i.tm.base_opcode; |
3273 | |
3274 | if ((unsigned char) *p == JUMP_PC_RELATIVE0xeb) |
3275 | subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL)((relax_substateT) (((0) << 2) | (0))); |
3276 | else if ((cpu_arch_flags & Cpu3860x8) != 0) |
3277 | subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL)((relax_substateT) (((1) << 2) | (0))); |
3278 | else |
3279 | subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL)((relax_substateT) (((2) << 2) | (0))); |
3280 | subtype |= code16; |
3281 | |
3282 | sym = i.op[0].disps->X_add_symbol; |
3283 | off = i.op[0].disps->X_add_number; |
3284 | |
3285 | if (i.op[0].disps->X_op != O_constant |
3286 | && i.op[0].disps->X_op != O_symbol) |
3287 | { |
3288 | /* Handle complex expressions. */ |
3289 | sym = make_expr_symbol (i.op[0].disps); |
3290 | off = 0; |
3291 | } |
3292 | |
3293 | /* 1 possible extra opcode + 4 byte displacement go in var part. |
3294 | Pass reloc in fr_var. */ |
3295 | frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p); |
3296 | } |
3297 | |
3298 | static void |
3299 | output_jump () |
3300 | { |
3301 | char *p; |
3302 | int size; |
3303 | fixS *fixP; |
3304 | |
3305 | if (i.tm.opcode_modifier & JumpByte0x100) |
3306 | { |
3307 | /* This is a loop or jecxz type instruction. */ |
3308 | size = 1; |
3309 | if (i.prefix[ADDR_PREFIX2] != 0) |
3310 | { |
3311 | FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE)frag_append_1_char (0x67); |
3312 | i.prefixes -= 1; |
3313 | } |
3314 | /* Pentium4 branch hints. */ |
3315 | if (i.prefix[SEG_PREFIX4] == CS_PREFIX_OPCODE0x2e /* not taken */ |
3316 | || i.prefix[SEG_PREFIX4] == DS_PREFIX_OPCODE0x3e /* taken */) |
3317 | { |
3318 | FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX])frag_append_1_char (i.prefix[4]); |
3319 | i.prefixes--; |
3320 | } |
3321 | } |
3322 | else |
3323 | { |
3324 | int code16; |
3325 | |
3326 | code16 = 0; |
3327 | if (flag_code == CODE_16BIT) |
3328 | code16 = CODE161; |
3329 | |
3330 | if (i.prefix[DATA_PREFIX3] != 0) |
3331 | { |
3332 | FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE)frag_append_1_char (0x66); |
3333 | i.prefixes -= 1; |
3334 | code16 ^= CODE161; |
3335 | } |
3336 | |
3337 | size = 4; |
3338 | if (code16) |
3339 | size = 2; |
3340 | } |
3341 | |
3342 | if (i.prefix[REX_PREFIX5] != 0) |
3343 | { |
3344 | FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX])frag_append_1_char (i.prefix[5]); |
3345 | i.prefixes -= 1; |
3346 | } |
3347 | |
3348 | if (i.prefixes != 0 && !intel_syntax) |
3349 | as_warn (_("skipping prefixes on this instruction")("skipping prefixes on this instruction")); |
3350 | |
3351 | p = frag_more (1 + size); |
3352 | *p++ = i.tm.base_opcode; |
3353 | |
3354 | fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
3355 | i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0])); |
3356 | |
3357 | /* All jumps handled here are signed, but don't use a signed limit |
3358 | check for 32 and 16 bit jumps as we want to allow wrap around at |
3359 | 4G and 64k respectively. */ |
3360 | if (size == 1) |
3361 | fixP->fx_signed = 1; |
3362 | } |
3363 | |
3364 | static void |
3365 | output_interseg_jump () |
3366 | { |
3367 | char *p; |
3368 | int size; |
3369 | int prefix; |
3370 | int code16; |
3371 | |
3372 | code16 = 0; |
3373 | if (flag_code == CODE_16BIT) |
3374 | code16 = CODE161; |
3375 | |
3376 | prefix = 0; |
3377 | if (i.prefix[DATA_PREFIX3] != 0) |
3378 | { |
3379 | prefix = 1; |
3380 | i.prefixes -= 1; |
3381 | code16 ^= CODE161; |
3382 | } |
3383 | if (i.prefix[REX_PREFIX5] != 0) |
3384 | { |
3385 | prefix++; |
3386 | i.prefixes -= 1; |
3387 | } |
3388 | |
3389 | size = 4; |
3390 | if (code16) |
3391 | size = 2; |
3392 | |
3393 | if (i.prefixes != 0 && !intel_syntax) |
3394 | as_warn (_("skipping prefixes on this instruction")("skipping prefixes on this instruction")); |
3395 | |
3396 | /* 1 opcode; 2 segment; offset */ |
3397 | p = frag_more (prefix + 1 + 2 + size); |
3398 | |
3399 | if (i.prefix[DATA_PREFIX3] != 0) |
3400 | *p++ = DATA_PREFIX_OPCODE0x66; |
3401 | |
3402 | if (i.prefix[REX_PREFIX5] != 0) |
3403 | *p++ = i.prefix[REX_PREFIX5]; |
3404 | |
3405 | *p++ = i.tm.base_opcode; |
3406 | if (i.op[1].imms->X_op == O_constant) |
3407 | { |
3408 | offsetT n = i.op[1].imms->X_add_number; |
3409 | |
3410 | if (size == 2 |
3411 | && !fits_in_unsigned_word (n) |
3412 | && !fits_in_signed_word (n)) |
3413 | { |
3414 | as_bad (_("16-bit jump out of range")("16-bit jump out of range")); |
3415 | return; |
3416 | } |
3417 | md_number_to_charsnumber_to_chars_littleendian (p, n, size); |
3418 | } |
3419 | else |
3420 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
3421 | i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1])); |
3422 | if (i.op[0].imms->X_op != O_constant) |
3423 | as_bad (_("can't handle non absolute segment in `%s'")("can't handle non absolute segment in `%s'"), |
3424 | i.tm.name); |
3425 | md_number_to_charsnumber_to_chars_littleendian (p + size, (valueT) i.op[0].imms->X_add_number, 2); |
3426 | } |
3427 | |
3428 | static void |
3429 | output_insn () |
3430 | { |
3431 | fragS *insn_start_frag; |
3432 | offsetT insn_start_off; |
3433 | |
3434 | /* Tie dwarf2 debug info to the address at the start of the insn. |
3435 | We can't do this after the insn has been output as the current |
3436 | frag may have been closed off. eg. by frag_var. */ |
3437 | dwarf2_emit_insn (0); |
3438 | |
3439 | insn_start_frag = frag_now; |
3440 | insn_start_off = frag_now_fix (); |
3441 | |
3442 | /* Output jumps. */ |
3443 | if (i.tm.opcode_modifier & Jump0x40) |
3444 | output_branch (); |
3445 | else if (i.tm.opcode_modifier & (JumpByte0x100 | JumpDword0x80)) |
3446 | output_jump (); |
3447 | else if (i.tm.opcode_modifier & JumpInterSegment0x200) |
3448 | output_interseg_jump (); |
3449 | else |
3450 | { |
3451 | /* Output normal instructions here. */ |
3452 | char *p; |
3453 | unsigned char *q; |
3454 | unsigned int prefix; |
3455 | |
3456 | /* All opcodes on i386 have either 1 or 2 bytes. Merom New |
3457 | Instructions have 3 bytes. We may use one more higher byte |
3458 | to specify a prefix the instruction requires. */ |
3459 | if ((i.tm.cpu_flags & (CpuMNI0x200000|CpuAES0x800000|CpuPCLMUL0x1000000)) != 0) |
3460 | { |
3461 | if (i.tm.base_opcode & 0xff000000) |
3462 | { |
3463 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
3464 | goto check_prefix; |
3465 | } |
3466 | } |
3467 | else if ((i.tm.base_opcode & ~3) == 0x660f3880) { |
3468 | /* INVEPT, INVVPID, and INVPCID are 3 byte instructions with a |
3469 | mandatory prefix. */ |
3470 | prefix = (i.tm.base_opcode >> 24) & 0xff; |
3471 | add_prefix (prefix); |
3472 | } |
3473 | else if ((i.tm.base_opcode & 0xff0000) != 0) |
3474 | { |
3475 | prefix = (i.tm.base_opcode >> 16) & 0xff; |
3476 | if ((i.tm.cpu_flags & CpuPadLock0x40000) != 0) |
3477 | { |
3478 | check_prefix: |
3479 | if (prefix != REPE_PREFIX_OPCODE0xf3 |
3480 | || i.prefix[LOCKREP_PREFIX1] != REPE_PREFIX_OPCODE0xf3) |
3481 | add_prefix (prefix); |
3482 | } |
3483 | else |
3484 | add_prefix (prefix); |
3485 | } |
3486 | |
3487 | /* The prefix bytes. */ |
3488 | for (q = i.prefix; |
3489 | q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]); |
3490 | q++) |
3491 | { |
3492 | if (*q) |
3493 | { |
3494 | p = frag_more (1); |
3495 | md_number_to_charsnumber_to_chars_littleendian (p, (valueT) *q, 1); |
3496 | } |
3497 | } |
3498 | |
3499 | /* Now the opcode; be careful about word order here! */ |
3500 | if (fits_in_unsigned_byte (i.tm.base_opcode)) |
3501 | { |
3502 | FRAG_APPEND_1_CHAR (i.tm.base_opcode)frag_append_1_char (i.tm.base_opcode); |
3503 | } |
3504 | else |
3505 | { |
3506 | if ((i.tm.cpu_flags & (CpuMNI0x200000|CpuAES0x800000|CpuPCLMUL0x1000000)) != 0) |
3507 | { |
3508 | p = frag_more (3); |
3509 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
3510 | } |
3511 | else if ((i.tm.base_opcode & ~3) == 0x660f3880) |
3512 | { |
3513 | p = frag_more (3); |
3514 | *p++ = (i.tm.base_opcode >> 16) & 0xff; |
3515 | } |
3516 | else |
3517 | p = frag_more (2); |
3518 | |
3519 | /* Put out high byte first: can't use md_number_to_chars! */ |
3520 | *p++ = (i.tm.base_opcode >> 8) & 0xff; |
3521 | *p = i.tm.base_opcode & 0xff; |
3522 | } |
3523 | |
3524 | /* Now the modrm byte and sib byte (if present). */ |
3525 | if (i.tm.opcode_modifier & Modrm0x4) |
3526 | { |
3527 | p = frag_more (1); |
3528 | md_number_to_charsnumber_to_chars_littleendian (p, |
3529 | (valueT) (i.rm.regmem << 0 |
3530 | | i.rm.reg << 3 |
3531 | | i.rm.mode << 6), |
3532 | 1); |
3533 | /* If i.rm.regmem == ESP (4) |
3534 | && i.rm.mode != (Register mode) |
3535 | && not 16 bit |
3536 | ==> need second modrm byte. */ |
3537 | if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING4 |
3538 | && i.rm.mode != 3 |
3539 | && !(i.base_reg && (i.base_reg->reg_type & Reg160x2) != 0)) |
3540 | { |
3541 | p = frag_more (1); |
3542 | md_number_to_charsnumber_to_chars_littleendian (p, |
3543 | (valueT) (i.sib.base << 0 |
3544 | | i.sib.index << 3 |
3545 | | i.sib.scale << 6), |
3546 | 1); |
3547 | } |
3548 | } |
3549 | |
3550 | if (i.disp_operands) |
3551 | output_disp (insn_start_frag, insn_start_off); |
3552 | |
3553 | if (i.imm_operands) |
3554 | output_imm (insn_start_frag, insn_start_off); |
3555 | } |
3556 | |
3557 | #ifdef DEBUG386 |
3558 | if (flag_debug) |
3559 | { |
3560 | pi ("" /*line*/, &i); |
3561 | } |
3562 | #endif /* DEBUG386 */ |
3563 | } |
3564 | |
3565 | static void |
3566 | output_disp (insn_start_frag, insn_start_off) |
3567 | fragS *insn_start_frag; |
3568 | offsetT insn_start_off; |
3569 | { |
3570 | char *p; |
3571 | unsigned int n; |
3572 | |
3573 | for (n = 0; n < i.operands; n++) |
3574 | { |
3575 | if (i.types[n] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000)) |
3576 | { |
3577 | if (i.op[n].disps->X_op == O_constant) |
3578 | { |
3579 | int size; |
3580 | offsetT val; |
3581 | |
3582 | size = 4; |
3583 | if (i.types[n] & (Disp80x1000 | Disp160x2000 | Disp640x10000)) |
3584 | { |
3585 | size = 2; |
3586 | if (i.types[n] & Disp80x1000) |
3587 | size = 1; |
3588 | if (i.types[n] & Disp640x10000) |
3589 | size = 8; |
3590 | } |
3591 | val = offset_in_range (i.op[n].disps->X_add_number, |
3592 | size); |
3593 | p = frag_more (size); |
3594 | md_number_to_charsnumber_to_chars_littleendian (p, val, size); |
3595 | } |
3596 | else |
3597 | { |
3598 | enum bfd_reloc_code_real reloc_type; |
3599 | int size = 4; |
3600 | int sign = 0; |
3601 | int pcrel = (i.flags[n] & Operand_PCrel1) != 0; |
3602 | |
3603 | /* The PC relative address is computed relative |
3604 | to the instruction boundary, so in case immediate |
3605 | fields follows, we need to adjust the value. */ |
3606 | if (pcrel && i.imm_operands) |
3607 | { |
3608 | int imm_size = 4; |
3609 | unsigned int n1; |
3610 | |
3611 | for (n1 = 0; n1 < i.operands; n1++) |
3612 | if (i.types[n1] & Imm(0x10|0x20|0x40|0x100|0x80|0x200)) |
3613 | { |
3614 | if (i.types[n1] & (Imm80x10 | Imm8S0x20 | Imm160x40 | Imm640x200)) |
3615 | { |
3616 | imm_size = 2; |
3617 | if (i.types[n1] & (Imm80x10 | Imm8S0x20)) |
3618 | imm_size = 1; |
3619 | if (i.types[n1] & Imm640x200) |
3620 | imm_size = 8; |
3621 | } |
3622 | break; |
3623 | } |
3624 | /* We should find the immediate. */ |
3625 | if (n1 == i.operands) |
3626 | abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 3626, __PRETTY_FUNCTION__); |
3627 | i.op[n].disps->X_add_number -= imm_size; |
3628 | } |
3629 | |
3630 | if (i.types[n] & Disp32S0x8000) |
3631 | sign = 1; |
3632 | |
3633 | if (i.types[n] & (Disp160x2000 | Disp640x10000)) |
3634 | { |
3635 | size = 2; |
3636 | if (i.types[n] & Disp640x10000) |
3637 | size = 8; |
3638 | } |
3639 | |
3640 | p = frag_more (size); |
3641 | reloc_type = reloc (size, pcrel, sign, i.reloc[n]); |
3642 | if (GOT_symbol |
3643 | && GOT_symbol == i.op[n].disps->X_add_symbol |
3644 | && (((reloc_type == BFD_RELOC_32 |
3645 | || reloc_type == BFD_RELOC_X86_64_32S |
3646 | || (reloc_type == BFD_RELOC_64 |
3647 | && object_64bit)) |
3648 | && (i.op[n].disps->X_op == O_symbol |
3649 | || (i.op[n].disps->X_op == O_add |
3650 | && ((symbol_get_value_expression |
3651 | (i.op[n].disps->X_op_symbol)->X_op) |
3652 | == O_subtract)))) |
3653 | || reloc_type == BFD_RELOC_32_PCREL)) |
3654 | { |
3655 | offsetT add; |
3656 | |
3657 | if (insn_start_frag == frag_now) |
3658 | add = (p - frag_now->fr_literal) - insn_start_off; |
3659 | else |
3660 | { |
3661 | fragS *fr; |
3662 | |
3663 | add = insn_start_frag->fr_fix - insn_start_off; |
3664 | for (fr = insn_start_frag->fr_next; |
3665 | fr && fr != frag_now; fr = fr->fr_next) |
3666 | add += fr->fr_fix; |
3667 | add += p - frag_now->fr_literal; |
3668 | } |
3669 | |
3670 | if (!object_64bit) |
3671 | { |
3672 | reloc_type = BFD_RELOC_386_GOTPC; |
3673 | i.op[n].imms->X_add_number += add; |
3674 | } |
3675 | else if (reloc_type == BFD_RELOC_64) |
3676 | reloc_type = BFD_RELOC_X86_64_GOTPC64; |
3677 | else |
3678 | /* Don't do the adjustment for x86-64, as there |
3679 | the pcrel addressing is relative to the _next_ |
3680 | insn, and that is taken care of in other code. */ |
3681 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
3682 | } |
3683 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
3684 | i.op[n].disps, pcrel, reloc_type); |
3685 | } |
3686 | } |
3687 | } |
3688 | } |
3689 | |
3690 | static void |
3691 | output_imm (insn_start_frag, insn_start_off) |
3692 | fragS *insn_start_frag; |
3693 | offsetT insn_start_off; |
3694 | { |
3695 | char *p; |
3696 | unsigned int n; |
3697 | |
3698 | for (n = 0; n < i.operands; n++) |
3699 | { |
3700 | if (i.types[n] & Imm(0x10|0x20|0x40|0x100|0x80|0x200)) |
3701 | { |
3702 | if (i.op[n].imms->X_op == O_constant) |
3703 | { |
3704 | int size; |
3705 | offsetT val; |
3706 | |
3707 | size = 4; |
3708 | if (i.types[n] & (Imm80x10 | Imm8S0x20 | Imm160x40 | Imm640x200)) |
3709 | { |
3710 | size = 2; |
3711 | if (i.types[n] & (Imm80x10 | Imm8S0x20)) |
3712 | size = 1; |
3713 | else if (i.types[n] & Imm640x200) |
3714 | size = 8; |
3715 | } |
3716 | val = offset_in_range (i.op[n].imms->X_add_number, |
3717 | size); |
3718 | p = frag_more (size); |
3719 | md_number_to_charsnumber_to_chars_littleendian (p, val, size); |
3720 | } |
3721 | else |
3722 | { |
3723 | /* Not absolute_section. |
3724 | Need a 32-bit fixup (don't support 8bit |
3725 | non-absolute imms). Try to support other |
3726 | sizes ... */ |
3727 | enum bfd_reloc_code_real reloc_type; |
3728 | int size = 4; |
3729 | int sign = 0; |
3730 | |
3731 | if ((i.types[n] & (Imm32S0x100)) |
3732 | && (i.suffix == QWORD_MNEM_SUFFIX'q' |
3733 | || (!i.suffix && (i.tm.opcode_modifier & No_lSuf0x100000)))) |
3734 | sign = 1; |
3735 | if (i.types[n] & (Imm80x10 | Imm8S0x20 | Imm160x40 | Imm640x200)) |
3736 | { |
3737 | size = 2; |
3738 | if (i.types[n] & (Imm80x10 | Imm8S0x20)) |
3739 | size = 1; |
3740 | if (i.types[n] & Imm640x200) |
3741 | size = 8; |
3742 | } |
3743 | |
3744 | p = frag_more (size); |
3745 | reloc_type = reloc (size, 0, sign, i.reloc[n]); |
3746 | |
3747 | /* This is tough to explain. We end up with this one if we |
3748 | * have operands that look like |
3749 | * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to |
3750 | * obtain the absolute address of the GOT, and it is strongly |
3751 | * preferable from a performance point of view to avoid using |
3752 | * a runtime relocation for this. The actual sequence of |
3753 | * instructions often look something like: |
3754 | * |
3755 | * call .L66 |
3756 | * .L66: |
3757 | * popl %ebx |
3758 | * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx |
3759 | * |
3760 | * The call and pop essentially return the absolute address |
3761 | * of the label .L66 and store it in %ebx. The linker itself |
3762 | * will ultimately change the first operand of the addl so |
3763 | * that %ebx points to the GOT, but to keep things simple, the |
3764 | * .o file must have this operand set so that it generates not |
3765 | * the absolute address of .L66, but the absolute address of |
3766 | * itself. This allows the linker itself simply treat a GOTPC |
3767 | * relocation as asking for a pcrel offset to the GOT to be |
3768 | * added in, and the addend of the relocation is stored in the |
3769 | * operand field for the instruction itself. |
3770 | * |
3771 | * Our job here is to fix the operand so that it would add |
3772 | * the correct offset so that %ebx would point to itself. The |
3773 | * thing that is tricky is that .-.L66 will point to the |
3774 | * beginning of the instruction, so we need to further modify |
3775 | * the operand so that it will point to itself. There are |
3776 | * other cases where you have something like: |
3777 | * |
3778 | * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66] |
3779 | * |
3780 | * and here no correction would be required. Internally in |
3781 | * the assembler we treat operands of this form as not being |
3782 | * pcrel since the '.' is explicitly mentioned, and I wonder |
3783 | * whether it would simplify matters to do it this way. Who |
3784 | * knows. In earlier versions of the PIC patches, the |
3785 | * pcrel_adjust field was used to store the correction, but |
3786 | * since the expression is not pcrel, I felt it would be |
3787 | * confusing to do it this way. */ |
3788 | |
3789 | if ((reloc_type == BFD_RELOC_32 |
3790 | || reloc_type == BFD_RELOC_X86_64_32S |
3791 | || reloc_type == BFD_RELOC_64) |
3792 | && GOT_symbol |
3793 | && GOT_symbol == i.op[n].imms->X_add_symbol |
3794 | && (i.op[n].imms->X_op == O_symbol |
3795 | || (i.op[n].imms->X_op == O_add |
3796 | && ((symbol_get_value_expression |
3797 | (i.op[n].imms->X_op_symbol)->X_op) |
3798 | == O_subtract)))) |
3799 | { |
3800 | offsetT add; |
3801 | |
3802 | if (insn_start_frag == frag_now) |
3803 | add = (p - frag_now->fr_literal) - insn_start_off; |
3804 | else |
3805 | { |
3806 | fragS *fr; |
3807 | |
3808 | add = insn_start_frag->fr_fix - insn_start_off; |
3809 | for (fr = insn_start_frag->fr_next; |
3810 | fr && fr != frag_now; fr = fr->fr_next) |
3811 | add += fr->fr_fix; |
3812 | add += p - frag_now->fr_literal; |
3813 | } |
3814 | |
3815 | if (!object_64bit) |
3816 | reloc_type = BFD_RELOC_386_GOTPC; |
3817 | else if (size == 4) |
3818 | reloc_type = BFD_RELOC_X86_64_GOTPC32; |
3819 | else if (size == 8) |
3820 | reloc_type = BFD_RELOC_X86_64_GOTPC64; |
3821 | i.op[n].imms->X_add_number += add; |
3822 | } |
3823 | fix_new_exp (frag_now, p - frag_now->fr_literal, size, |
3824 | i.op[n].imms, 0, reloc_type); |
3825 | } |
3826 | } |
3827 | } |
3828 | } |
3829 | |
3830 | /* x86_cons_fix_new is called via the expression parsing code when a |
3831 | reloc is needed. We use this hook to get the correct .got reloc. */ |
3832 | static enum bfd_reloc_code_real got_reloc = NO_RELOCBFD_RELOC_NONE; |
3833 | static int cons_sign = -1; |
3834 | |
3835 | void |
3836 | x86_cons_fix_new (fragS *frag, |
3837 | unsigned int off, |
3838 | unsigned int len, |
3839 | expressionS *exp) |
3840 | { |
3841 | enum bfd_reloc_code_real r = reloc (len, 0, cons_sign, got_reloc); |
3842 | |
3843 | got_reloc = NO_RELOCBFD_RELOC_NONE; |
3844 | |
3845 | #ifdef TE_PE |
3846 | if (exp->X_op == O_secrel) |
3847 | { |
3848 | exp->X_op = O_symbol; |
3849 | r = BFD_RELOC_32_SECREL; |
3850 | } |
3851 | #endif |
3852 | |
3853 | fix_new_exp (frag, off, len, exp, 0, r); |
3854 | } |
3855 | |
3856 | #if (!defined (OBJ_ELF1) && !defined (OBJ_MAYBE_ELF)) || defined (LEX_AT) |
3857 | # define lex_got(reloc, adjust, types) NULL((void*)0) |
3858 | #else |
3859 | /* Parse operands of the form |
3860 | <symbol>@GOTOFF+<nnn> |
3861 | and similar .plt or .got references. |
3862 | |
3863 | If we find one, set up the correct relocation in RELOC and copy the |
3864 | input string, minus the `@GOTOFF' into a malloc'd buffer for |
3865 | parsing by the calling routine. Return this buffer, and if ADJUST |
3866 | is non-null set it to the length of the string we removed from the |
3867 | input line. Otherwise return NULL. */ |
3868 | static char * |
3869 | lex_got (enum bfd_reloc_code_real *reloc, |
3870 | int *adjust, |
3871 | unsigned int *types) |
3872 | { |
3873 | /* Some of the relocations depend on the size of what field is to |
3874 | be relocated. But in our callers i386_immediate and i386_displacement |
3875 | we don't yet know the operand size (this will be set by insn |
3876 | matching). Hence we record the word32 relocation here, |
3877 | and adjust the reloc according to the real size in reloc(). */ |
3878 | static const struct { |
3879 | const char *str; |
3880 | const enum bfd_reloc_code_real rel[2]; |
3881 | const unsigned int types64; |
3882 | } gotrel[] = { |
3883 | { "PLTOFF", { 0, BFD_RELOC_X86_64_PLTOFF64 }, Imm640x200 }, |
3884 | { "PLT", { BFD_RELOC_386_PLT32, BFD_RELOC_X86_64_PLT32 }, Imm320x80|Imm32S0x100|Disp320x4000 }, |
3885 | { "GOTPLT", { 0, BFD_RELOC_X86_64_GOTPLT64 }, Imm640x200|Disp640x10000 }, |
3886 | { "GOTOFF", { BFD_RELOC_386_GOTOFF, BFD_RELOC_X86_64_GOTOFF64 }, Imm640x200|Disp640x10000 }, |
3887 | { "GOTPCREL", { 0, BFD_RELOC_X86_64_GOTPCREL }, Imm320x80|Imm32S0x100|Disp320x4000 }, |
3888 | { "TLSGD", { BFD_RELOC_386_TLS_GD, BFD_RELOC_X86_64_TLSGD }, Imm320x80|Imm32S0x100|Disp320x4000 }, |
3889 | { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0 }, 0 }, |
3890 | { "TLSLD", { 0, BFD_RELOC_X86_64_TLSLD }, Imm320x80|Imm32S0x100|Disp320x4000 }, |
3891 | { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, BFD_RELOC_X86_64_GOTTPOFF }, Imm320x80|Imm32S0x100|Disp320x4000 }, |
3892 | { "TPOFF", { BFD_RELOC_386_TLS_LE_32, BFD_RELOC_X86_64_TPOFF32 }, Imm320x80|Imm32S0x100|Imm640x200|Disp320x4000|Disp640x10000 }, |
3893 | { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0 }, 0 }, |
3894 | { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, BFD_RELOC_X86_64_DTPOFF32 }, Imm320x80|Imm32S0x100|Imm640x200|Disp320x4000|Disp640x10000 }, |
3895 | { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0 }, 0 }, |
3896 | { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0 }, 0 }, |
3897 | { "GOT", { BFD_RELOC_386_GOT32, BFD_RELOC_X86_64_GOT32 }, Imm320x80|Imm32S0x100|Disp320x4000|Imm640x200 }, |
3898 | { "TLSDESC", { BFD_RELOC_386_TLS_GOTDESC, BFD_RELOC_X86_64_GOTPC32_TLSDESC }, Imm320x80|Imm32S0x100|Disp320x4000 }, |
3899 | { "TLSCALL", { BFD_RELOC_386_TLS_DESC_CALL, BFD_RELOC_X86_64_TLSDESC_CALL }, Imm320x80|Imm32S0x100|Disp320x4000 } |
3900 | }; |
3901 | char *cp; |
3902 | unsigned int j; |
3903 | |
3904 | if (!IS_ELF1) |
3905 | return NULL((void*)0); |
3906 | |
3907 | for (cp = input_line_pointer; *cp != '@'; cp++) |
3908 | if (is_end_of_line[(unsigned char) *cp]) |
3909 | return NULL((void*)0); |
3910 | |
3911 | for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++) |
3912 | { |
3913 | int len; |
3914 | |
3915 | len = strlen (gotrel[j].str); |
3916 | if (strncasecmp (cp + 1, gotrel[j].str, len) == 0) |
3917 | { |
3918 | if (gotrel[j].rel[object_64bit] != 0) |
3919 | { |
3920 | int first, second; |
3921 | char *tmpbuf, *past_reloc; |
3922 | |
3923 | *reloc = gotrel[j].rel[object_64bit]; |
3924 | if (adjust) |
3925 | *adjust = len; |
3926 | |
3927 | if (types) |
3928 | { |
3929 | if (flag_code != CODE_64BIT) |
3930 | *types = Imm320x80|Disp320x4000; |
3931 | else |
3932 | *types = gotrel[j].types64; |
3933 | } |
3934 | |
3935 | if (GOT_symbol == NULL((void*)0)) |
3936 | GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME"_GLOBAL_OFFSET_TABLE_"); |
3937 | |
3938 | /* Replace the relocation token with ' ', so that |
3939 | errors like foo@GOTOFF1 will be detected. */ |
3940 | |
3941 | /* The length of the first part of our input line. */ |
3942 | first = cp - input_line_pointer; |
3943 | |
3944 | /* The second part goes from after the reloc token until |
3945 | (and including) an end_of_line char. Don't use strlen |
3946 | here as the end_of_line char may not be a NUL. */ |
3947 | past_reloc = cp + 1 + len; |
3948 | for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; ) |
3949 | ; |
3950 | second = cp - past_reloc; |
3951 | |
3952 | /* Allocate and copy string. The trailing NUL shouldn't |
3953 | be necessary, but be safe. */ |
3954 | tmpbuf = xmalloc (first + second + 2); |
3955 | memcpy (tmpbuf, input_line_pointer, first); |
3956 | tmpbuf[first] = ' '; |
3957 | memcpy (tmpbuf + first + 1, past_reloc, second); |
3958 | tmpbuf[first + second + 1] = '\0'; |
3959 | return tmpbuf; |
3960 | } |
3961 | |
3962 | as_bad (_("@%s reloc is not supported with %d-bit output format")("@%s reloc is not supported with %d-bit output format"), |
3963 | gotrel[j].str, 1 << (5 + object_64bit)); |
3964 | return NULL((void*)0); |
3965 | } |
3966 | } |
3967 | |
3968 | /* Might be a symbol version string. Don't as_bad here. */ |
3969 | return NULL((void*)0); |
3970 | } |
3971 | |
3972 | void |
3973 | x86_cons (exp, size) |
3974 | expressionS *exp; |
3975 | int size; |
3976 | { |
3977 | if (size == 4 || (object_64bit && size == 8)) |
3978 | { |
3979 | /* Handle @GOTOFF and the like in an expression. */ |
3980 | char *save; |
3981 | char *gotfree_input_line; |
3982 | int adjust; |
3983 | |
3984 | save = input_line_pointer; |
3985 | gotfree_input_line = lex_got (&got_reloc, &adjust, NULL((void*)0)); |
3986 | if (gotfree_input_line) |
3987 | input_line_pointer = gotfree_input_line; |
3988 | |
3989 | expression (exp)expr (0, exp, expr_normal); |
3990 | |
3991 | if (gotfree_input_line) |
3992 | { |
3993 | /* expression () has merrily parsed up to the end of line, |
3994 | or a comma - in the wrong buffer. Transfer how far |
3995 | input_line_pointer has moved to the right buffer. */ |
3996 | input_line_pointer = (save |
3997 | + (input_line_pointer - gotfree_input_line) |
3998 | + adjust); |
3999 | free (gotfree_input_line); |
4000 | } |
4001 | } |
4002 | else |
4003 | expression (exp)expr (0, exp, expr_normal); |
4004 | } |
4005 | #endif |
4006 | |
4007 | static void signed_cons (int size) |
4008 | { |
4009 | if (flag_code == CODE_64BIT) |
4010 | cons_sign = 1; |
4011 | cons (size); |
4012 | cons_sign = -1; |
4013 | } |
4014 | |
4015 | #ifdef TE_PE |
4016 | static void |
4017 | pe_directive_secrel (dummy) |
4018 | int dummy ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
4019 | { |
4020 | expressionS exp; |
4021 | |
4022 | do |
4023 | { |
4024 | expression (&exp)expr (0, &exp, expr_normal); |
4025 | if (exp.X_op == O_symbol) |
4026 | exp.X_op = O_secrel; |
4027 | |
4028 | emit_expr (&exp, 4); |
4029 | } |
4030 | while (*input_line_pointer++ == ','); |
4031 | |
4032 | input_line_pointer--; |
4033 | demand_empty_rest_of_line (); |
4034 | } |
4035 | #endif |
4036 | |
4037 | static int i386_immediate PARAMS ((char *))(char *); |
4038 | |
4039 | static int |
4040 | i386_immediate (imm_start) |
4041 | char *imm_start; |
4042 | { |
4043 | char *save_input_line_pointer; |
4044 | char *gotfree_input_line; |
4045 | segT exp_seg = 0; |
4046 | expressionS *exp; |
4047 | unsigned int types = ~0U; |
4048 | |
4049 | if (i.imm_operands == MAX_IMMEDIATE_OPERANDS2) |
4050 | { |
4051 | as_bad (_("only 1 or 2 immediate operands are allowed")("only 1 or 2 immediate operands are allowed")); |
4052 | return 0; |
4053 | } |
4054 | |
4055 | exp = &im_expressions[i.imm_operands++]; |
4056 | i.op[this_operand].imms = exp; |
4057 | |
4058 | if (is_space_char (*imm_start)((*imm_start) == ' ')) |
4059 | ++imm_start; |
4060 | |
4061 | save_input_line_pointer = input_line_pointer; |
4062 | input_line_pointer = imm_start; |
4063 | |
4064 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL((void*)0), &types); |
4065 | if (gotfree_input_line) |
4066 | input_line_pointer = gotfree_input_line; |
4067 | |
4068 | exp_seg = expression (exp)expr (0, exp, expr_normal); |
4069 | |
4070 | SKIP_WHITESPACE ()((*input_line_pointer == ' ') ? ++input_line_pointer : 0); |
4071 | if (*input_line_pointer) |
4072 | as_bad (_("junk `%s' after expression")("junk `%s' after expression"), input_line_pointer); |
4073 | |
4074 | input_line_pointer = save_input_line_pointer; |
4075 | if (gotfree_input_line) |
4076 | free (gotfree_input_line); |
4077 | |
4078 | if (exp->X_op == O_absent || exp->X_op == O_big) |
4079 | { |
4080 | /* Missing or bad expr becomes absolute 0. */ |
4081 | as_bad (_("missing or invalid immediate expression `%s' taken as 0")("missing or invalid immediate expression `%s' taken as 0"), |
4082 | imm_start); |
4083 | exp->X_op = O_constant; |
4084 | exp->X_add_number = 0; |
4085 | exp->X_add_symbol = (symbolS *) 0; |
4086 | exp->X_op_symbol = (symbolS *) 0; |
4087 | } |
4088 | else if (exp->X_op == O_constant) |
4089 | { |
4090 | /* Size it properly later. */ |
4091 | i.types[this_operand] |= Imm640x200; |
4092 | /* If BFD64, sign extend val. */ |
4093 | if (!use_rela_relocations) |
4094 | if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0) |
4095 | exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31); |
4096 | } |
4097 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
4098 | else if (OUTPUT_FLAVORbfd_target_elf_flavour == bfd_target_aout_flavour |
4099 | && exp_seg != absolute_section((asection *) &bfd_abs_section) |
4100 | && exp_seg != text_section |
4101 | && exp_seg != data_section |
4102 | && exp_seg != bss_section |
4103 | && exp_seg != undefined_section((asection *) &bfd_und_section) |
4104 | && !bfd_is_com_section (exp_seg)(((exp_seg)->flags & 0x1000) != 0)) |
4105 | { |
4106 | as_bad (_("unimplemented segment %s in operand")("unimplemented segment %s in operand"), exp_seg->name); |
4107 | return 0; |
4108 | } |
4109 | #endif |
4110 | else |
4111 | { |
4112 | /* This is an address. The size of the address will be |
4113 | determined later, depending on destination register, |
4114 | suffix, or the default for the section. */ |
4115 | i.types[this_operand] |= Imm80x10 | Imm160x40 | Imm320x80 | Imm32S0x100 | Imm640x200; |
4116 | i.types[this_operand] &= types; |
4117 | } |
4118 | |
4119 | return 1; |
4120 | } |
4121 | |
4122 | static char *i386_scale PARAMS ((char *))(char *); |
4123 | |
4124 | static char * |
4125 | i386_scale (scale) |
4126 | char *scale; |
4127 | { |
4128 | offsetT val; |
4129 | char *save = input_line_pointer; |
4130 | |
4131 | input_line_pointer = scale; |
4132 | val = get_absolute_expression (); |
4133 | |
4134 | switch (val) |
4135 | { |
4136 | case 1: |
4137 | i.log2_scale_factor = 0; |
4138 | break; |
4139 | case 2: |
4140 | i.log2_scale_factor = 1; |
4141 | break; |
4142 | case 4: |
4143 | i.log2_scale_factor = 2; |
4144 | break; |
4145 | case 8: |
4146 | i.log2_scale_factor = 3; |
4147 | break; |
4148 | default: |
4149 | { |
4150 | char sep = *input_line_pointer; |
4151 | |
4152 | *input_line_pointer = '\0'; |
4153 | as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'")("expecting scale factor of 1, 2, 4, or 8: got `%s'"), |
4154 | scale); |
4155 | *input_line_pointer = sep; |
4156 | input_line_pointer = save; |
4157 | return NULL((void*)0); |
4158 | } |
4159 | } |
4160 | if (i.log2_scale_factor != 0 && i.index_reg == 0) |
4161 | { |
4162 | as_warn (_("scale factor of %d without an index register")("scale factor of %d without an index register"), |
4163 | 1 << i.log2_scale_factor); |
4164 | #if SCALE1_WHEN_NO_INDEX1 |
4165 | i.log2_scale_factor = 0; |
4166 | #endif |
4167 | } |
4168 | scale = input_line_pointer; |
4169 | input_line_pointer = save; |
4170 | return scale; |
4171 | } |
4172 | |
4173 | static int i386_displacement PARAMS ((char *, char *))(char *, char *); |
4174 | |
4175 | static int |
4176 | i386_displacement (disp_start, disp_end) |
4177 | char *disp_start; |
4178 | char *disp_end; |
4179 | { |
4180 | expressionS *exp; |
4181 | segT exp_seg = 0; |
4182 | char *save_input_line_pointer; |
4183 | char *gotfree_input_line; |
4184 | int bigdisp, override; |
4185 | unsigned int types = Disp(0x1000|0x2000|0x4000|0x8000|0x10000); |
4186 | |
4187 | if ((i.types[this_operand] & JumpAbsolute0x8000000) |
4188 | || !(current_templates->start->opcode_modifier & (Jump0x40 | JumpDword0x80))) |
4189 | { |
4190 | bigdisp = Disp320x4000; |
4191 | override = (i.prefix[ADDR_PREFIX2] != 0); |
4192 | } |
4193 | else |
4194 | { |
4195 | /* For PC-relative branches, the width of the displacement |
4196 | is dependent upon data size, not address size. */ |
4197 | bigdisp = 0; |
4198 | override = (i.prefix[DATA_PREFIX3] != 0); |
4199 | } |
4200 | if (flag_code == CODE_64BIT) |
4201 | { |
4202 | if (!bigdisp) |
4203 | bigdisp = (override || i.suffix == WORD_MNEM_SUFFIX'w') |
4204 | ? Disp160x2000 |
4205 | : Disp32S0x8000 | Disp320x4000; |
4206 | else if (!override) |
4207 | bigdisp = Disp640x10000 | Disp32S0x8000 | Disp320x4000; |
4208 | } |
4209 | else |
4210 | { |
4211 | if (!bigdisp) |
4212 | { |
4213 | if (!override) |
4214 | override = (i.suffix == (flag_code != CODE_16BIT |
4215 | ? WORD_MNEM_SUFFIX'w' |
4216 | : LONG_MNEM_SUFFIX'l')); |
4217 | bigdisp = Disp320x4000; |
4218 | } |
4219 | if ((flag_code == CODE_16BIT) ^ override) |
4220 | bigdisp = Disp160x2000; |
4221 | } |
4222 | i.types[this_operand] |= bigdisp; |
4223 | |
4224 | exp = &disp_expressions[i.disp_operands]; |
4225 | i.op[this_operand].disps = exp; |
4226 | i.disp_operands++; |
4227 | save_input_line_pointer = input_line_pointer; |
4228 | input_line_pointer = disp_start; |
4229 | END_STRING_AND_SAVE (disp_end)do { *save_stack_p++ = *(disp_end); *(disp_end) = '\0'; } while (0); |
4230 | |
4231 | #ifndef GCC_ASM_O_HACK0 |
4232 | #define GCC_ASM_O_HACK0 0 |
4233 | #endif |
4234 | #if GCC_ASM_O_HACK0 |
4235 | END_STRING_AND_SAVE (disp_end + 1)do { *save_stack_p++ = *(disp_end + 1); *(disp_end + 1) = '\0' ; } while (0); |
4236 | if ((i.types[this_operand] & BaseIndex0x800) != 0 |
4237 | && displacement_string_end[-1] == '+') |
4238 | { |
4239 | /* This hack is to avoid a warning when using the "o" |
4240 | constraint within gcc asm statements. |
4241 | For instance: |
4242 | |
4243 | #define _set_tssldt_desc(n,addr,limit,type) \ |
4244 | __asm__ __volatile__ ( \ |
4245 | "movw %w2,%0\n\t" \ |
4246 | "movw %w1,2+%0\n\t" \ |
4247 | "rorl $16,%1\n\t" \ |
4248 | "movb %b1,4+%0\n\t" \ |
4249 | "movb %4,5+%0\n\t" \ |
4250 | "movb $0,6+%0\n\t" \ |
4251 | "movb %h1,7+%0\n\t" \ |
4252 | "rorl $16,%1" \ |
4253 | : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type)) |
4254 | |
4255 | This works great except that the output assembler ends |
4256 | up looking a bit weird if it turns out that there is |
4257 | no offset. You end up producing code that looks like: |
4258 | |
4259 | #APP |
4260 | movw $235,(%eax) |
4261 | movw %dx,2+(%eax) |
4262 | rorl $16,%edx |
4263 | movb %dl,4+(%eax) |
4264 | movb $137,5+(%eax) |
4265 | movb $0,6+(%eax) |
4266 | movb %dh,7+(%eax) |
4267 | rorl $16,%edx |
4268 | #NO_APP |
4269 | |
4270 | So here we provide the missing zero. */ |
4271 | |
4272 | *displacement_string_end = '0'; |
4273 | } |
4274 | #endif |
4275 | gotfree_input_line = lex_got (&i.reloc[this_operand], NULL((void*)0), &types); |
4276 | if (gotfree_input_line) |
4277 | input_line_pointer = gotfree_input_line; |
4278 | |
4279 | exp_seg = expression (exp)expr (0, exp, expr_normal); |
4280 | |
4281 | SKIP_WHITESPACE ()((*input_line_pointer == ' ') ? ++input_line_pointer : 0); |
4282 | if (*input_line_pointer) |
4283 | as_bad (_("junk `%s' after expression")("junk `%s' after expression"), input_line_pointer); |
4284 | #if GCC_ASM_O_HACK0 |
4285 | RESTORE_END_STRING (disp_end + 1)do { *(disp_end + 1) = *--save_stack_p; } while (0); |
4286 | #endif |
4287 | RESTORE_END_STRING (disp_end)do { *(disp_end) = *--save_stack_p; } while (0); |
4288 | input_line_pointer = save_input_line_pointer; |
4289 | if (gotfree_input_line) |
4290 | free (gotfree_input_line); |
4291 | |
4292 | /* We do this to make sure that the section symbol is in |
4293 | the symbol table. We will ultimately change the relocation |
4294 | to be relative to the beginning of the section. */ |
4295 | if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF |
4296 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
4297 | || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
4298 | { |
4299 | if (exp->X_op != O_symbol) |
4300 | { |
4301 | as_bad (_("bad expression used with @%s")("bad expression used with @%s"), |
4302 | (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL |
4303 | ? "GOTPCREL" |
4304 | : "GOTOFF")); |
4305 | return 0; |
4306 | } |
4307 | |
4308 | if (S_IS_LOCAL (exp->X_add_symbol) |
4309 | && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section((asection *) &bfd_und_section)) |
4310 | section_symbol (S_GET_SEGMENT (exp->X_add_symbol)); |
4311 | exp->X_op = O_subtract; |
4312 | exp->X_op_symbol = GOT_symbol; |
4313 | if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL) |
4314 | i.reloc[this_operand] = BFD_RELOC_32_PCREL; |
4315 | else if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTOFF64) |
4316 | i.reloc[this_operand] = BFD_RELOC_64; |
4317 | else |
4318 | i.reloc[this_operand] = BFD_RELOC_32; |
4319 | } |
4320 | |
4321 | if (exp->X_op == O_absent || exp->X_op == O_big) |
4322 | { |
4323 | /* Missing or bad expr becomes absolute 0. */ |
4324 | as_bad (_("missing or invalid displacement expression `%s' taken as 0")("missing or invalid displacement expression `%s' taken as 0" ), |
4325 | disp_start); |
4326 | exp->X_op = O_constant; |
4327 | exp->X_add_number = 0; |
4328 | exp->X_add_symbol = (symbolS *) 0; |
4329 | exp->X_op_symbol = (symbolS *) 0; |
4330 | } |
4331 | |
4332 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
4333 | if (exp->X_op != O_constant |
4334 | && OUTPUT_FLAVORbfd_target_elf_flavour == bfd_target_aout_flavour |
4335 | && exp_seg != absolute_section((asection *) &bfd_abs_section) |
4336 | && exp_seg != text_section |
4337 | && exp_seg != data_section |
4338 | && exp_seg != bss_section |
4339 | && exp_seg != undefined_section((asection *) &bfd_und_section) |
4340 | && !bfd_is_com_section (exp_seg)(((exp_seg)->flags & 0x1000) != 0)) |
4341 | { |
4342 | as_bad (_("unimplemented segment %s in operand")("unimplemented segment %s in operand"), exp_seg->name); |
4343 | return 0; |
4344 | } |
4345 | #endif |
4346 | |
4347 | if (!(i.types[this_operand] & ~Disp(0x1000|0x2000|0x4000|0x8000|0x10000))) |
4348 | i.types[this_operand] &= types; |
4349 | |
4350 | return 1; |
4351 | } |
4352 | |
4353 | static int i386_index_check PARAMS ((const char *))(const char *); |
4354 | |
4355 | /* Make sure the memory operand we've been dealt is valid. |
4356 | Return 1 on success, 0 on a failure. */ |
4357 | |
4358 | static int |
4359 | i386_index_check (operand_string) |
4360 | const char *operand_string; |
4361 | { |
4362 | int ok; |
4363 | #if INFER_ADDR_PREFIX1 |
4364 | int fudged = 0; |
4365 | |
4366 | tryprefix: |
4367 | #endif |
4368 | ok = 1; |
4369 | if ((current_templates->start->cpu_flags & CpuSVME0x80000) |
4370 | && current_templates->end[-1].operand_types[0] == AnyMem(0x1000|0x2000|0x4000|0x8000|0x800|0x80000000)) |
4371 | { |
4372 | /* Memory operands of SVME insns are special in that they only allow |
4373 | rAX as their memory address and ignore any segment override. */ |
4374 | unsigned RegXX; |
4375 | |
4376 | /* SKINIT is even more restrictive: it always requires EAX. */ |
4377 | if (strcmp (current_templates->start->name, "skinit") == 0) |
4378 | RegXX = Reg320x4; |
4379 | else if (flag_code == CODE_64BIT) |
4380 | RegXX = i.prefix[ADDR_PREFIX2] == 0 ? Reg640x8 : Reg320x4; |
4381 | else |
4382 | RegXX = (flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX2] != 0) |
4383 | ? Reg160x2 |
4384 | : Reg320x4; |
4385 | if (!i.base_reg |
4386 | || !(i.base_reg->reg_type & Acc0x4000000) |
4387 | || !(i.base_reg->reg_type & RegXX) |
4388 | || i.index_reg |
4389 | || (i.types[0] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000))) |
4390 | ok = 0; |
4391 | } |
4392 | else if (flag_code == CODE_64BIT) |
4393 | { |
4394 | unsigned RegXX = (i.prefix[ADDR_PREFIX2] == 0 ? Reg640x8 : Reg320x4); |
4395 | |
4396 | if ((i.base_reg |
4397 | && ((i.base_reg->reg_type & RegXX) == 0) |
4398 | && (i.base_reg->reg_type != BaseIndex0x800 |
4399 | || i.index_reg)) |
4400 | || (i.index_reg |
4401 | && ((i.index_reg->reg_type & (RegXX | BaseIndex0x800)) |
4402 | != (RegXX | BaseIndex0x800)))) |
4403 | ok = 0; |
4404 | } |
4405 | else |
4406 | { |
4407 | if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX2] != 0)) |
4408 | { |
4409 | /* 16bit checks. */ |
4410 | if ((i.base_reg |
4411 | && ((i.base_reg->reg_type & (Reg160x2 | BaseIndex0x800 | RegRex0x1)) |
4412 | != (Reg160x2 | BaseIndex0x800))) |
4413 | || (i.index_reg |
4414 | && (((i.index_reg->reg_type & (Reg160x2 | BaseIndex0x800)) |
4415 | != (Reg160x2 | BaseIndex0x800)) |
4416 | || !(i.base_reg |
4417 | && i.base_reg->reg_num < 6 |
4418 | && i.index_reg->reg_num >= 6 |
4419 | && i.log2_scale_factor == 0)))) |
4420 | ok = 0; |
4421 | } |
4422 | else |
4423 | { |
4424 | /* 32bit checks. */ |
4425 | if ((i.base_reg |
4426 | && (i.base_reg->reg_type & (Reg320x4 | RegRex0x1)) != Reg320x4) |
4427 | || (i.index_reg |
4428 | && ((i.index_reg->reg_type & (Reg320x4 | BaseIndex0x800 | RegRex0x1)) |
4429 | != (Reg320x4 | BaseIndex0x800)))) |
4430 | ok = 0; |
4431 | } |
4432 | } |
4433 | if (!ok) |
4434 | { |
4435 | #if INFER_ADDR_PREFIX1 |
4436 | if (i.prefix[ADDR_PREFIX2] == 0) |
4437 | { |
4438 | i.prefix[ADDR_PREFIX2] = ADDR_PREFIX_OPCODE0x67; |
4439 | i.prefixes += 1; |
4440 | /* Change the size of any displacement too. At most one of |
4441 | Disp16 or Disp32 is set. |
4442 | FIXME. There doesn't seem to be any real need for separate |
4443 | Disp16 and Disp32 flags. The same goes for Imm16 and Imm32. |
4444 | Removing them would probably clean up the code quite a lot. */ |
4445 | if (flag_code != CODE_64BIT && (i.types[this_operand] & (Disp160x2000 | Disp320x4000))) |
4446 | i.types[this_operand] ^= (Disp160x2000 | Disp320x4000); |
4447 | fudged = 1; |
4448 | goto tryprefix; |
4449 | } |
4450 | if (fudged) |
4451 | as_bad (_("`%s' is not a valid base/index expression")("`%s' is not a valid base/index expression"), |
4452 | operand_string); |
4453 | else |
4454 | #endif |
4455 | as_bad (_("`%s' is not a valid %s bit base/index expression")("`%s' is not a valid %s bit base/index expression"), |
4456 | operand_string, |
4457 | flag_code_names[flag_code]); |
4458 | } |
4459 | return ok; |
4460 | } |
4461 | |
4462 | /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero |
4463 | on error. */ |
4464 | |
4465 | static int |
4466 | i386_operand (operand_string) |
4467 | char *operand_string; |
4468 | { |
4469 | const reg_entry *r; |
4470 | char *end_op; |
4471 | char *op_string = operand_string; |
4472 | |
4473 | if (is_space_char (*op_string)((*op_string) == ' ')) |
4474 | ++op_string; |
4475 | |
4476 | /* We check for an absolute prefix (differentiating, |
4477 | for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */ |
4478 | if (*op_string == ABSOLUTE_PREFIX'*') |
4479 | { |
4480 | ++op_string; |
4481 | if (is_space_char (*op_string)((*op_string) == ' ')) |
4482 | ++op_string; |
4483 | i.types[this_operand] |= JumpAbsolute0x8000000; |
4484 | } |
4485 | |
4486 | /* Check if operand is a register. */ |
4487 | if ((r = parse_register (op_string, &end_op)) != NULL((void*)0)) |
4488 | { |
4489 | /* Check for a segment override by searching for ':' after a |
4490 | segment register. */ |
4491 | op_string = end_op; |
4492 | if (is_space_char (*op_string)((*op_string) == ' ')) |
4493 | ++op_string; |
4494 | if (*op_string == ':' && (r->reg_type & (SReg20x1000000 | SReg30x2000000))) |
4495 | { |
4496 | switch (r->reg_num) |
4497 | { |
4498 | case 0: |
4499 | i.seg[i.mem_operands] = &es; |
4500 | break; |
4501 | case 1: |
4502 | i.seg[i.mem_operands] = &cs; |
4503 | break; |
4504 | case 2: |
4505 | i.seg[i.mem_operands] = &ss; |
4506 | break; |
4507 | case 3: |
4508 | i.seg[i.mem_operands] = &ds; |
4509 | break; |
4510 | case 4: |
4511 | i.seg[i.mem_operands] = &fs; |
4512 | break; |
4513 | case 5: |
4514 | i.seg[i.mem_operands] = &gs; |
4515 | break; |
4516 | } |
4517 | |
4518 | /* Skip the ':' and whitespace. */ |
4519 | ++op_string; |
4520 | if (is_space_char (*op_string)((*op_string) == ' ')) |
4521 | ++op_string; |
4522 | |
4523 | if (!is_digit_char (*op_string)(digit_chars[(unsigned char) *op_string]) |
4524 | && !is_identifier_char (*op_string)(identifier_chars[(unsigned char) *op_string]) |
4525 | && *op_string != '(' |
4526 | && *op_string != ABSOLUTE_PREFIX'*') |
4527 | { |
4528 | as_bad (_("bad memory operand `%s'")("bad memory operand `%s'"), op_string); |
4529 | return 0; |
4530 | } |
4531 | /* Handle case of %es:*foo. */ |
4532 | if (*op_string == ABSOLUTE_PREFIX'*') |
4533 | { |
4534 | ++op_string; |
4535 | if (is_space_char (*op_string)((*op_string) == ' ')) |
4536 | ++op_string; |
4537 | i.types[this_operand] |= JumpAbsolute0x8000000; |
4538 | } |
4539 | goto do_memory_reference; |
4540 | } |
4541 | if (*op_string) |
4542 | { |
4543 | as_bad (_("junk `%s' after register")("junk `%s' after register"), op_string); |
4544 | return 0; |
4545 | } |
4546 | i.types[this_operand] |= r->reg_type & ~BaseIndex0x800; |
4547 | i.op[this_operand].regs = r; |
4548 | i.reg_operands++; |
4549 | } |
4550 | else if (*op_string == REGISTER_PREFIX'%') |
4551 | { |
4552 | as_bad (_("bad register name `%s'")("bad register name `%s'"), op_string); |
4553 | return 0; |
4554 | } |
4555 | else if (*op_string == IMMEDIATE_PREFIX'$') |
4556 | { |
4557 | ++op_string; |
4558 | if (i.types[this_operand] & JumpAbsolute0x8000000) |
4559 | { |
4560 | as_bad (_("immediate operand illegal with absolute jump")("immediate operand illegal with absolute jump")); |
4561 | return 0; |
4562 | } |
4563 | if (!i386_immediate (op_string)) |
4564 | return 0; |
4565 | } |
4566 | else if (is_digit_char (*op_string)(digit_chars[(unsigned char) *op_string]) |
4567 | || is_identifier_char (*op_string)(identifier_chars[(unsigned char) *op_string]) |
4568 | || *op_string == '(') |
4569 | { |
4570 | /* This is a memory reference of some sort. */ |
4571 | char *base_string; |
4572 | |
4573 | /* Start and end of displacement string expression (if found). */ |
4574 | char *displacement_string_start; |
4575 | char *displacement_string_end; |
4576 | |
4577 | do_memory_reference: |
4578 | if ((i.mem_operands == 1 |
4579 | && (current_templates->start->opcode_modifier & IsString0x2000000) == 0) |
4580 | || i.mem_operands == 2) |
4581 | { |
4582 | as_bad (_("too many memory references for `%s'")("too many memory references for `%s'"), |
4583 | current_templates->start->name); |
4584 | return 0; |
4585 | } |
4586 | |
4587 | /* Check for base index form. We detect the base index form by |
4588 | looking for an ')' at the end of the operand, searching |
4589 | for the '(' matching it, and finding a REGISTER_PREFIX or ',' |
4590 | after the '('. */ |
4591 | base_string = op_string + strlen (op_string); |
4592 | |
4593 | --base_string; |
4594 | if (is_space_char (*base_string)((*base_string) == ' ')) |
4595 | --base_string; |
4596 | |
4597 | /* If we only have a displacement, set-up for it to be parsed later. */ |
4598 | displacement_string_start = op_string; |
4599 | displacement_string_end = base_string + 1; |
4600 | |
4601 | if (*base_string == ')') |
4602 | { |
4603 | char *temp_string; |
4604 | unsigned int parens_balanced = 1; |
4605 | /* We've already checked that the number of left & right ()'s are |
4606 | equal, so this loop will not be infinite. */ |
4607 | do |
4608 | { |
4609 | base_string--; |
4610 | if (*base_string == ')') |
4611 | parens_balanced++; |
4612 | if (*base_string == '(') |
4613 | parens_balanced--; |
4614 | } |
4615 | while (parens_balanced); |
4616 | |
4617 | temp_string = base_string; |
4618 | |
4619 | /* Skip past '(' and whitespace. */ |
4620 | ++base_string; |
4621 | if (is_space_char (*base_string)((*base_string) == ' ')) |
4622 | ++base_string; |
4623 | |
4624 | if (*base_string == ',' |
4625 | || ((i.base_reg = parse_register (base_string, &end_op)) != NULL((void*)0))) |
4626 | { |
4627 | displacement_string_end = temp_string; |
4628 | |
4629 | i.types[this_operand] |= BaseIndex0x800; |
4630 | |
4631 | if (i.base_reg) |
4632 | { |
4633 | base_string = end_op; |
4634 | if (is_space_char (*base_string)((*base_string) == ' ')) |
4635 | ++base_string; |
4636 | } |
4637 | |
4638 | /* There may be an index reg or scale factor here. */ |
4639 | if (*base_string == ',') |
4640 | { |
4641 | ++base_string; |
4642 | if (is_space_char (*base_string)((*base_string) == ' ')) |
4643 | ++base_string; |
4644 | |
4645 | if ((i.index_reg = parse_register (base_string, &end_op)) != NULL((void*)0)) |
4646 | { |
4647 | base_string = end_op; |
4648 | if (is_space_char (*base_string)((*base_string) == ' ')) |
4649 | ++base_string; |
4650 | if (*base_string == ',') |
4651 | { |
4652 | ++base_string; |
4653 | if (is_space_char (*base_string)((*base_string) == ' ')) |
4654 | ++base_string; |
4655 | } |
4656 | else if (*base_string != ')') |
4657 | { |
4658 | as_bad (_("expecting `,' or `)' after index register in `%s'")("expecting `,' or `)' after index register in `%s'"), |
4659 | operand_string); |
4660 | return 0; |
4661 | } |
4662 | } |
4663 | else if (*base_string == REGISTER_PREFIX'%') |
4664 | { |
4665 | as_bad (_("bad register name `%s'")("bad register name `%s'"), base_string); |
4666 | return 0; |
4667 | } |
4668 | |
4669 | /* Check for scale factor. */ |
4670 | if (*base_string != ')') |
4671 | { |
4672 | char *end_scale = i386_scale (base_string); |
4673 | |
4674 | if (!end_scale) |
4675 | return 0; |
4676 | |
4677 | base_string = end_scale; |
4678 | if (is_space_char (*base_string)((*base_string) == ' ')) |
4679 | ++base_string; |
4680 | if (*base_string != ')') |
4681 | { |
4682 | as_bad (_("expecting `)' after scale factor in `%s'")("expecting `)' after scale factor in `%s'"), |
4683 | operand_string); |
4684 | return 0; |
4685 | } |
4686 | } |
4687 | else if (!i.index_reg) |
4688 | { |
4689 | as_bad (_("expecting index register or scale factor after `,'; got '%c'")("expecting index register or scale factor after `,'; got '%c'" ), |
4690 | *base_string); |
4691 | return 0; |
4692 | } |
4693 | } |
4694 | else if (*base_string != ')') |
4695 | { |
4696 | as_bad (_("expecting `,' or `)' after base register in `%s'")("expecting `,' or `)' after base register in `%s'"), |
4697 | operand_string); |
4698 | return 0; |
4699 | } |
4700 | } |
4701 | else if (*base_string == REGISTER_PREFIX'%') |
4702 | { |
4703 | as_bad (_("bad register name `%s'")("bad register name `%s'"), base_string); |
4704 | return 0; |
4705 | } |
4706 | } |
4707 | |
4708 | /* If there's an expression beginning the operand, parse it, |
4709 | assuming displacement_string_start and |
4710 | displacement_string_end are meaningful. */ |
4711 | if (displacement_string_start != displacement_string_end) |
4712 | { |
4713 | if (!i386_displacement (displacement_string_start, |
4714 | displacement_string_end)) |
4715 | return 0; |
4716 | } |
4717 | |
4718 | /* Special case for (%dx) while doing input/output op. */ |
4719 | if (i.base_reg |
4720 | && i.base_reg->reg_type == (Reg160x2 | InOutPortReg0x20000) |
4721 | && i.index_reg == 0 |
4722 | && i.log2_scale_factor == 0 |
4723 | && i.seg[i.mem_operands] == 0 |
4724 | && (i.types[this_operand] & Disp(0x1000|0x2000|0x4000|0x8000|0x10000)) == 0) |
4725 | { |
4726 | i.types[this_operand] = InOutPortReg0x20000; |
4727 | return 1; |
4728 | } |
4729 | |
4730 | if (i386_index_check (operand_string) == 0) |
4731 | return 0; |
4732 | i.mem_operands++; |
4733 | } |
4734 | else |
4735 | { |
4736 | /* It's not a memory operand; argh! */ |
4737 | as_bad (_("invalid char %s beginning operand %d `%s'")("invalid char %s beginning operand %d `%s'"), |
4738 | output_invalid (*op_string), |
4739 | this_operand + 1, |
4740 | op_string); |
4741 | return 0; |
4742 | } |
4743 | return 1; /* Normal return. */ |
4744 | } |
4745 | |
4746 | /* md_estimate_size_before_relax() |
4747 | |
4748 | Called just before relax() for rs_machine_dependent frags. The x86 |
4749 | assembler uses these frags to handle variable size jump |
4750 | instructions. |
4751 | |
4752 | Any symbol that is now undefined will not become defined. |
4753 | Return the correct fr_subtype in the frag. |
4754 | Return the initial "guess for variable size of frag" to caller. |
4755 | The guess is actually the growth beyond the fixed part. Whatever |
4756 | we do to grow the fixed or variable part contributes to our |
4757 | returned value. */ |
4758 | |
4759 | int |
4760 | md_estimate_size_before_relax (fragP, segment) |
4761 | fragS *fragP; |
4762 | segT segment; |
4763 | { |
4764 | /* We've already got fragP->fr_subtype right; all we have to do is |
4765 | check for un-relaxable symbols. On an ELF system, we can't relax |
4766 | an externally visible symbol, because it may be overridden by a |
4767 | shared library. */ |
4768 | if (S_GET_SEGMENT (fragP->fr_symbol) != segment |
4769 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
4770 | || (IS_ELF1 |
4771 | && (S_IS_EXTERNAL (fragP->fr_symbol) |
4772 | || S_IS_WEAK (fragP->fr_symbol))) |
4773 | #endif |
4774 | ) |
4775 | { |
4776 | /* Symbol is undefined in this segment, or we need to keep a |
4777 | reloc so that weak symbols can be overridden. */ |
4778 | int size = (fragP->fr_subtype & CODE161) ? 2 : 4; |
4779 | enum bfd_reloc_code_real reloc_type; |
4780 | unsigned char *opcode; |
4781 | int old_fr_fix; |
4782 | |
4783 | if (fragP->fr_var != NO_RELOCBFD_RELOC_NONE) |
4784 | reloc_type = fragP->fr_var; |
4785 | else if (size == 2) |
4786 | reloc_type = BFD_RELOC_16_PCREL; |
4787 | else |
4788 | reloc_type = BFD_RELOC_32_PCREL; |
4789 | |
4790 | old_fr_fix = fragP->fr_fix; |
4791 | opcode = (unsigned char *) fragP->fr_opcode; |
4792 | |
4793 | switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype)((fragP->fr_subtype) >> 2)) |
4794 | { |
4795 | case UNCOND_JUMP0: |
4796 | /* Make jmp (0xeb) a (d)word displacement jump. */ |
4797 | opcode[0] = 0xe9; |
4798 | fragP->fr_fix += size; |
4799 | fix_new (fragP, old_fr_fix, size, |
4800 | fragP->fr_symbol, |
4801 | fragP->fr_offset, 1, |
4802 | reloc_type); |
4803 | break; |
4804 | |
4805 | case COND_JUMP862: |
4806 | if (size == 2 |
4807 | && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOCBFD_RELOC_NONE)) |
4808 | { |
4809 | /* Negate the condition, and branch past an |
4810 | unconditional jump. */ |
4811 | opcode[0] ^= 1; |
4812 | opcode[1] = 3; |
4813 | /* Insert an unconditional jump. */ |
4814 | opcode[2] = 0xe9; |
4815 | /* We added two extra opcode bytes, and have a two byte |
4816 | offset. */ |
4817 | fragP->fr_fix += 2 + 2; |
4818 | fix_new (fragP, old_fr_fix + 2, 2, |
4819 | fragP->fr_symbol, |
4820 | fragP->fr_offset, 1, |
4821 | reloc_type); |
4822 | break; |
4823 | } |
4824 | /* Fall through. */ |
4825 | |
4826 | case COND_JUMP1: |
4827 | if (no_cond_jump_promotion && fragP->fr_var == NO_RELOCBFD_RELOC_NONE) |
4828 | { |
4829 | fixS *fixP; |
4830 | |
4831 | fragP->fr_fix += 1; |
4832 | fixP = fix_new (fragP, old_fr_fix, 1, |
4833 | fragP->fr_symbol, |
4834 | fragP->fr_offset, 1, |
4835 | BFD_RELOC_8_PCREL); |
4836 | fixP->fx_signed = 1; |
4837 | break; |
4838 | } |
4839 | |
4840 | /* This changes the byte-displacement jump 0x7N |
4841 | to the (d)word-displacement jump 0x0f,0x8N. */ |
4842 | opcode[1] = opcode[0] + 0x10; |
4843 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE0x0f; |
4844 | /* We've added an opcode byte. */ |
4845 | fragP->fr_fix += 1 + size; |
4846 | fix_new (fragP, old_fr_fix + 1, size, |
4847 | fragP->fr_symbol, |
4848 | fragP->fr_offset, 1, |
4849 | reloc_type); |
4850 | break; |
4851 | |
4852 | default: |
4853 | BAD_CASE (fragP->fr_subtype){ as_fatal (("Case value %ld unexpected at line %d of file \"%s\"\n" ), (long) fragP->fr_subtype, 4853, "/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" ); }; |
4854 | break; |
4855 | } |
4856 | frag_wane (fragP); |
4857 | return fragP->fr_fix - old_fr_fix; |
4858 | } |
4859 | |
4860 | /* Guess size depending on current relax state. Initially the relax |
4861 | state will correspond to a short jump and we return 1, because |
4862 | the variable part of the frag (the branch offset) is one byte |
4863 | long. However, we can relax a section more than once and in that |
4864 | case we must either set fr_subtype back to the unrelaxed state, |
4865 | or return the value for the appropriate branch. */ |
4866 | return md_relax_table[fragP->fr_subtype].rlx_length; |
4867 | } |
4868 | |
4869 | /* Called after relax() is finished. |
4870 | |
4871 | In: Address of frag. |
4872 | fr_type == rs_machine_dependent. |
4873 | fr_subtype is what the address relaxed to. |
4874 | |
4875 | Out: Any fixSs and constants are set up. |
4876 | Caller will turn frag into a ".space 0". */ |
4877 | |
4878 | void |
4879 | md_convert_frag (abfd, sec, fragP) |
4880 | bfd *abfd ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
4881 | segT sec ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
4882 | fragS *fragP; |
4883 | { |
4884 | unsigned char *opcode; |
4885 | unsigned char *where_to_put_displacement = NULL((void*)0); |
4886 | offsetT target_address; |
4887 | offsetT opcode_address; |
4888 | unsigned int extension = 0; |
4889 | offsetT displacement_from_opcode_start; |
4890 | |
4891 | opcode = (unsigned char *) fragP->fr_opcode; |
4892 | |
4893 | /* Address we want to reach in file space. */ |
4894 | target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset; |
4895 | |
4896 | /* Address opcode resides at in file space. */ |
4897 | opcode_address = fragP->fr_address + fragP->fr_fix; |
4898 | |
4899 | /* Displacement from opcode start to fill into instruction. */ |
4900 | displacement_from_opcode_start = target_address - opcode_address; |
4901 | |
4902 | if ((fragP->fr_subtype & BIG2) == 0) |
4903 | { |
4904 | /* Don't have to change opcode. */ |
4905 | extension = 1; /* 1 opcode + 1 displacement */ |
4906 | where_to_put_displacement = &opcode[1]; |
4907 | } |
4908 | else |
4909 | { |
4910 | if (no_cond_jump_promotion |
4911 | && TYPE_FROM_RELAX_STATE (fragP->fr_subtype)((fragP->fr_subtype) >> 2) != UNCOND_JUMP0) |
4912 | as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required")("long jump required")); |
4913 | |
4914 | switch (fragP->fr_subtype) |
4915 | { |
4916 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)((relax_substateT) (((0) << 2) | (2))): |
4917 | extension = 4; /* 1 opcode + 4 displacement */ |
4918 | opcode[0] = 0xe9; |
4919 | where_to_put_displacement = &opcode[1]; |
4920 | break; |
4921 | |
4922 | case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)((relax_substateT) (((0) << 2) | ((2 | 1)))): |
4923 | extension = 2; /* 1 opcode + 2 displacement */ |
4924 | opcode[0] = 0xe9; |
4925 | where_to_put_displacement = &opcode[1]; |
4926 | break; |
4927 | |
4928 | case ENCODE_RELAX_STATE (COND_JUMP, BIG)((relax_substateT) (((1) << 2) | (2))): |
4929 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG)((relax_substateT) (((2) << 2) | (2))): |
4930 | extension = 5; /* 2 opcode + 4 displacement */ |
4931 | opcode[1] = opcode[0] + 0x10; |
4932 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE0x0f; |
4933 | where_to_put_displacement = &opcode[2]; |
4934 | break; |
4935 | |
4936 | case ENCODE_RELAX_STATE (COND_JUMP, BIG16)((relax_substateT) (((1) << 2) | ((2 | 1)))): |
4937 | extension = 3; /* 2 opcode + 2 displacement */ |
4938 | opcode[1] = opcode[0] + 0x10; |
4939 | opcode[0] = TWO_BYTE_OPCODE_ESCAPE0x0f; |
4940 | where_to_put_displacement = &opcode[2]; |
4941 | break; |
4942 | |
4943 | case ENCODE_RELAX_STATE (COND_JUMP86, BIG16)((relax_substateT) (((2) << 2) | ((2 | 1)))): |
4944 | extension = 4; |
4945 | opcode[0] ^= 1; |
4946 | opcode[1] = 3; |
4947 | opcode[2] = 0xe9; |
4948 | where_to_put_displacement = &opcode[3]; |
4949 | break; |
4950 | |
4951 | default: |
4952 | BAD_CASE (fragP->fr_subtype){ as_fatal (("Case value %ld unexpected at line %d of file \"%s\"\n" ), (long) fragP->fr_subtype, 4952, "/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" ); }; |
4953 | break; |
4954 | } |
4955 | } |
4956 | |
4957 | /* If size if less then four we are sure that the operand fits, |
4958 | but if it's 4, then it could be that the displacement is larger |
4959 | then -/+ 2GB. */ |
4960 | if (DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)((((fragP->fr_subtype) & 3) == 2 ? 4 : (((fragP->fr_subtype ) & 3) == (2 | 1) ? 2 : 1))) == 4 |
4961 | && object_64bit |
4962 | && ((addressT) (displacement_from_opcode_start - extension |
4963 | + ((addressT) 1 << 31)) |
4964 | > (((addressT) 2 << 31) - 1))) |
4965 | { |
4966 | as_bad_where (fragP->fr_file, fragP->fr_line, |
4967 | _("jump target out of range")("jump target out of range")); |
4968 | /* Make us emit 0. */ |
4969 | displacement_from_opcode_start = extension; |
4970 | } |
4971 | /* Now put displacement after opcode. */ |
4972 | md_number_to_charsnumber_to_chars_littleendian ((char *) where_to_put_displacement, |
4973 | (valueT) (displacement_from_opcode_start - extension), |
4974 | DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype)((((fragP->fr_subtype) & 3) == 2 ? 4 : (((fragP->fr_subtype ) & 3) == (2 | 1) ? 2 : 1)))); |
4975 | fragP->fr_fix += extension; |
4976 | } |
4977 | |
4978 | /* Size of byte displacement jmp. */ |
4979 | int md_short_jump_size = 2; |
4980 | |
4981 | /* Size of dword displacement jmp. */ |
4982 | int md_long_jump_size = 5; |
4983 | |
4984 | void |
4985 | md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol) |
4986 | char *ptr; |
4987 | addressT from_addr, to_addr; |
4988 | fragS *frag ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
4989 | symbolS *to_symbol ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
4990 | { |
4991 | offsetT offset; |
4992 | |
4993 | offset = to_addr - (from_addr + 2); |
4994 | /* Opcode for byte-disp jump. */ |
4995 | md_number_to_charsnumber_to_chars_littleendian (ptr, (valueT) 0xeb, 1); |
4996 | md_number_to_charsnumber_to_chars_littleendian (ptr + 1, (valueT) offset, 1); |
4997 | } |
4998 | |
4999 | void |
5000 | md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol) |
5001 | char *ptr; |
5002 | addressT from_addr, to_addr; |
5003 | fragS *frag ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
5004 | symbolS *to_symbol ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
5005 | { |
5006 | offsetT offset; |
5007 | |
5008 | offset = to_addr - (from_addr + 5); |
5009 | md_number_to_charsnumber_to_chars_littleendian (ptr, (valueT) 0xe9, 1); |
5010 | md_number_to_charsnumber_to_chars_littleendian (ptr + 1, (valueT) offset, 4); |
5011 | } |
5012 | |
5013 | /* Apply a fixup (fixS) to segment data, once it has been determined |
5014 | by our caller that we have all the info we need to fix it up. |
5015 | |
5016 | On the 386, immediates, displacements, and data pointers are all in |
5017 | the same (little-endian) format, so we don't need to care about which |
5018 | we are handling. */ |
5019 | |
5020 | void |
5021 | md_apply_fix (fixP, valP, seg) |
5022 | /* The fix we're to put in. */ |
5023 | fixS *fixP; |
5024 | /* Pointer to the value of the bits. */ |
5025 | valueT *valP; |
5026 | /* Segment fix is from. */ |
5027 | segT seg ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
5028 | { |
5029 | char *p = fixP->fx_where + fixP->fx_frag->fr_literal; |
5030 | valueT value = *valP; |
5031 | |
5032 | #if !defined (TE_Mach) |
5033 | if (fixP->fx_pcrel) |
5034 | { |
5035 | switch (fixP->fx_r_type) |
5036 | { |
5037 | default: |
5038 | break; |
5039 | |
5040 | case BFD_RELOC_64: |
5041 | fixP->fx_r_type = BFD_RELOC_64_PCREL; |
5042 | break; |
5043 | case BFD_RELOC_32: |
5044 | case BFD_RELOC_X86_64_32S: |
5045 | fixP->fx_r_type = BFD_RELOC_32_PCREL; |
5046 | break; |
5047 | case BFD_RELOC_16: |
5048 | fixP->fx_r_type = BFD_RELOC_16_PCREL; |
5049 | break; |
5050 | case BFD_RELOC_8: |
5051 | fixP->fx_r_type = BFD_RELOC_8_PCREL; |
5052 | break; |
5053 | } |
5054 | } |
5055 | |
5056 | if (fixP->fx_addsy != NULL((void*)0) |
5057 | && (fixP->fx_r_type == BFD_RELOC_32_PCREL |
5058 | || fixP->fx_r_type == BFD_RELOC_64_PCREL |
5059 | || fixP->fx_r_type == BFD_RELOC_16_PCREL |
5060 | || fixP->fx_r_type == BFD_RELOC_8_PCREL) |
5061 | && !use_rela_relocations) |
5062 | { |
5063 | /* This is a hack. There should be a better way to handle this. |
5064 | This covers for the fact that bfd_install_relocation will |
5065 | subtract the current location (for partial_inplace, PC relative |
5066 | relocations); see more below. */ |
5067 | #ifndef OBJ_AOUT |
5068 | if (IS_ELF1 |
5069 | #ifdef TE_PE |
5070 | || OUTPUT_FLAVORbfd_target_elf_flavour == bfd_target_coff_flavour |
5071 | #endif |
5072 | ) |
5073 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
5074 | #endif |
5075 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
5076 | if (IS_ELF1) |
5077 | { |
5078 | segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy); |
5079 | |
5080 | if ((sym_seg == seg |
5081 | || (symbol_section_p (fixP->fx_addsy) |
5082 | && sym_seg != absolute_section((asection *) &bfd_abs_section))) |
5083 | && !generic_force_reloc (fixP)) |
5084 | { |
5085 | /* Yes, we add the values in twice. This is because |
5086 | bfd_install_relocation subtracts them out again. I think |
5087 | bfd_install_relocation is broken, but I don't dare change |
5088 | it. FIXME. */ |
5089 | value += fixP->fx_where + fixP->fx_frag->fr_address; |
5090 | } |
5091 | } |
5092 | #endif |
5093 | #if defined (OBJ_COFF) && defined (TE_PE) |
5094 | /* For some reason, the PE format does not store a |
5095 | section address offset for a PC relative symbol. */ |
5096 | if (S_GET_SEGMENT (fixP->fx_addsy) != seg |
5097 | || S_IS_WEAK (fixP->fx_addsy)) |
5098 | value += md_pcrel_from (fixP); |
5099 | #endif |
5100 | } |
5101 | |
5102 | /* Fix a few things - the dynamic linker expects certain values here, |
5103 | and we must not disappoint it. */ |
5104 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
5105 | if (IS_ELF1 && fixP->fx_addsy) |
5106 | switch (fixP->fx_r_type) |
5107 | { |
5108 | case BFD_RELOC_386_PLT32: |
5109 | case BFD_RELOC_X86_64_PLT32: |
5110 | /* Make the jump instruction point to the address of the operand. At |
5111 | runtime we merely add the offset to the actual PLT entry. */ |
5112 | value = -4; |
5113 | break; |
5114 | |
5115 | case BFD_RELOC_386_TLS_GD: |
5116 | case BFD_RELOC_386_TLS_LDM: |
5117 | case BFD_RELOC_386_TLS_IE_32: |
5118 | case BFD_RELOC_386_TLS_IE: |
5119 | case BFD_RELOC_386_TLS_GOTIE: |
5120 | case BFD_RELOC_386_TLS_GOTDESC: |
5121 | case BFD_RELOC_X86_64_TLSGD: |
5122 | case BFD_RELOC_X86_64_TLSLD: |
5123 | case BFD_RELOC_X86_64_GOTTPOFF: |
5124 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
5125 | value = 0; /* Fully resolved at runtime. No addend. */ |
5126 | /* Fallthrough */ |
5127 | case BFD_RELOC_386_TLS_LE: |
5128 | case BFD_RELOC_386_TLS_LDO_32: |
5129 | case BFD_RELOC_386_TLS_LE_32: |
5130 | case BFD_RELOC_X86_64_DTPOFF32: |
5131 | case BFD_RELOC_X86_64_DTPOFF64: |
5132 | case BFD_RELOC_X86_64_TPOFF32: |
5133 | case BFD_RELOC_X86_64_TPOFF64: |
5134 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
5135 | break; |
5136 | |
5137 | case BFD_RELOC_386_TLS_DESC_CALL: |
5138 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
5139 | value = 0; /* Fully resolved at runtime. No addend. */ |
Value stored to 'value' is never read | |
5140 | S_SET_THREAD_LOCAL (fixP->fx_addsy); |
5141 | fixP->fx_done = 0; |
5142 | return; |
5143 | |
5144 | case BFD_RELOC_386_GOT32: |
5145 | case BFD_RELOC_X86_64_GOT32: |
5146 | value = 0; /* Fully resolved at runtime. No addend. */ |
5147 | break; |
5148 | |
5149 | case BFD_RELOC_VTABLE_INHERIT: |
5150 | case BFD_RELOC_VTABLE_ENTRY: |
5151 | fixP->fx_done = 0; |
5152 | return; |
5153 | |
5154 | default: |
5155 | break; |
5156 | } |
5157 | #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */ |
5158 | *valP = value; |
5159 | #endif /* !defined (TE_Mach) */ |
5160 | |
5161 | /* Are we finished with this relocation now? */ |
5162 | if (fixP->fx_addsy == NULL((void*)0)) |
5163 | fixP->fx_done = 1; |
5164 | else if (use_rela_relocations) |
5165 | { |
5166 | fixP->fx_no_overflow = 1; |
5167 | /* Remember value for tc_gen_reloc. */ |
5168 | fixP->fx_addnumber = value; |
5169 | value = 0; |
5170 | } |
5171 | |
5172 | md_number_to_charsnumber_to_chars_littleendian (p, value, fixP->fx_size); |
5173 | } |
5174 | |
5175 | #define MAX_LITTLENUMS6 6 |
5176 | |
5177 | /* Turn the string pointed to by litP into a floating point constant |
5178 | of type TYPE, and emit the appropriate bytes. The number of |
5179 | LITTLENUMS emitted is stored in *SIZEP. An error message is |
5180 | returned, or NULL on OK. */ |
5181 | |
5182 | char * |
5183 | md_atof (type, litP, sizeP) |
5184 | int type; |
5185 | char *litP; |
5186 | int *sizeP; |
5187 | { |
5188 | int prec; |
5189 | LITTLENUM_TYPE words[MAX_LITTLENUMS6]; |
5190 | LITTLENUM_TYPE *wordP; |
5191 | char *t; |
5192 | |
5193 | switch (type) |
5194 | { |
5195 | case 'f': |
5196 | case 'F': |
5197 | prec = 2; |
5198 | break; |
5199 | |
5200 | case 'd': |
5201 | case 'D': |
5202 | prec = 4; |
5203 | break; |
5204 | |
5205 | case 'x': |
5206 | case 'X': |
5207 | prec = 5; |
5208 | break; |
5209 | |
5210 | default: |
5211 | *sizeP = 0; |
5212 | return _("Bad call to md_atof ()")("Bad call to md_atof ()"); |
5213 | } |
5214 | t = atof_ieee (input_line_pointer, type, words); |
5215 | if (t) |
5216 | input_line_pointer = t; |
5217 | |
5218 | *sizeP = prec * sizeof (LITTLENUM_TYPE); |
5219 | /* This loops outputs the LITTLENUMs in REVERSE order; in accord with |
5220 | the bigendian 386. */ |
5221 | for (wordP = words + prec - 1; prec--;) |
5222 | { |
5223 | md_number_to_charsnumber_to_chars_littleendian (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE)); |
5224 | litP += sizeof (LITTLENUM_TYPE); |
5225 | } |
5226 | return 0; |
5227 | } |
5228 | |
5229 | static char output_invalid_buf[8]; |
5230 | |
5231 | static char * |
5232 | output_invalid (c) |
5233 | int c; |
5234 | { |
5235 | if (ISPRINT (c)(_sch_istable[(c) & 0xff] & (unsigned short)(_sch_isprint ))) |
5236 | sprintf (output_invalid_buf, "'%c'", c); |
5237 | else |
5238 | sprintf (output_invalid_buf, "(0x%x)", (unsigned) c); |
5239 | return output_invalid_buf; |
5240 | } |
5241 | |
5242 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
5243 | |
5244 | static const reg_entry * |
5245 | parse_real_register (char *reg_string, char **end_op) |
5246 | { |
5247 | char *s = reg_string; |
5248 | char *p; |
5249 | char reg_name_given[MAX_REG_NAME_SIZE8 + 1]; |
5250 | const reg_entry *r; |
5251 | |
5252 | /* Skip possible REGISTER_PREFIX and possible whitespace. */ |
5253 | if (*s == REGISTER_PREFIX'%') |
5254 | ++s; |
5255 | |
5256 | if (is_space_char (*s)((*s) == ' ')) |
5257 | ++s; |
5258 | |
5259 | p = reg_name_given; |
5260 | while ((*p++ = register_chars[(unsigned char) *s]) != '\0') |
5261 | { |
5262 | if (p >= reg_name_given + MAX_REG_NAME_SIZE8) |
5263 | return (const reg_entry *) NULL((void*)0); |
5264 | s++; |
5265 | } |
5266 | |
5267 | /* For naked regs, make sure that we are not dealing with an identifier. |
5268 | This prevents confusing an identifier like `eax_var' with register |
5269 | `eax'. */ |
5270 | if (allow_naked_reg && identifier_chars[(unsigned char) *s]) |
5271 | return (const reg_entry *) NULL((void*)0); |
5272 | |
5273 | *end_op = s; |
5274 | |
5275 | r = (const reg_entry *) hash_find (reg_hash, reg_name_given); |
5276 | |
5277 | /* Handle floating point regs, allowing spaces in the (i) part. */ |
5278 | if (r == i386_regtab /* %st is first entry of table */) |
5279 | { |
5280 | if (is_space_char (*s)((*s) == ' ')) |
5281 | ++s; |
5282 | if (*s == '(') |
5283 | { |
5284 | ++s; |
5285 | if (is_space_char (*s)((*s) == ' ')) |
5286 | ++s; |
5287 | if (*s >= '0' && *s <= '7') |
5288 | { |
5289 | r = &i386_float_regtab[*s - '0']; |
5290 | ++s; |
5291 | if (is_space_char (*s)((*s) == ' ')) |
5292 | ++s; |
5293 | if (*s == ')') |
5294 | { |
5295 | *end_op = s + 1; |
5296 | return r; |
5297 | } |
5298 | } |
5299 | /* We have "%st(" then garbage. */ |
5300 | return (const reg_entry *) NULL((void*)0); |
5301 | } |
5302 | } |
5303 | |
5304 | if (r != NULL((void*)0) |
5305 | && ((r->reg_flags & (RegRex640x2 | RegRex0x1)) | (r->reg_type & Reg640x8)) != 0 |
5306 | && (r->reg_type != Control0x80000 || !(cpu_arch_flags & CpuSledgehammer0x400)) |
5307 | && flag_code != CODE_64BIT) |
5308 | return (const reg_entry *) NULL((void*)0); |
5309 | |
5310 | return r; |
5311 | } |
5312 | |
5313 | /* REG_STRING starts *before* REGISTER_PREFIX. */ |
5314 | |
5315 | static const reg_entry * |
5316 | parse_register (char *reg_string, char **end_op) |
5317 | { |
5318 | const reg_entry *r; |
5319 | |
5320 | if (*reg_string == REGISTER_PREFIX'%' || allow_naked_reg) |
5321 | r = parse_real_register (reg_string, end_op); |
5322 | else |
5323 | r = NULL((void*)0); |
5324 | if (!r) |
5325 | { |
5326 | char *save = input_line_pointer; |
5327 | char c; |
5328 | symbolS *symbolP; |
5329 | |
5330 | input_line_pointer = reg_string; |
5331 | c = get_symbol_end (); |
5332 | symbolP = symbol_find (reg_string); |
5333 | if (symbolP && S_GET_SEGMENT (symbolP) == reg_section) |
5334 | { |
5335 | const expressionS *e = symbol_get_value_expression (symbolP); |
5336 | |
5337 | know (e->X_op == O_register); |
5338 | know (e->X_add_number >= 0 && (valueT) e->X_add_number < ARRAY_SIZE (i386_regtab)); |
5339 | r = i386_regtab + e->X_add_number; |
5340 | *end_op = input_line_pointer; |
5341 | } |
5342 | *input_line_pointer = c; |
5343 | input_line_pointer = save; |
5344 | } |
5345 | return r; |
5346 | } |
5347 | |
5348 | int |
5349 | i386_parse_name (char *name, expressionS *e, char *nextcharP) |
5350 | { |
5351 | const reg_entry *r; |
5352 | char *end = input_line_pointer; |
5353 | |
5354 | *end = *nextcharP; |
5355 | r = parse_register (name, &input_line_pointer); |
5356 | if (r && end <= input_line_pointer) |
5357 | { |
5358 | *nextcharP = *input_line_pointer; |
5359 | *input_line_pointer = 0; |
5360 | e->X_op = O_register; |
5361 | e->X_add_number = r - i386_regtab; |
5362 | return 1; |
5363 | } |
5364 | input_line_pointer = end; |
5365 | *end = 0; |
5366 | return 0; |
5367 | } |
5368 | |
5369 | void |
5370 | md_operand (expressionS *e) |
5371 | { |
5372 | if (*input_line_pointer == REGISTER_PREFIX'%') |
5373 | { |
5374 | char *end; |
5375 | const reg_entry *r = parse_real_register (input_line_pointer, &end); |
5376 | |
5377 | if (r) |
5378 | { |
5379 | e->X_op = O_register; |
5380 | e->X_add_number = r - i386_regtab; |
5381 | input_line_pointer = end; |
5382 | } |
5383 | } |
5384 | } |
5385 | |
5386 | |
5387 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
5388 | const char *md_shortopts = "kVQ:sqn"; |
5389 | #else |
5390 | const char *md_shortopts = "qn"; |
5391 | #endif |
5392 | |
5393 | #define OPTION_32(190 + 0) (OPTION_MD_BASE190 + 0) |
5394 | #define OPTION_64(190 + 1) (OPTION_MD_BASE190 + 1) |
5395 | #define OPTION_DIVIDE(190 + 2) (OPTION_MD_BASE190 + 2) |
5396 | |
5397 | struct option md_longopts[] = { |
5398 | {"32", no_argument0, NULL((void*)0), OPTION_32(190 + 0)}, |
5399 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
5400 | {"64", no_argument0, NULL((void*)0), OPTION_64(190 + 1)}, |
5401 | #endif |
5402 | {"divide", no_argument0, NULL((void*)0), OPTION_DIVIDE(190 + 2)}, |
5403 | {NULL((void*)0), no_argument0, NULL((void*)0), 0} |
5404 | }; |
5405 | size_t md_longopts_size = sizeof (md_longopts); |
5406 | |
5407 | int |
5408 | md_parse_option (c, arg) |
5409 | int c; |
5410 | char *arg ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
5411 | { |
5412 | switch (c) |
5413 | { |
5414 | case 'n': |
5415 | optimize_align_code = 0; |
5416 | break; |
5417 | |
5418 | case 'q': |
5419 | quiet_warnings = 1; |
5420 | break; |
5421 | |
5422 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
5423 | /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section |
5424 | should be emitted or not. FIXME: Not implemented. */ |
5425 | case 'Q': |
5426 | break; |
5427 | |
5428 | /* -V: SVR4 argument to print version ID. */ |
5429 | case 'V': |
5430 | print_version_id (); |
5431 | break; |
5432 | |
5433 | /* -k: Ignore for FreeBSD compatibility. */ |
5434 | case 'k': |
5435 | break; |
5436 | |
5437 | case 's': |
5438 | /* -s: On i386 Solaris, this tells the native assembler to use |
5439 | .stab instead of .stab.excl. We always use .stab anyhow. */ |
5440 | break; |
5441 | |
5442 | case OPTION_64(190 + 1): |
5443 | { |
5444 | const char **list, **l; |
5445 | |
5446 | list = bfd_target_list (); |
5447 | for (l = list; *l != NULL((void*)0); l++) |
5448 | if (strcmp (*l, "elf64-x86-64") == 0) |
5449 | { |
5450 | default_arch = "x86_64"; |
5451 | break; |
5452 | } |
5453 | if (*l == NULL((void*)0)) |
5454 | as_fatal (_("No compiled in support for x86_64")("No compiled in support for x86_64")); |
5455 | free (list); |
5456 | } |
5457 | break; |
5458 | #endif |
5459 | |
5460 | case OPTION_32(190 + 0): |
5461 | default_arch = "i386"; |
5462 | break; |
5463 | |
5464 | case OPTION_DIVIDE(190 + 2): |
5465 | #ifdef SVR4_COMMENT_CHARS |
5466 | { |
5467 | char *n, *t; |
5468 | const char *s; |
5469 | |
5470 | n = (char *) xmalloc (strlen (i386_comment_chars) + 1); |
5471 | t = n; |
5472 | for (s = i386_comment_chars; *s != '\0'; s++) |
5473 | if (*s != '/') |
5474 | *t++ = *s; |
5475 | *t = '\0'; |
5476 | i386_comment_chars = n; |
5477 | } |
5478 | #endif |
5479 | break; |
5480 | |
5481 | default: |
5482 | return 0; |
5483 | } |
5484 | return 1; |
5485 | } |
5486 | |
5487 | void |
5488 | md_show_usage (stream) |
5489 | FILE *stream; |
5490 | { |
5491 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
5492 | fprintf (stream, _("\(" -Q ignored\n -V print assembler version number\n -k ignored\n" ) |
5493 | -Q ignored\n\(" -Q ignored\n -V print assembler version number\n -k ignored\n" ) |
5494 | -V print assembler version number\n\(" -Q ignored\n -V print assembler version number\n -k ignored\n" ) |
5495 | -k ignored\n")(" -Q ignored\n -V print assembler version number\n -k ignored\n" )); |
5496 | #endif |
5497 | fprintf (stream, _("\(" -n Do not optimize code alignment\n -q quieten some warnings\n" ) |
5498 | -n Do not optimize code alignment\n\(" -n Do not optimize code alignment\n -q quieten some warnings\n" ) |
5499 | -q quieten some warnings\n")(" -n Do not optimize code alignment\n -q quieten some warnings\n" )); |
5500 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
5501 | fprintf (stream, _("\(" -s ignored\n") |
5502 | -s ignored\n")(" -s ignored\n")); |
5503 | #endif |
5504 | #ifdef SVR4_COMMENT_CHARS |
5505 | fprintf (stream, _("\(" --divide do not treat `/' as a comment character\n" ) |
5506 | --divide do not treat `/' as a comment character\n")(" --divide do not treat `/' as a comment character\n" )); |
5507 | #else |
5508 | fprintf (stream, _("\(" --divide ignored\n") |
5509 | --divide ignored\n")(" --divide ignored\n")); |
5510 | #endif |
5511 | } |
5512 | |
5513 | #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \ |
5514 | || defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)) |
5515 | |
5516 | /* Pick the target format to use. */ |
5517 | |
5518 | const char * |
5519 | i386_target_format () |
5520 | { |
5521 | if (!strcmp (default_arch, "x86_64")) |
5522 | set_code_flag (CODE_64BIT); |
5523 | else if (!strcmp (default_arch, "i386")) |
5524 | set_code_flag (CODE_32BIT); |
5525 | else |
5526 | as_fatal (_("Unknown architecture")("Unknown architecture")); |
5527 | switch (OUTPUT_FLAVORbfd_target_elf_flavour) |
5528 | { |
5529 | #ifdef OBJ_MAYBE_AOUT |
5530 | case bfd_target_aout_flavour: |
5531 | return AOUT_TARGET_FORMAT"a.out-i386-netbsd"; |
5532 | #endif |
5533 | #ifdef OBJ_MAYBE_COFF |
5534 | case bfd_target_coff_flavour: |
5535 | return "coff-i386"; |
5536 | #endif |
5537 | #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF1) |
5538 | case bfd_target_elf_flavour: |
5539 | { |
5540 | if (flag_code == CODE_64BIT) |
5541 | { |
5542 | object_64bit = 1; |
5543 | use_rela_relocations = 1; |
5544 | } |
5545 | return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT"elf32-i386"; |
5546 | } |
5547 | #endif |
5548 | default: |
5549 | abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 5549, __PRETTY_FUNCTION__); |
5550 | return NULL((void*)0); |
5551 | } |
5552 | } |
5553 | |
5554 | #endif /* OBJ_MAYBE_ more than one */ |
5555 | |
5556 | #if (defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF)) |
5557 | void i386_elf_emit_arch_note () |
5558 | { |
5559 | if (IS_ELF1 && cpu_arch_name != NULL((void*)0)) |
5560 | { |
5561 | char *p; |
5562 | asection *seg = now_seg; |
5563 | subsegT subseg = now_subseg; |
5564 | Elf_Internal_Note i_note; |
5565 | Elf_External_Note e_note; |
5566 | asection *note_secp; |
5567 | int len; |
5568 | |
5569 | /* Create the .note section. */ |
5570 | note_secp = subseg_new (".note", 0); |
5571 | bfd_set_section_flags (stdoutput, |
5572 | note_secp, |
5573 | SEC_HAS_CONTENTS0x100 | SEC_READONLY0x008); |
5574 | |
5575 | /* Process the arch string. */ |
5576 | len = strlen (cpu_arch_name); |
5577 | |
5578 | i_note.namesz = len + 1; |
5579 | i_note.descsz = 0; |
5580 | i_note.type = NT_ARCH2; |
5581 | p = frag_more (sizeof (e_note.namesz)); |
5582 | md_number_to_charsnumber_to_chars_littleendian (p, (valueT) i_note.namesz, sizeof (e_note.namesz)); |
5583 | p = frag_more (sizeof (e_note.descsz)); |
5584 | md_number_to_charsnumber_to_chars_littleendian (p, (valueT) i_note.descsz, sizeof (e_note.descsz)); |
5585 | p = frag_more (sizeof (e_note.type)); |
5586 | md_number_to_charsnumber_to_chars_littleendian (p, (valueT) i_note.type, sizeof (e_note.type)); |
5587 | p = frag_more (len + 1); |
5588 | strcpy (p, cpu_arch_name); |
5589 | |
5590 | frag_align (2, 0, 0); |
5591 | |
5592 | subseg_set (seg, subseg); |
5593 | } |
5594 | } |
5595 | #endif |
5596 | |
5597 | symbolS * |
5598 | md_undefined_symbol (name) |
5599 | char *name; |
5600 | { |
5601 | if (name[0] == GLOBAL_OFFSET_TABLE_NAME"_GLOBAL_OFFSET_TABLE_"[0] |
5602 | && name[1] == GLOBAL_OFFSET_TABLE_NAME"_GLOBAL_OFFSET_TABLE_"[1] |
5603 | && name[2] == GLOBAL_OFFSET_TABLE_NAME"_GLOBAL_OFFSET_TABLE_"[2] |
5604 | && strcmp (name, GLOBAL_OFFSET_TABLE_NAME"_GLOBAL_OFFSET_TABLE_") == 0) |
5605 | { |
5606 | if (!GOT_symbol) |
5607 | { |
5608 | if (symbol_find (name)) |
5609 | as_bad (_("GOT already in symbol table")("GOT already in symbol table")); |
5610 | GOT_symbol = symbol_new (name, undefined_section((asection *) &bfd_und_section), |
5611 | (valueT) 0, &zero_address_frag); |
5612 | }; |
5613 | return GOT_symbol; |
5614 | } |
5615 | return 0; |
5616 | } |
5617 | |
5618 | /* Round up a section size to the appropriate boundary. */ |
5619 | |
5620 | valueT |
5621 | md_section_align (segment, size) |
5622 | segT segment ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
5623 | valueT size; |
5624 | { |
5625 | #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT)) |
5626 | if (OUTPUT_FLAVORbfd_target_elf_flavour == bfd_target_aout_flavour) |
5627 | { |
5628 | /* For a.out, force the section size to be aligned. If we don't do |
5629 | this, BFD will align it for us, but it will not write out the |
5630 | final bytes of the section. This may be a bug in BFD, but it is |
5631 | easier to fix it here since that is how the other a.out targets |
5632 | work. */ |
5633 | int align; |
5634 | |
5635 | align = bfd_get_section_alignment (stdoutput, segment)((segment)->alignment_power + 0); |
5636 | size = ((size + (1 << align) - 1) & ((valueT) -1 << align)); |
5637 | } |
5638 | #endif |
5639 | |
5640 | return size; |
5641 | } |
5642 | |
5643 | /* On the i386, PC-relative offsets are relative to the start of the |
5644 | next instruction. That is, the address of the offset, plus its |
5645 | size, since the offset is always the last part of the insn. */ |
5646 | |
5647 | long |
5648 | md_pcrel_from (fixP) |
5649 | fixS *fixP; |
5650 | { |
5651 | return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address; |
5652 | } |
5653 | |
5654 | #ifndef I386COFF |
5655 | |
5656 | static void |
5657 | s_bss (ignore) |
5658 | int ignore ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
5659 | { |
5660 | int temp; |
5661 | |
5662 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
5663 | if (IS_ELF1) |
5664 | obj_elf_section_change_hook (); |
5665 | #endif |
5666 | temp = get_absolute_expression (); |
5667 | subseg_set (bss_section, (subsegT) temp); |
5668 | demand_empty_rest_of_line (); |
5669 | } |
5670 | |
5671 | #endif |
5672 | |
5673 | void |
5674 | i386_validate_fix (fixp) |
5675 | fixS *fixp; |
5676 | { |
5677 | if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol) |
5678 | { |
5679 | if (fixp->fx_r_type == BFD_RELOC_32_PCREL) |
5680 | { |
5681 | if (!object_64bit) |
5682 | abort ()as_abort ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 5682, __PRETTY_FUNCTION__); |
5683 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL; |
5684 | } |
5685 | else |
5686 | { |
5687 | if (!object_64bit) |
5688 | fixp->fx_r_type = BFD_RELOC_386_GOTOFF; |
5689 | else |
5690 | fixp->fx_r_type = BFD_RELOC_X86_64_GOTOFF64; |
5691 | } |
5692 | fixp->fx_subsy = 0; |
5693 | } |
5694 | } |
5695 | |
5696 | arelent * |
5697 | tc_gen_reloc (section, fixp) |
5698 | asection *section ATTRIBUTE_UNUSED__attribute__ ((__unused__)); |
5699 | fixS *fixp; |
5700 | { |
5701 | arelent *rel; |
5702 | bfd_reloc_code_real_type code; |
5703 | |
5704 | switch (fixp->fx_r_type) |
5705 | { |
5706 | case BFD_RELOC_X86_64_PLT32: |
5707 | case BFD_RELOC_X86_64_GOT32: |
5708 | case BFD_RELOC_X86_64_GOTPCREL: |
5709 | case BFD_RELOC_386_PLT32: |
5710 | case BFD_RELOC_386_GOT32: |
5711 | case BFD_RELOC_386_GOTOFF: |
5712 | case BFD_RELOC_386_GOTPC: |
5713 | case BFD_RELOC_386_TLS_GD: |
5714 | case BFD_RELOC_386_TLS_LDM: |
5715 | case BFD_RELOC_386_TLS_LDO_32: |
5716 | case BFD_RELOC_386_TLS_IE_32: |
5717 | case BFD_RELOC_386_TLS_IE: |
5718 | case BFD_RELOC_386_TLS_GOTIE: |
5719 | case BFD_RELOC_386_TLS_LE_32: |
5720 | case BFD_RELOC_386_TLS_LE: |
5721 | case BFD_RELOC_386_TLS_GOTDESC: |
5722 | case BFD_RELOC_386_TLS_DESC_CALL: |
5723 | case BFD_RELOC_X86_64_TLSGD: |
5724 | case BFD_RELOC_X86_64_TLSLD: |
5725 | case BFD_RELOC_X86_64_DTPOFF32: |
5726 | case BFD_RELOC_X86_64_DTPOFF64: |
5727 | case BFD_RELOC_X86_64_GOTTPOFF: |
5728 | case BFD_RELOC_X86_64_TPOFF32: |
5729 | case BFD_RELOC_X86_64_TPOFF64: |
5730 | case BFD_RELOC_X86_64_GOTOFF64: |
5731 | case BFD_RELOC_X86_64_GOTPC32: |
5732 | case BFD_RELOC_X86_64_GOT64: |
5733 | case BFD_RELOC_X86_64_GOTPCREL64: |
5734 | case BFD_RELOC_X86_64_GOTPC64: |
5735 | case BFD_RELOC_X86_64_GOTPLT64: |
5736 | case BFD_RELOC_X86_64_PLTOFF64: |
5737 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
5738 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
5739 | case BFD_RELOC_RVA: |
5740 | case BFD_RELOC_VTABLE_ENTRY: |
5741 | case BFD_RELOC_VTABLE_INHERIT: |
5742 | #ifdef TE_PE |
5743 | case BFD_RELOC_32_SECREL: |
5744 | #endif |
5745 | code = fixp->fx_r_type; |
5746 | break; |
5747 | case BFD_RELOC_X86_64_32S: |
5748 | if (!fixp->fx_pcrel) |
5749 | { |
5750 | /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */ |
5751 | code = fixp->fx_r_type; |
5752 | break; |
5753 | } |
5754 | default: |
5755 | if (fixp->fx_pcrel) |
5756 | { |
5757 | switch (fixp->fx_size) |
5758 | { |
5759 | default: |
5760 | as_bad_where (fixp->fx_file, fixp->fx_line, |
5761 | _("can not do %d byte pc-relative relocation")("can not do %d byte pc-relative relocation"), |
5762 | fixp->fx_size); |
5763 | code = BFD_RELOC_32_PCREL; |
5764 | break; |
5765 | case 1: code = BFD_RELOC_8_PCREL; break; |
5766 | case 2: code = BFD_RELOC_16_PCREL; break; |
5767 | case 4: code = BFD_RELOC_32_PCREL; break; |
5768 | #ifdef BFD64 |
5769 | case 8: code = BFD_RELOC_64_PCREL; break; |
5770 | #endif |
5771 | } |
5772 | } |
5773 | else |
5774 | { |
5775 | switch (fixp->fx_size) |
5776 | { |
5777 | default: |
5778 | as_bad_where (fixp->fx_file, fixp->fx_line, |
5779 | _("can not do %d byte relocation")("can not do %d byte relocation"), |
5780 | fixp->fx_size); |
5781 | code = BFD_RELOC_32; |
5782 | break; |
5783 | case 1: code = BFD_RELOC_8; break; |
5784 | case 2: code = BFD_RELOC_16; break; |
5785 | case 4: code = BFD_RELOC_32; break; |
5786 | #ifdef BFD64 |
5787 | case 8: code = BFD_RELOC_64; break; |
5788 | #endif |
5789 | } |
5790 | } |
5791 | break; |
5792 | } |
5793 | |
5794 | if ((code == BFD_RELOC_32 |
5795 | || code == BFD_RELOC_32_PCREL |
5796 | || code == BFD_RELOC_X86_64_32S) |
5797 | && GOT_symbol |
5798 | && fixp->fx_addsy == GOT_symbol) |
5799 | { |
5800 | if (!object_64bit) |
5801 | code = BFD_RELOC_386_GOTPC; |
5802 | else |
5803 | code = BFD_RELOC_X86_64_GOTPC32; |
5804 | } |
5805 | if ((code == BFD_RELOC_64 || code == BFD_RELOC_64_PCREL) |
5806 | && GOT_symbol |
5807 | && fixp->fx_addsy == GOT_symbol) |
5808 | { |
5809 | code = BFD_RELOC_X86_64_GOTPC64; |
5810 | } |
5811 | |
5812 | rel = (arelent *) xmalloc (sizeof (arelent)); |
5813 | rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *)); |
5814 | *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy); |
5815 | |
5816 | rel->address = fixp->fx_frag->fr_address + fixp->fx_where; |
5817 | |
5818 | if (!use_rela_relocations) |
5819 | { |
5820 | /* HACK: Since i386 ELF uses Rel instead of Rela, encode the |
5821 | vtable entry to be used in the relocation's section offset. */ |
5822 | if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY) |
5823 | rel->address = fixp->fx_offset; |
5824 | |
5825 | rel->addend = 0; |
5826 | } |
5827 | /* Use the rela in 64bit mode. */ |
5828 | else |
5829 | { |
5830 | if (!fixp->fx_pcrel) |
5831 | rel->addend = fixp->fx_offset; |
5832 | else |
5833 | switch (code) |
5834 | { |
5835 | case BFD_RELOC_X86_64_PLT32: |
5836 | case BFD_RELOC_X86_64_GOT32: |
5837 | case BFD_RELOC_X86_64_GOTPCREL: |
5838 | case BFD_RELOC_X86_64_TLSGD: |
5839 | case BFD_RELOC_X86_64_TLSLD: |
5840 | case BFD_RELOC_X86_64_GOTTPOFF: |
5841 | case BFD_RELOC_X86_64_GOTPC32_TLSDESC: |
5842 | case BFD_RELOC_X86_64_TLSDESC_CALL: |
5843 | rel->addend = fixp->fx_offset - fixp->fx_size; |
5844 | break; |
5845 | default: |
5846 | rel->addend = (section->vma |
5847 | - fixp->fx_size |
5848 | + fixp->fx_addnumber |
5849 | + md_pcrel_from (fixp)); |
5850 | break; |
5851 | } |
5852 | } |
5853 | |
5854 | rel->howto = bfd_reloc_type_lookup (stdoutput, code); |
5855 | if (rel->howto == NULL((void*)0)) |
5856 | { |
5857 | as_bad_where (fixp->fx_file, fixp->fx_line, |
5858 | _("cannot represent relocation type %s")("cannot represent relocation type %s"), |
5859 | bfd_get_reloc_code_name (code)); |
5860 | /* Set howto to a garbage value so that we can keep going. */ |
5861 | rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32); |
5862 | assert (rel->howto != NULL)((void) ((rel->howto != ((void*)0)) ? 0 : (as_assert ("/usr/src/gnu/usr.bin/binutils-2.17/gas/config/tc-i386.c" , 5862, __PRETTY_FUNCTION__), 0))); |
5863 | } |
5864 | |
5865 | return rel; |
5866 | } |
5867 | |
5868 | |
5869 | /* Parse operands using Intel syntax. This implements a recursive descent |
5870 | parser based on the BNF grammar published in Appendix B of the MASM 6.1 |
5871 | Programmer's Guide. |
5872 | |
5873 | FIXME: We do not recognize the full operand grammar defined in the MASM |
5874 | documentation. In particular, all the structure/union and |
5875 | high-level macro operands are missing. |
5876 | |
5877 | Uppercase words are terminals, lower case words are non-terminals. |
5878 | Objects surrounded by double brackets '[[' ']]' are optional. Vertical |
5879 | bars '|' denote choices. Most grammar productions are implemented in |
5880 | functions called 'intel_<production>'. |
5881 | |
5882 | Initial production is 'expr'. |
5883 | |
5884 | addOp + | - |
5885 | |
5886 | alpha [a-zA-Z] |
5887 | |
5888 | binOp & | AND | \| | OR | ^ | XOR |
5889 | |
5890 | byteRegister AL | AH | BL | BH | CL | CH | DL | DH |
5891 | |
5892 | constant digits [[ radixOverride ]] |
5893 | |
5894 | dataType BYTE | WORD | DWORD | FWORD | QWORD | TBYTE | OWORD | XMMWORD |
5895 | |
5896 | digits decdigit |
5897 | | digits decdigit |
5898 | | digits hexdigit |
5899 | |
5900 | decdigit [0-9] |
5901 | |
5902 | e04 e04 addOp e05 |
5903 | | e05 |
5904 | |
5905 | e05 e05 binOp e06 |
5906 | | e06 |
5907 | |
5908 | e06 e06 mulOp e09 |
5909 | | e09 |
5910 | |
5911 | e09 OFFSET e10 |
5912 | | SHORT e10 |
5913 | | + e10 |
5914 | | - e10 |
5915 | | ~ e10 |
5916 | | NOT e10 |
5917 | | e09 PTR e10 |
5918 | | e09 : e10 |
5919 | | e10 |
5920 | |
5921 | e10 e10 [ expr ] |
5922 | | e11 |
5923 | |
5924 | e11 ( expr ) |
5925 | | [ expr ] |
5926 | | constant |
5927 | | dataType |
5928 | | id |
5929 | | $ |
5930 | | register |
5931 | |
5932 | => expr expr cmpOp e04 |
5933 | | e04 |
5934 | |
5935 | gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX |
5936 | | BP | EBP | SP | ESP | DI | EDI | SI | ESI |
5937 | |
5938 | hexdigit a | b | c | d | e | f |
5939 | | A | B | C | D | E | F |
5940 | |
5941 | id alpha |
5942 | | id alpha |
5943 | | id decdigit |
5944 | |
5945 | mulOp * | / | % | MOD | << | SHL | >> | SHR |
5946 | |
5947 | quote " | ' |
5948 | |
5949 | register specialRegister |
5950 | | gpRegister |
5951 | | byteRegister |
5952 | |
5953 | segmentRegister CS | DS | ES | FS | GS | SS |
5954 | |
5955 | specialRegister CR0 | CR2 | CR3 | CR4 |
5956 | | DR0 | DR1 | DR2 | DR3 | DR6 | DR7 |
5957 | | TR3 | TR4 | TR5 | TR6 | TR7 |
5958 | |
5959 | We simplify the grammar in obvious places (e.g., register parsing is |
5960 | done by calling parse_register) and eliminate immediate left recursion |
5961 | to implement a recursive-descent parser. |
5962 | |
5963 | expr e04 expr' |
5964 | |
5965 | expr' cmpOp e04 expr' |
5966 | | Empty |
5967 | |
5968 | e04 e05 e04' |
5969 | |
5970 | e04' addOp e05 e04' |
5971 | | Empty |
5972 | |
5973 | e05 e06 e05' |
5974 | |
5975 | e05' binOp e06 e05' |
5976 | | Empty |
5977 | |
5978 | e06 e09 e06' |
5979 | |
5980 | e06' mulOp e09 e06' |
5981 | | Empty |
5982 | |
5983 | e09 OFFSET e10 e09' |
5984 | | SHORT e10' |
5985 | | + e10' |
5986 | | - e10' |
5987 | | ~ e10' |
5988 | | NOT e10' |
5989 | | e10 e09' |
5990 | |
5991 | e09' PTR e10 e09' |
5992 | | : e10 e09' |
5993 | | Empty |
5994 | |
5995 | e10 e11 e10' |
5996 | |
5997 | e10' [ expr ] e10' |
5998 | | Empty |
5999 | |
6000 | e11 ( expr ) |
6001 | | [ expr ] |
6002 | | BYTE |
6003 | | WORD |
6004 | | DWORD |
6005 | | FWORD |
6006 | | QWORD |
6007 | | TBYTE |
6008 | | OWORD |
6009 | | XMMWORD |
6010 | | . |
6011 | | $ |
6012 | | register |
6013 | | id |
6014 | | constant */ |
6015 | |
6016 | /* Parsing structure for the intel syntax parser. Used to implement the |
6017 | semantic actions for the operand grammar. */ |
6018 | struct intel_parser_s |
6019 | { |
6020 | char *op_string; /* The string being parsed. */ |
6021 | int got_a_float; /* Whether the operand is a float. */ |
6022 | int op_modifier; /* Operand modifier. */ |
6023 | int is_mem; /* 1 if operand is memory reference. */ |
6024 | int in_offset; /* >=1 if parsing operand of offset. */ |
6025 | int in_bracket; /* >=1 if parsing operand in brackets. */ |
6026 | const reg_entry *reg; /* Last register reference found. */ |
6027 | char *disp; /* Displacement string being built. */ |
6028 | char *next_operand; /* Resume point when splitting operands. */ |
6029 | }; |
6030 | |
6031 | static struct intel_parser_s intel_parser; |
6032 | |
6033 | /* Token structure for parsing intel syntax. */ |
6034 | struct intel_token |
6035 | { |
6036 | int code; /* Token code. */ |
6037 | const reg_entry *reg; /* Register entry for register tokens. */ |
6038 | char *str; /* String representation. */ |
6039 | }; |
6040 | |
6041 | static struct intel_token cur_token, prev_token; |
6042 | |
6043 | /* Token codes for the intel parser. Since T_SHORT is already used |
6044 | by COFF, undefine it first to prevent a warning. */ |
6045 | #define T_NIL-1 -1 |
6046 | #define T_CONST1 1 |
6047 | #define T_REG2 2 |
6048 | #define T_BYTE3 3 |
6049 | #define T_WORD4 4 |
6050 | #define T_DWORD5 5 |
6051 | #define T_FWORD6 6 |
6052 | #define T_QWORD7 7 |
6053 | #define T_TBYTE8 8 |
6054 | #define T_XMMWORD9 9 |
6055 | #undef T_SHORT10 |
6056 | #define T_SHORT10 10 |
6057 | #define T_OFFSET11 11 |
6058 | #define T_PTR12 12 |
6059 | #define T_ID13 13 |
6060 | #define T_SHL14 14 |
6061 | #define T_SHR15 15 |
6062 | |
6063 | /* Prototypes for intel parser functions. */ |
6064 | static int intel_match_token PARAMS ((int code))(int code); |
6065 | static void intel_get_token PARAMS ((void))(void); |
6066 | static void intel_putback_token PARAMS ((void))(void); |
6067 | static int intel_expr PARAMS ((void))(void); |
6068 | static int intel_e04 PARAMS ((void))(void); |
6069 | static int intel_e05 PARAMS ((void))(void); |
6070 | static int intel_e06 PARAMS ((void))(void); |
6071 | static int intel_e09 PARAMS ((void))(void); |
6072 | static int intel_bracket_expr PARAMS ((void))(void); |
6073 | static int intel_e10 PARAMS ((void))(void); |
6074 | static int intel_e11 PARAMS ((void))(void); |
6075 | |
6076 | static int |
6077 | i386_intel_operand (operand_string, got_a_float) |
6078 | char *operand_string; |
6079 | int got_a_float; |
6080 | { |
6081 | int ret; |
6082 | char *p; |
6083 | |
6084 | p = intel_parser.op_string = xstrdup (operand_string); |
6085 | intel_parser.disp = (char *) xmalloc (strlen (operand_string) + 1); |
6086 | |
6087 | for (;;) |
6088 | { |
6089 | /* Initialize token holders. */ |
6090 | cur_token.code = prev_token.code = T_NIL-1; |
6091 | cur_token.reg = prev_token.reg = NULL((void*)0); |
6092 | cur_token.str = prev_token.str = NULL((void*)0); |
6093 | |
6094 | /* Initialize parser structure. */ |
6095 | intel_parser.got_a_float = got_a_float; |
6096 | intel_parser.op_modifier = 0; |
6097 | intel_parser.is_mem = 0; |
6098 | intel_parser.in_offset = 0; |
6099 | intel_parser.in_bracket = 0; |
6100 | intel_parser.reg = NULL((void*)0); |
6101 | intel_parser.disp[0] = '\0'; |
6102 | intel_parser.next_operand = NULL((void*)0); |
6103 | |
6104 | /* Read the first token and start the parser. */ |
6105 | intel_get_token (); |
6106 | ret = intel_expr (); |
6107 | |
6108 | if (!ret) |
6109 | break; |
6110 | |
6111 | if (cur_token.code != T_NIL-1) |
6112 | { |
6113 | as_bad (_("invalid operand for '%s' ('%s' unexpected)")("invalid operand for '%s' ('%s' unexpected)"), |
6114 | current_templates->start->name, cur_token.str); |
6115 | ret = 0; |
6116 | } |
6117 | /* If we found a memory reference, hand it over to i386_displacement |
6118 | to fill in the rest of the operand fields. */ |
6119 | else if (intel_parser.is_mem) |
6120 | { |
6121 | if ((i.mem_operands == 1 |
6122 | && (current_templates->start->opcode_modifier & IsString0x2000000) == 0) |
6123 | || i.mem_operands == 2) |
6124 | { |
6125 | as_bad (_("too many memory references for '%s'")("too many memory references for '%s'"), |
6126 | current_templates->start->name); |
6127 | ret = 0; |
6128 | } |
6129 | else |
6130 | { |
6131 | char *s = intel_parser.disp; |
6132 | i.mem_operands++; |
6133 | |
6134 | if (!quiet_warnings && intel_parser.is_mem < 0) |
6135 | /* See the comments in intel_bracket_expr. */ |
6136 | as_warn (_("Treating `%s' as memory reference")("Treating `%s' as memory reference"), operand_string); |
6137 | |
6138 | /* Add the displacement expression. */ |
6139 | if (*s != '\0') |
6140 | ret = i386_displacement (s, s + strlen (s)); |
6141 | if (ret) |
6142 | { |
6143 | /* Swap base and index in 16-bit memory operands like |
6144 | [si+bx]. Since i386_index_check is also used in AT&T |
6145 | mode we have to do that here. */ |
6146 | if (i.base_reg |
6147 | && i.index_reg |
6148 | && (i.base_reg->reg_type & Reg160x2) |
6149 | && (i.index_reg->reg_type & Reg160x2) |
6150 | && i.base_reg->reg_num >= 6 |
6151 | && i.index_reg->reg_num < 6) |
6152 | { |
6153 | const reg_entry *base = i.index_reg; |
6154 | |
6155 | i.index_reg = i.base_reg; |
6156 | i.base_reg = base; |
6157 | } |
6158 | ret = i386_index_check (operand_string); |
6159 | } |
6160 | } |
6161 | } |
6162 | |
6163 | /* Constant and OFFSET expressions are handled by i386_immediate. */ |
6164 | else if ((intel_parser.op_modifier & (1 << T_OFFSET11)) |
6165 | || intel_parser.reg == NULL((void*)0)) |
6166 | ret = i386_immediate (intel_parser.disp); |
6167 | |
6168 | if (intel_parser.next_operand && this_operand >= MAX_OPERANDS3 - 1) |
6169 | ret = 0; |
6170 | if (!ret || !intel_parser.next_operand) |
6171 | break; |
6172 | intel_parser.op_string = intel_parser.next_operand; |
6173 | this_operand = i.operands++; |
6174 | } |
6175 | |
6176 | free (p); |
6177 | free (intel_parser.disp); |
6178 | |
6179 | return ret; |
6180 | } |
6181 | |
6182 | #define NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg) (!!i.base_reg + !!i.index_reg) |
6183 | |
6184 | /* expr e04 expr' |
6185 | |
6186 | expr' cmpOp e04 expr' |
6187 | | Empty */ |
6188 | static int |
6189 | intel_expr () |
6190 | { |
6191 | /* XXX Implement the comparison operators. */ |
6192 | return intel_e04 (); |
6193 | } |
6194 | |
6195 | /* e04 e05 e04' |
6196 | |
6197 | e04' addOp e05 e04' |
6198 | | Empty */ |
6199 | static int |
6200 | intel_e04 () |
6201 | { |
6202 | int nregs = -1; |
6203 | |
6204 | for (;;) |
6205 | { |
6206 | if (!intel_e05()) |
6207 | return 0; |
6208 | |
6209 | if (nregs >= 0 && NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg) > nregs) |
6210 | i.base_reg = i386_regtab + REGNAM_AL1; /* al is invalid as base */ |
6211 | |
6212 | if (cur_token.code == '+') |
6213 | nregs = -1; |
6214 | else if (cur_token.code == '-') |
6215 | nregs = NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg); |
6216 | else |
6217 | return 1; |
6218 | |
6219 | strcat (intel_parser.disp, cur_token.str); |
6220 | intel_match_token (cur_token.code); |
6221 | } |
6222 | } |
6223 | |
6224 | /* e05 e06 e05' |
6225 | |
6226 | e05' binOp e06 e05' |
6227 | | Empty */ |
6228 | static int |
6229 | intel_e05 () |
6230 | { |
6231 | int nregs = ~NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg); |
6232 | |
6233 | for (;;) |
6234 | { |
6235 | if (!intel_e06()) |
6236 | return 0; |
6237 | |
6238 | if (cur_token.code == '&' || cur_token.code == '|' || cur_token.code == '^') |
6239 | { |
6240 | char str[2]; |
6241 | |
6242 | str[0] = cur_token.code; |
6243 | str[1] = 0; |
6244 | strcat (intel_parser.disp, str); |
6245 | } |
6246 | else |
6247 | break; |
6248 | |
6249 | intel_match_token (cur_token.code); |
6250 | |
6251 | if (nregs < 0) |
6252 | nregs = ~nregs; |
6253 | } |
6254 | if (nregs >= 0 && NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg) > nregs) |
6255 | i.base_reg = i386_regtab + REGNAM_AL1 + 1; /* cl is invalid as base */ |
6256 | return 1; |
6257 | } |
6258 | |
6259 | /* e06 e09 e06' |
6260 | |
6261 | e06' mulOp e09 e06' |
6262 | | Empty */ |
6263 | static int |
6264 | intel_e06 () |
6265 | { |
6266 | int nregs = ~NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg); |
6267 | |
6268 | for (;;) |
6269 | { |
6270 | if (!intel_e09()) |
6271 | return 0; |
6272 | |
6273 | if (cur_token.code == '*' || cur_token.code == '/' || cur_token.code == '%') |
6274 | { |
6275 | char str[2]; |
6276 | |
6277 | str[0] = cur_token.code; |
6278 | str[1] = 0; |
6279 | strcat (intel_parser.disp, str); |
6280 | } |
6281 | else if (cur_token.code == T_SHL14) |
6282 | strcat (intel_parser.disp, "<<"); |
6283 | else if (cur_token.code == T_SHR15) |
6284 | strcat (intel_parser.disp, ">>"); |
6285 | else |
6286 | break; |
6287 | |
6288 | intel_match_token (cur_token.code); |
6289 | |
6290 | if (nregs < 0) |
6291 | nregs = ~nregs; |
6292 | } |
6293 | if (nregs >= 0 && NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg) > nregs) |
6294 | i.base_reg = i386_regtab + REGNAM_AL1 + 2; /* dl is invalid as base */ |
6295 | return 1; |
6296 | } |
6297 | |
6298 | /* e09 OFFSET e09 |
6299 | | SHORT e09 |
6300 | | + e09 |
6301 | | - e09 |
6302 | | ~ e09 |
6303 | | NOT e09 |
6304 | | e10 e09' |
6305 | |
6306 | e09' PTR e10 e09' |
6307 | | : e10 e09' |
6308 | | Empty */ |
6309 | static int |
6310 | intel_e09 () |
6311 | { |
6312 | int nregs = ~NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg); |
6313 | int in_offset = 0; |
6314 | |
6315 | for (;;) |
6316 | { |
6317 | /* Don't consume constants here. */ |
6318 | if (cur_token.code == '+' || cur_token.code == '-') |
6319 | { |
6320 | /* Need to look one token ahead - if the next token |
6321 | is a constant, the current token is its sign. */ |
6322 | int next_code; |
6323 | |
6324 | intel_match_token (cur_token.code); |
6325 | next_code = cur_token.code; |
6326 | intel_putback_token (); |
6327 | if (next_code == T_CONST1) |
6328 | break; |
6329 | } |
6330 | |
6331 | /* e09 OFFSET e09 */ |
6332 | if (cur_token.code == T_OFFSET11) |
6333 | { |
6334 | if (!in_offset++) |
6335 | ++intel_parser.in_offset; |
6336 | } |
6337 | |
6338 | /* e09 SHORT e09 */ |
6339 | else if (cur_token.code == T_SHORT10) |
6340 | intel_parser.op_modifier |= 1 << T_SHORT10; |
6341 | |
6342 | /* e09 + e09 */ |
6343 | else if (cur_token.code == '+') |
6344 | strcat (intel_parser.disp, "+"); |
6345 | |
6346 | /* e09 - e09 |
6347 | | ~ e09 |
6348 | | NOT e09 */ |
6349 | else if (cur_token.code == '-' || cur_token.code == '~') |
6350 | { |
6351 | char str[2]; |
6352 | |
6353 | if (nregs < 0) |
6354 | nregs = ~nregs; |
6355 | str[0] = cur_token.code; |
6356 | str[1] = 0; |
6357 | strcat (intel_parser.disp, str); |
6358 | } |
6359 | |
6360 | /* e09 e10 e09' */ |
6361 | else |
6362 | break; |
6363 | |
6364 | intel_match_token (cur_token.code); |
6365 | } |
6366 | |
6367 | for (;;) |
6368 | { |
6369 | if (!intel_e10 ()) |
6370 | return 0; |
6371 | |
6372 | /* e09' PTR e10 e09' */ |
6373 | if (cur_token.code == T_PTR12) |
6374 | { |
6375 | char suffix; |
6376 | |
6377 | if (prev_token.code == T_BYTE3) |
6378 | suffix = BYTE_MNEM_SUFFIX'b'; |
6379 | |
6380 | else if (prev_token.code == T_WORD4) |
6381 | { |
6382 | if (current_templates->start->name[0] == 'l' |
6383 | && current_templates->start->name[2] == 's' |
6384 | && current_templates->start->name[3] == 0) |
6385 | suffix = BYTE_MNEM_SUFFIX'b'; /* so it will cause an error */ |
6386 | else if (intel_parser.got_a_float == 2) /* "fi..." */ |
6387 | suffix = SHORT_MNEM_SUFFIX's'; |
6388 | else |
6389 | suffix = WORD_MNEM_SUFFIX'w'; |
6390 | } |
6391 | |
6392 | else if (prev_token.code == T_DWORD5) |
6393 | { |
6394 | if (current_templates->start->name[0] == 'l' |
6395 | && current_templates->start->name[2] == 's' |
6396 | && current_templates->start->name[3] == 0) |
6397 | suffix = WORD_MNEM_SUFFIX'w'; |
6398 | else if (flag_code == CODE_16BIT |
6399 | && (current_templates->start->opcode_modifier |
6400 | & (Jump0x40 | JumpDword0x80))) |
6401 | suffix = LONG_DOUBLE_MNEM_SUFFIX'x'; |
6402 | else if (intel_parser.got_a_float == 1) /* "f..." */ |
6403 | suffix = SHORT_MNEM_SUFFIX's'; |
6404 | else |
6405 | suffix = LONG_MNEM_SUFFIX'l'; |
6406 | } |
6407 | |
6408 | else if (prev_token.code == T_FWORD6) |
6409 | { |
6410 | if (current_templates->start->name[0] == 'l' |
6411 | && current_templates->start->name[2] == 's' |
6412 | && current_templates->start->name[3] == 0) |
6413 | suffix = LONG_MNEM_SUFFIX'l'; |
6414 | else if (!intel_parser.got_a_float) |
6415 | { |
6416 | if (flag_code == CODE_16BIT) |
6417 | add_prefix (DATA_PREFIX_OPCODE0x66); |
6418 | suffix = LONG_DOUBLE_MNEM_SUFFIX'x'; |
6419 | } |
6420 | else |
6421 | suffix = BYTE_MNEM_SUFFIX'b'; /* so it will cause an error */ |
6422 | } |
6423 | |
6424 | else if (prev_token.code == T_QWORD7) |
6425 | { |
6426 | if (intel_parser.got_a_float == 1) /* "f..." */ |
6427 | suffix = LONG_MNEM_SUFFIX'l'; |
6428 | else |
6429 | suffix = QWORD_MNEM_SUFFIX'q'; |
6430 | } |
6431 | |
6432 | else if (prev_token.code == T_TBYTE8) |
6433 | { |
6434 | if (intel_parser.got_a_float == 1) |
6435 | suffix = LONG_DOUBLE_MNEM_SUFFIX'x'; |
6436 | else |
6437 | suffix = BYTE_MNEM_SUFFIX'b'; /* so it will cause an error */ |
6438 | } |
6439 | |
6440 | else if (prev_token.code == T_XMMWORD9) |
6441 | { |
6442 | /* XXX ignored for now, but accepted since gcc uses it */ |
6443 | suffix = 0; |
6444 | } |
6445 | |
6446 | else |
6447 | { |
6448 | as_bad (_("Unknown operand modifier `%s'")("Unknown operand modifier `%s'"), prev_token.str); |
6449 | return 0; |
6450 | } |
6451 | |
6452 | /* Operands for jump/call using 'ptr' notation denote absolute |
6453 | addresses. */ |
6454 | if (current_templates->start->opcode_modifier & (Jump0x40 | JumpDword0x80)) |
6455 | i.types[this_operand] |= JumpAbsolute0x8000000; |
6456 | |
6457 | if (current_templates->start->base_opcode == 0x8d /* lea */) |
6458 | ; |
6459 | else if (!i.suffix) |
6460 | i.suffix = suffix; |
6461 | else if (i.suffix != suffix) |
6462 | { |
6463 | as_bad (_("Conflicting operand modifiers")("Conflicting operand modifiers")); |
6464 | return 0; |
6465 | } |
6466 | |
6467 | } |
6468 | |
6469 | /* e09' : e10 e09' */ |
6470 | else if (cur_token.code == ':') |
6471 | { |
6472 | if (prev_token.code != T_REG2) |
6473 | { |
6474 | /* While {call,jmp} SSSS:OOOO is MASM syntax only when SSSS is a |
6475 | segment/group identifier (which we don't have), using comma |
6476 | as the operand separator there is even less consistent, since |
6477 | there all branches only have a single operand. */ |
6478 | if (this_operand != 0 |
6479 | || intel_parser.in_offset |
6480 | || intel_parser.in_bracket |
6481 | || (!(current_templates->start->opcode_modifier |
6482 | & (Jump0x40|JumpDword0x80|JumpInterSegment0x200)) |
6483 | && !(current_templates->start->operand_types[0] |
6484 | & JumpAbsolute0x8000000))) |
6485 | return intel_match_token (T_NIL-1); |
6486 | /* Remember the start of the 2nd operand and terminate 1st |
6487 | operand here. |
6488 | XXX This isn't right, yet (when SSSS:OOOO is right operand of |
6489 | another expression), but it gets at least the simplest case |
6490 | (a plain number or symbol on the left side) right. */ |
6491 | intel_parser.next_operand = intel_parser.op_string; |
6492 | *--intel_parser.op_string = '\0'; |
6493 | return intel_match_token (':'); |
6494 | } |
6495 | } |
6496 | |
6497 | /* e09' Empty */ |
6498 | else |
6499 | break; |
6500 | |
6501 | intel_match_token (cur_token.code); |
6502 | |
6503 | } |
6504 | |
6505 | if (in_offset) |
6506 | { |
6507 | --intel_parser.in_offset; |
6508 | if (nregs < 0) |
6509 | nregs = ~nregs; |
6510 | if (NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg) > nregs) |
6511 | { |
6512 | as_bad (_("Invalid operand to `OFFSET'")("Invalid operand to `OFFSET'")); |
6513 | return 0; |
6514 | } |
6515 | intel_parser.op_modifier |= 1 << T_OFFSET11; |
6516 | } |
6517 | |
6518 | if (nregs >= 0 && NUM_ADDRESS_REGS(!!i.base_reg + !!i.index_reg) > nregs) |
6519 | i.base_reg = i386_regtab + REGNAM_AL1 + 3; /* bl is invalid as base */ |
6520 | return 1; |
6521 | } |
6522 | |
6523 | static int |
6524 | intel_bracket_expr () |
6525 | { |
6526 | int was_offset = intel_parser.op_modifier & (1 << T_OFFSET11); |
6527 | const char *start = intel_parser.op_string; |
6528 | int len; |
6529 | |
6530 | if (i.op[this_operand].regs) |
6531 | return intel_match_token (T_NIL-1); |
6532 | |
6533 | intel_match_token ('['); |
6534 | |
6535 | /* Mark as a memory operand only if it's not already known to be an |
6536 | offset expression. If it's an offset expression, we need to keep |
6537 | the brace in. */ |
6538 | if (!intel_parser.in_offset) |
6539 | { |
6540 | ++intel_parser.in_bracket; |
6541 | |
6542 | /* Operands for jump/call inside brackets denote absolute addresses. */ |
6543 | if (current_templates->start->opcode_modifier & (Jump0x40 | JumpDword0x80)) |
6544 | i.types[this_operand] |= JumpAbsolute0x8000000; |
6545 | |
6546 | /* Unfortunately gas always diverged from MASM in a respect that can't |
6547 | be easily fixed without risking to break code sequences likely to be |
6548 | encountered (the testsuite even check for this): MASM doesn't consider |
6549 | an expression inside brackets unconditionally as a memory reference. |
6550 | When that is e.g. a constant, an offset expression, or the sum of the |
6551 | two, this is still taken as a constant load. gas, however, always |
6552 | treated these as memory references. As a compromise, we'll try to make |
6553 | offset expressions inside brackets work the MASM way (since that's |
6554 | less likely to be found in real world code), but make constants alone |
6555 | continue to work the traditional gas way. In either case, issue a |
6556 | warning. */ |
6557 | intel_parser.op_modifier &= ~was_offset; |
6558 | } |
6559 | else |
6560 | strcat (intel_parser.disp, "["); |
6561 | |
6562 | /* Add a '+' to the displacement string if necessary. */ |
6563 | if (*intel_parser.disp != '\0' |
6564 | && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+') |
6565 | strcat (intel_parser.disp, "+"); |
6566 | |
6567 | if (intel_expr () |
6568 | && (len = intel_parser.op_string - start - 1, |
6569 | intel_match_token (']'))) |
6570 | { |
6571 | /* Preserve brackets when the operand is an offset expression. */ |
6572 | if (intel_parser.in_offset) |
6573 | strcat (intel_parser.disp, "]"); |
6574 | else |
6575 | { |
6576 | --intel_parser.in_bracket; |
6577 | if (i.base_reg || i.index_reg) |
6578 | intel_parser.is_mem = 1; |
6579 | if (!intel_parser.is_mem) |
6580 | { |
6581 | if (!(intel_parser.op_modifier & (1 << T_OFFSET11))) |
6582 | /* Defer the warning until all of the operand was parsed. */ |
6583 | intel_parser.is_mem = -1; |
6584 | else if (!quiet_warnings) |
6585 | as_warn (_("`[%.*s]' taken to mean just `%.*s'")("`[%.*s]' taken to mean just `%.*s'"), len, start, len, start); |
6586 | } |
6587 | } |
6588 | intel_parser.op_modifier |= was_offset; |
6589 | |
6590 | return 1; |
6591 | } |
6592 | return 0; |
6593 | } |
6594 | |
6595 | /* e10 e11 e10' |
6596 | |
6597 | e10' [ expr ] e10' |
6598 | | Empty */ |
6599 | static int |
6600 | intel_e10 () |
6601 | { |
6602 | if (!intel_e11 ()) |
6603 | return 0; |
6604 | |
6605 | while (cur_token.code == '[') |
6606 | { |
6607 | if (!intel_bracket_expr ()) |
6608 | return 0; |
6609 | } |
6610 | |
6611 | return 1; |
6612 | } |
6613 | |
6614 | /* e11 ( expr ) |
6615 | | [ expr ] |
6616 | | BYTE |
6617 | | WORD |
6618 | | DWORD |
6619 | | FWORD |
6620 | | QWORD |
6621 | | TBYTE |
6622 | | OWORD |
6623 | | XMMWORD |
6624 | | $ |
6625 | | . |
6626 | | register |
6627 | | id |
6628 | | constant */ |
6629 | static int |
6630 | intel_e11 () |
6631 | { |
6632 | switch (cur_token.code) |
6633 | { |
6634 | /* e11 ( expr ) */ |
6635 | case '(': |
6636 | intel_match_token ('('); |
6637 | strcat (intel_parser.disp, "("); |
6638 | |
6639 | if (intel_expr () && intel_match_token (')')) |
6640 | { |
6641 | strcat (intel_parser.disp, ")"); |
6642 | return 1; |
6643 | } |
6644 | return 0; |
6645 | |
6646 | /* e11 [ expr ] */ |
6647 | case '[': |
6648 | return intel_bracket_expr (); |
6649 | |
6650 | /* e11 $ |
6651 | | . */ |
6652 | case '.': |
6653 | strcat (intel_parser.disp, cur_token.str); |
6654 | intel_match_token (cur_token.code); |
6655 | |
6656 | /* Mark as a memory operand only if it's not already known to be an |
6657 | offset expression. */ |
6658 | if (!intel_parser.in_offset) |
6659 | intel_parser.is_mem = 1; |
6660 | |
6661 | return 1; |
6662 | |
6663 | /* e11 register */ |
6664 | case T_REG2: |
6665 | { |
6666 | const reg_entry *reg = intel_parser.reg = cur_token.reg; |
6667 | |
6668 | intel_match_token (T_REG2); |
6669 | |
6670 | /* Check for segment change. */ |
6671 | if (cur_token.code == ':') |
6672 | { |
6673 | if (!(reg->reg_type & (SReg20x1000000 | SReg30x2000000))) |
6674 | { |
6675 | as_bad (_("`%s' is not a valid segment register")("`%s' is not a valid segment register"), reg->reg_name); |
6676 | return 0; |
6677 | } |
6678 | else if (i.seg[i.mem_operands]) |
6679 | as_warn (_("Extra segment override ignored")("Extra segment override ignored")); |
6680 | else |
6681 | { |
6682 | if (!intel_parser.in_offset) |
6683 | intel_parser.is_mem = 1; |
6684 | switch (reg->reg_num) |
6685 | { |
6686 | case 0: |
6687 | i.seg[i.mem_operands] = &es; |
6688 | break; |
6689 | case 1: |
6690 | i.seg[i.mem_operands] = &cs; |
6691 | break; |
6692 | case 2: |
6693 | i.seg[i.mem_operands] = &ss; |
6694 | break; |
6695 | case 3: |
6696 | i.seg[i.mem_operands] = &ds; |
6697 | break; |
6698 | case 4: |
6699 | i.seg[i.mem_operands] = &fs; |
6700 | break; |
6701 | case 5: |
6702 | i.seg[i.mem_operands] = &gs; |
6703 | break; |
6704 | } |
6705 | } |
6706 | } |
6707 | |
6708 | /* Not a segment register. Check for register scaling. */ |
6709 | else if (cur_token.code == '*') |
6710 | { |
6711 | if (!intel_parser.in_bracket) |
6712 | { |
6713 | as_bad (_("Register scaling only allowed in memory operands")("Register scaling only allowed in memory operands")); |
6714 | return 0; |
6715 | } |
6716 | |
6717 | if (reg->reg_type & Reg160x2) /* Disallow things like [si*1]. */ |
6718 | reg = i386_regtab + REGNAM_AX25 + 4; /* sp is invalid as index */ |
6719 | else if (i.index_reg) |
6720 | reg = i386_regtab + REGNAM_EAX41 + 4; /* esp is invalid as index */ |
6721 | |
6722 | /* What follows must be a valid scale. */ |
6723 | intel_match_token ('*'); |
6724 | i.index_reg = reg; |
6725 | i.types[this_operand] |= BaseIndex0x800; |
6726 | |
6727 | /* Set the scale after setting the register (otherwise, |
6728 | i386_scale will complain) */ |
6729 | if (cur_token.code == '+' || cur_token.code == '-') |
6730 | { |
6731 | char *str, sign = cur_token.code; |
6732 | intel_match_token (cur_token.code); |
6733 | if (cur_token.code != T_CONST1) |
6734 | { |
6735 | as_bad (_("Syntax error: Expecting a constant, got `%s'")("Syntax error: Expecting a constant, got `%s'"), |
6736 | cur_token.str); |
6737 | return 0; |
6738 | } |
6739 | str = (char *) xmalloc (strlen (cur_token.str) + 2); |
6740 | strcpy (str + 1, cur_token.str); |
6741 | *str = sign; |
6742 | if (!i386_scale (str)) |
6743 | return 0; |
6744 | free (str); |
6745 | } |
6746 | else if (!i386_scale (cur_token.str)) |
6747 | return 0; |
6748 | intel_match_token (cur_token.code); |
6749 | } |
6750 | |
6751 | /* No scaling. If this is a memory operand, the register is either a |
6752 | base register (first occurrence) or an index register (second |
6753 | occurrence). */ |
6754 | else if (intel_parser.in_bracket) |
6755 | { |
6756 | |
6757 | if (!i.base_reg) |
6758 | i.base_reg = reg; |
6759 | else if (!i.index_reg) |
6760 | i.index_reg = reg; |
6761 | else |
6762 | { |
6763 | as_bad (_("Too many register references in memory operand")("Too many register references in memory operand")); |
6764 | return 0; |
6765 | } |
6766 | |
6767 | i.types[this_operand] |= BaseIndex0x800; |
6768 | } |
6769 | |
6770 | /* It's neither base nor index. */ |
6771 | else if (!intel_parser.in_offset && !intel_parser.is_mem) |
6772 | { |
6773 | i.types[this_operand] |= reg->reg_type & ~BaseIndex0x800; |
6774 | i.op[this_operand].regs = reg; |
6775 | i.reg_operands++; |
6776 | } |
6777 | else |
6778 | { |
6779 | as_bad (_("Invalid use of register")("Invalid use of register")); |
6780 | return 0; |
6781 | } |
6782 | |
6783 | /* Since registers are not part of the displacement string (except |
6784 | when we're parsing offset operands), we may need to remove any |
6785 | preceding '+' from the displacement string. */ |
6786 | if (*intel_parser.disp != '\0' |
6787 | && !intel_parser.in_offset) |
6788 | { |
6789 | char *s = intel_parser.disp; |
6790 | s += strlen (s) - 1; |
6791 | if (*s == '+') |
6792 | *s = '\0'; |
6793 | } |
6794 | |
6795 | return 1; |
6796 | } |
6797 | |
6798 | /* e11 BYTE |
6799 | | WORD |
6800 | | DWORD |
6801 | | FWORD |
6802 | | QWORD |
6803 | | TBYTE |
6804 | | OWORD |
6805 | | XMMWORD */ |
6806 | case T_BYTE3: |
6807 | case T_WORD4: |
6808 | case T_DWORD5: |
6809 | case T_FWORD6: |
6810 | case T_QWORD7: |
6811 | case T_TBYTE8: |
6812 | case T_XMMWORD9: |
6813 | intel_match_token (cur_token.code); |
6814 | |
6815 | if (cur_token.code == T_PTR12) |
6816 | return 1; |
6817 | |
6818 | /* It must have been an identifier. */ |
6819 | intel_putback_token (); |
6820 | cur_token.code = T_ID13; |
6821 | /* FALLTHRU */ |
6822 | |
6823 | /* e11 id |
6824 | | constant */ |
6825 | case T_ID13: |
6826 | if (!intel_parser.in_offset && intel_parser.is_mem <= 0) |
6827 | { |
6828 | symbolS *symbolP; |
6829 | |
6830 | /* The identifier represents a memory reference only if it's not |
6831 | preceded by an offset modifier and if it's not an equate. */ |
6832 | symbolP = symbol_find(cur_token.str); |
6833 | if (!symbolP || S_GET_SEGMENT(symbolP) != absolute_section((asection *) &bfd_abs_section)) |
6834 | intel_parser.is_mem = 1; |
6835 | } |
6836 | /* FALLTHRU */ |
6837 | |
6838 | case T_CONST1: |
6839 | case '-': |
6840 | case '+': |
6841 | { |
6842 | char *save_str, sign = 0; |
6843 | |
6844 | /* Allow constants that start with `+' or `-'. */ |
6845 | if (cur_token.code == '-' || cur_token.code == '+') |
6846 | { |
6847 | sign = cur_token.code; |
6848 | intel_match_token (cur_token.code); |
6849 | if (cur_token.code != T_CONST1) |
6850 | { |
6851 | as_bad (_("Syntax error: Expecting a constant, got `%s'")("Syntax error: Expecting a constant, got `%s'"), |
6852 | cur_token.str); |
6853 | return 0; |
6854 | } |
6855 | } |
6856 | |
6857 | save_str = (char *) xmalloc (strlen (cur_token.str) + 2); |
6858 | strcpy (save_str + !!sign, cur_token.str); |
6859 | if (sign) |
6860 | *save_str = sign; |
6861 | |
6862 | /* Get the next token to check for register scaling. */ |
6863 | intel_match_token (cur_token.code); |
6864 | |
6865 | /* Check if this constant is a scaling factor for an index register. */ |
6866 | if (cur_token.code == '*') |
6867 | { |
6868 | if (intel_match_token ('*') && cur_token.code == T_REG2) |
6869 | { |
6870 | const reg_entry *reg = cur_token.reg; |
6871 | |
6872 | if (!intel_parser.in_bracket) |
6873 | { |
6874 | as_bad (_("Register scaling only allowed in memory operands")("Register scaling only allowed in memory operands")); |
6875 | return 0; |
6876 | } |
6877 | |
6878 | if (reg->reg_type & Reg160x2) /* Disallow things like [1*si]. */ |
6879 | reg = i386_regtab + REGNAM_AX25 + 4; /* sp is invalid as index */ |
6880 | else if (i.index_reg) |
6881 | reg = i386_regtab + REGNAM_EAX41 + 4; /* esp is invalid as index */ |
6882 | |
6883 | /* The constant is followed by `* reg', so it must be |
6884 | a valid scale. */ |
6885 | i.index_reg = reg; |
6886 | i.types[this_operand] |= BaseIndex0x800; |
6887 | |
6888 | /* Set the scale after setting the register (otherwise, |
6889 | i386_scale will complain) */ |
6890 | if (!i386_scale (save_str)) |
6891 | return 0; |
6892 | intel_match_token (T_REG2); |
6893 | |
6894 | /* Since registers are not part of the displacement |
6895 | string, we may need to remove any preceding '+' from |
6896 | the displacement string. */ |
6897 | if (*intel_parser.disp != '\0') |
6898 | { |
6899 | char *s = intel_parser.disp; |
6900 | s += strlen (s) - 1; |
6901 | if (*s == '+') |
6902 | *s = '\0'; |
6903 | } |
6904 | |
6905 | free (save_str); |
6906 | |
6907 | return 1; |
6908 | } |
6909 | |
6910 | /* The constant was not used for register scaling. Since we have |
6911 | already consumed the token following `*' we now need to put it |
6912 | back in the stream. */ |
6913 | intel_putback_token (); |
6914 | } |
6915 | |
6916 | /* Add the constant to the displacement string. */ |
6917 | strcat (intel_parser.disp, save_str); |
6918 | free (save_str); |
6919 | |
6920 | return 1; |
6921 | } |
6922 | } |
6923 | |
6924 | as_bad (_("Unrecognized token '%s'")("Unrecognized token '%s'"), cur_token.str); |
6925 | return 0; |
6926 | } |
6927 | |
6928 | /* Match the given token against cur_token. If they match, read the next |
6929 | token from the operand string. */ |
6930 | static int |
6931 | intel_match_token (code) |
6932 | int code; |
6933 | { |
6934 | if (cur_token.code == code) |
6935 | { |
6936 | intel_get_token (); |
6937 | return 1; |
6938 | } |
6939 | else |
6940 | { |
6941 | as_bad (_("Unexpected token `%s'")("Unexpected token `%s'"), cur_token.str); |
6942 | return 0; |
6943 | } |
6944 | } |
6945 | |
6946 | /* Read a new token from intel_parser.op_string and store it in cur_token. */ |
6947 | static void |
6948 | intel_get_token () |
6949 | { |
6950 | char *end_op; |
6951 | const reg_entry *reg; |
6952 | struct intel_token new_token; |
6953 | |
6954 | new_token.code = T_NIL-1; |
6955 | new_token.reg = NULL((void*)0); |
6956 | new_token.str = NULL((void*)0); |
6957 | |
6958 | /* Free the memory allocated to the previous token and move |
6959 | cur_token to prev_token. */ |
6960 | if (prev_token.str) |
6961 | free (prev_token.str); |
6962 | |
6963 | prev_token = cur_token; |
6964 | |
6965 | /* Skip whitespace. */ |
6966 | while (is_space_char (*intel_parser.op_string)((*intel_parser.op_string) == ' ')) |
6967 | intel_parser.op_string++; |
6968 | |
6969 | /* Return an empty token if we find nothing else on the line. */ |
6970 | if (*intel_parser.op_string == '\0') |
6971 | { |
6972 | cur_token = new_token; |
6973 | return; |
6974 | } |
6975 | |
6976 | /* The new token cannot be larger than the remainder of the operand |
6977 | string. */ |
6978 | new_token.str = (char *) xmalloc (strlen (intel_parser.op_string) + 1); |
6979 | new_token.str[0] = '\0'; |
6980 | |
6981 | if (strchr ("0123456789", *intel_parser.op_string)) |
6982 | { |
6983 | char *p = new_token.str; |
6984 | char *q = intel_parser.op_string; |
6985 | new_token.code = T_CONST1; |
6986 | |
6987 | /* Allow any kind of identifier char to encompass floating point and |
6988 | hexadecimal numbers. */ |
6989 | while (is_identifier_char (*q)(identifier_chars[(unsigned char) *q])) |
6990 | *p++ = *q++; |
6991 | *p = '\0'; |
6992 | |
6993 | /* Recognize special symbol names [0-9][bf]. */ |
6994 | if (strlen (intel_parser.op_string) == 2 |
6995 | && (intel_parser.op_string[1] == 'b' |
6996 | || intel_parser.op_string[1] == 'f')) |
6997 | new_token.code = T_ID13; |
6998 | } |
6999 | |
7000 | else if ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL((void*)0)) |
7001 | { |
7002 | size_t len = end_op - intel_parser.op_string; |
7003 | |
7004 | new_token.code = T_REG2; |
7005 | new_token.reg = reg; |
7006 | |
7007 | memcpy (new_token.str, intel_parser.op_string, len); |
7008 | new_token.str[len] = '\0'; |
7009 | } |
7010 | |
7011 | else if (is_identifier_char (*intel_parser.op_string)(identifier_chars[(unsigned char) *intel_parser.op_string])) |
7012 | { |
7013 | char *p = new_token.str; |
7014 | char *q = intel_parser.op_string; |
7015 | |
7016 | /* A '.' or '$' followed by an identifier char is an identifier. |
7017 | Otherwise, it's operator '.' followed by an expression. */ |
7018 | if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1))(identifier_chars[(unsigned char) *(q + 1)])) |
7019 | { |
7020 | new_token.code = '.'; |
7021 | new_token.str[0] = '.'; |
7022 | new_token.str[1] = '\0'; |
7023 | } |
7024 | else |
7025 | { |
7026 | while (is_identifier_char (*q)(identifier_chars[(unsigned char) *q]) || *q == '@') |
7027 | *p++ = *q++; |
7028 | *p = '\0'; |
7029 | |
7030 | if (strcasecmp (new_token.str, "NOT") == 0) |
7031 | new_token.code = '~'; |
7032 | |
7033 | else if (strcasecmp (new_token.str, "MOD") == 0) |
7034 | new_token.code = '%'; |
7035 | |
7036 | else if (strcasecmp (new_token.str, "AND") == 0) |
7037 | new_token.code = '&'; |
7038 | |
7039 | else if (strcasecmp (new_token.str, "OR") == 0) |
7040 | new_token.code = '|'; |
7041 | |
7042 | else if (strcasecmp (new_token.str, "XOR") == 0) |
7043 | new_token.code = '^'; |
7044 | |
7045 | else if (strcasecmp (new_token.str, "SHL") == 0) |
7046 | new_token.code = T_SHL14; |
7047 | |
7048 | else if (strcasecmp (new_token.str, "SHR") == 0) |
7049 | new_token.code = T_SHR15; |
7050 | |
7051 | else if (strcasecmp (new_token.str, "BYTE") == 0) |
7052 | new_token.code = T_BYTE3; |
7053 | |
7054 | else if (strcasecmp (new_token.str, "WORD") == 0) |
7055 | new_token.code = T_WORD4; |
7056 | |
7057 | else if (strcasecmp (new_token.str, "DWORD") == 0) |
7058 | new_token.code = T_DWORD5; |
7059 | |
7060 | else if (strcasecmp (new_token.str, "FWORD") == 0) |
7061 | new_token.code = T_FWORD6; |
7062 | |
7063 | else if (strcasecmp (new_token.str, "QWORD") == 0) |
7064 | new_token.code = T_QWORD7; |
7065 | |
7066 | else if (strcasecmp (new_token.str, "TBYTE") == 0 |
7067 | /* XXX remove (gcc still uses it) */ |
7068 | || strcasecmp (new_token.str, "XWORD") == 0) |
7069 | new_token.code = T_TBYTE8; |
7070 | |
7071 | else if (strcasecmp (new_token.str, "XMMWORD") == 0 |
7072 | || strcasecmp (new_token.str, "OWORD") == 0) |
7073 | new_token.code = T_XMMWORD9; |
7074 | |
7075 | else if (strcasecmp (new_token.str, "PTR") == 0) |
7076 | new_token.code = T_PTR12; |
7077 | |
7078 | else if (strcasecmp (new_token.str, "SHORT") == 0) |
7079 | new_token.code = T_SHORT10; |
7080 | |
7081 | else if (strcasecmp (new_token.str, "OFFSET") == 0) |
7082 | { |
7083 | new_token.code = T_OFFSET11; |
7084 | |
7085 | /* ??? This is not mentioned in the MASM grammar but gcc |
7086 | makes use of it with -mintel-syntax. OFFSET may be |
7087 | followed by FLAT: */ |
7088 | if (strncasecmp (q, " FLAT:", 6) == 0) |
7089 | strcat (new_token.str, " FLAT:"); |
7090 | } |
7091 | |
7092 | /* ??? This is not mentioned in the MASM grammar. */ |
7093 | else if (strcasecmp (new_token.str, "FLAT") == 0) |
7094 | { |
7095 | new_token.code = T_OFFSET11; |
7096 | if (*q == ':') |
7097 | strcat (new_token.str, ":"); |
7098 | else |
7099 | as_bad (_("`:' expected")("`:' expected")); |
7100 | } |
7101 | |
7102 | else |
7103 | new_token.code = T_ID13; |
7104 | } |
7105 | } |
7106 | |
7107 | else if (strchr ("+-/*%|&^:[]()~", *intel_parser.op_string)) |
7108 | { |
7109 | new_token.code = *intel_parser.op_string; |
7110 | new_token.str[0] = *intel_parser.op_string; |
7111 | new_token.str[1] = '\0'; |
7112 | } |
7113 | |
7114 | else if (strchr ("<>", *intel_parser.op_string) |
7115 | && *intel_parser.op_string == *(intel_parser.op_string + 1)) |
7116 | { |
7117 | new_token.code = *intel_parser.op_string == '<' ? T_SHL14 : T_SHR15; |
7118 | new_token.str[0] = *intel_parser.op_string; |
7119 | new_token.str[1] = *intel_parser.op_string; |
7120 | new_token.str[2] = '\0'; |
7121 | } |
7122 | |
7123 | else |
7124 | as_bad (_("Unrecognized token `%s'")("Unrecognized token `%s'"), intel_parser.op_string); |
7125 | |
7126 | intel_parser.op_string += strlen (new_token.str); |
7127 | cur_token = new_token; |
7128 | } |
7129 | |
7130 | /* Put cur_token back into the token stream and make cur_token point to |
7131 | prev_token. */ |
7132 | static void |
7133 | intel_putback_token () |
7134 | { |
7135 | if (cur_token.code != T_NIL-1) |
7136 | { |
7137 | intel_parser.op_string -= strlen (cur_token.str); |
7138 | free (cur_token.str); |
7139 | } |
7140 | cur_token = prev_token; |
7141 | |
7142 | /* Forget prev_token. */ |
7143 | prev_token.code = T_NIL-1; |
7144 | prev_token.reg = NULL((void*)0); |
7145 | prev_token.str = NULL((void*)0); |
7146 | } |
7147 | |
7148 | int |
7149 | tc_x86_regname_to_dw2regnum (const char *regname) |
7150 | { |
7151 | unsigned int regnum; |
7152 | unsigned int regnames_count; |
7153 | static const char *const regnames_32[] = |
7154 | { |
7155 | "eax", "ecx", "edx", "ebx", |
7156 | "esp", "ebp", "esi", "edi", |
7157 | "eip", "eflags", NULL((void*)0), |
7158 | "st0", "st1", "st2", "st3", |
7159 | "st4", "st5", "st6", "st7", |
7160 | NULL((void*)0), NULL((void*)0), |
7161 | "xmm0", "xmm1", "xmm2", "xmm3", |
7162 | "xmm4", "xmm5", "xmm6", "xmm7", |
7163 | "mm0", "mm1", "mm2", "mm3", |
7164 | "mm4", "mm5", "mm6", "mm7", |
7165 | "fcw", "fsw", "mxcsr", |
7166 | "es", "cs", "ss", "ds", "fs", "gs", NULL((void*)0), NULL((void*)0), |
7167 | "tr", "ldtr" |
7168 | }; |
7169 | static const char *const regnames_64[] = |
7170 | { |
7171 | "rax", "rdx", "rcx", "rbx", |
7172 | "rsi", "rdi", "rbp", "rsp", |
7173 | "r8", "r9", "r10", "r11", |
7174 | "r12", "r13", "r14", "r15", |
7175 | "rip", |
7176 | "xmm0", "xmm1", "xmm2", "xmm3", |
7177 | "xmm4", "xmm5", "xmm6", "xmm7", |
7178 | "xmm8", "xmm9", "xmm10", "xmm11", |
7179 | "xmm12", "xmm13", "xmm14", "xmm15", |
7180 | "st0", "st1", "st2", "st3", |
7181 | "st4", "st5", "st6", "st7", |
7182 | "mm0", "mm1", "mm2", "mm3", |
7183 | "mm4", "mm5", "mm6", "mm7", |
7184 | "rflags", |
7185 | "es", "cs", "ss", "ds", "fs", "gs", NULL((void*)0), NULL((void*)0), |
7186 | "fs.base", "gs.base", NULL((void*)0), NULL((void*)0), |
7187 | "tr", "ldtr", |
7188 | "mxcsr", "fcw", "fsw" |
7189 | }; |
7190 | const char *const *regnames; |
7191 | |
7192 | if (flag_code == CODE_64BIT) |
7193 | { |
7194 | regnames = regnames_64; |
7195 | regnames_count = ARRAY_SIZE (regnames_64)(sizeof (regnames_64) / sizeof ((regnames_64)[0])); |
7196 | } |
7197 | else |
7198 | { |
7199 | regnames = regnames_32; |
7200 | regnames_count = ARRAY_SIZE (regnames_32)(sizeof (regnames_32) / sizeof ((regnames_32)[0])); |
7201 | } |
7202 | |
7203 | for (regnum = 0; regnum < regnames_count; regnum++) |
7204 | if (regnames[regnum] != NULL((void*)0) |
7205 | && strcmp (regname, regnames[regnum]) == 0) |
7206 | return regnum; |
7207 | |
7208 | return -1; |
7209 | } |
7210 | |
7211 | void |
7212 | tc_x86_frame_initial_instructions (void) |
7213 | { |
7214 | static unsigned int sp_regno; |
7215 | |
7216 | if (!sp_regno) |
7217 | sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT |
7218 | ? "rsp" : "esp"); |
7219 | |
7220 | cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment); |
7221 | cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment); |
7222 | } |
7223 | |
7224 | int |
7225 | i386_elf_section_type (const char *str, size_t len) |
7226 | { |
7227 | if (flag_code == CODE_64BIT |
7228 | && len == sizeof ("unwind") - 1 |
7229 | && strncmp (str, "unwind", 6) == 0) |
7230 | return SHT_X86_64_UNWIND0x70000001; |
7231 | |
7232 | return -1; |
7233 | } |
7234 | |
7235 | #ifdef TE_PE |
7236 | void |
7237 | tc_pe_dwarf2_emit_offset (symbolS *symbol, unsigned int size) |
7238 | { |
7239 | expressionS expr; |
7240 | |
7241 | expr.X_op = O_secrel; |
7242 | expr.X_add_symbol = symbol; |
7243 | expr.X_add_number = 0; |
7244 | emit_expr (&expr, size); |
7245 | } |
7246 | #endif |
7247 | |
7248 | #if defined (OBJ_ELF1) || defined (OBJ_MAYBE_ELF) |
7249 | /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */ |
7250 | |
7251 | int |
7252 | x86_64_section_letter (int letter, char **ptr_msg) |
7253 | { |
7254 | if (flag_code == CODE_64BIT) |
7255 | { |
7256 | if (letter == 'l') |
7257 | return SHF_X86_64_LARGE0x10000000; |
7258 | |
7259 | *ptr_msg = _("Bad .section directive: want a,l,w,x,M,S,G,T in string")("Bad .section directive: want a,l,w,x,M,S,G,T in string"); |
7260 | } |
7261 | else |
7262 | *ptr_msg = _("Bad .section directive: want a,w,x,M,S,G,T in string")("Bad .section directive: want a,w,x,M,S,G,T in string"); |
7263 | return -1; |
7264 | } |
7265 | |
7266 | int |
7267 | x86_64_section_word (char *str, size_t len) |
7268 | { |
7269 | if (len == 5 && flag_code == CODE_64BIT && strncmp (str, "large", 5) == 0) |
7270 | return SHF_X86_64_LARGE0x10000000; |
7271 | |
7272 | return -1; |
7273 | } |
7274 | |
7275 | static void |
7276 | handle_large_common (int small ATTRIBUTE_UNUSED__attribute__ ((__unused__))) |
7277 | { |
7278 | if (flag_code != CODE_64BIT) |
7279 | { |
7280 | s_comm_internal (0, elf_common_parse); |
7281 | as_warn (_(".largecomm supported only in 64bit mode, producing .comm")(".largecomm supported only in 64bit mode, producing .comm")); |
7282 | } |
7283 | else |
7284 | { |
7285 | static segT lbss_section; |
7286 | asection *saved_com_section_ptr = elf_com_section_ptr; |
7287 | asection *saved_bss_section = bss_section; |
7288 | |
7289 | if (lbss_section == NULL((void*)0)) |
7290 | { |
7291 | flagword applicable; |
7292 | segT seg = now_seg; |
7293 | subsegT subseg = now_subseg; |
7294 | |
7295 | /* The .lbss section is for local .largecomm symbols. */ |
7296 | lbss_section = subseg_new (".lbss", 0); |
7297 | applicable = bfd_applicable_section_flags (stdoutput)((stdoutput)->xvec->section_flags); |
7298 | bfd_set_section_flags (stdoutput, lbss_section, |
7299 | applicable & SEC_ALLOC0x001); |
7300 | seg_info (lbss_section)->bss = 1; |
7301 | |
7302 | subseg_set (seg, subseg); |
7303 | } |
7304 | |
7305 | elf_com_section_ptr = &_bfd_elf_large_com_section; |
7306 | bss_section = lbss_section; |
7307 | |
7308 | s_comm_internal (0, elf_common_parse); |
7309 | |
7310 | elf_com_section_ptr = saved_com_section_ptr; |
7311 | bss_section = saved_bss_section; |
7312 | } |
7313 | } |
7314 | #endif /* OBJ_ELF || OBJ_MAYBE_ELF */ |