clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name R600InstrInfo.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/gnu/usr.bin/clang/libLLVM/obj -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Analysis -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ASMParser -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/BinaryFormat -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitcode -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitcode -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitstream -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /include/llvm/CodeGen -I /include/llvm/CodeGen/PBQP -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/IR -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/IR -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Coroutines -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ProfileData/Coverage -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/CodeView -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/DWARF -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/MSF -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/PDB -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Demangle -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine/JITLink -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine/Orc -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend/OpenACC -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend/OpenMP -I /include/llvm/CodeGen/GlobalISel -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/IRReader -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/InstCombine -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/Transforms/InstCombine -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/LTO -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Linker -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/MC -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/MC/MCParser -I /include/llvm/CodeGen/MIRParser -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Object -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Option -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Passes -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ProfileData -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Scalar -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ADT -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Support -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/Symbolize -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Target -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Utils -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Vectorize -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/IPO -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include -I /usr/src/gnu/usr.bin/clang/libLLVM/../include -I /usr/src/gnu/usr.bin/clang/libLLVM/obj -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include -D NDEBUG -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D LLVM_PREFIX="/usr" -internal-isystem /usr/include/c++/v1 -internal-isystem /usr/local/lib/clang/13.0.0/include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/usr/src/gnu/usr.bin/clang/libLLVM/obj -ferror-limit 19 -fvisibility-inlines-hidden -fwrapv -stack-protector 2 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /home/ben/Projects/vmm/scan-build/2022-01-12-194120-40624-1 -x c++ /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp
1 | |
2 | |
3 | |
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5 | |
6 | |
7 | |
8 | |
9 | |
10 | |
11 | |
12 | |
13 | |
14 | #include "R600InstrInfo.h" |
15 | #include "AMDGPU.h" |
16 | #include "MCTargetDesc/AMDGPUMCTargetDesc.h" |
17 | #include "R600Defines.h" |
18 | #include "R600Subtarget.h" |
19 | #include "llvm/ADT/SmallSet.h" |
20 | |
21 | using namespace llvm; |
22 | |
23 | #define GET_INSTRINFO_CTOR_DTOR |
24 | #include "R600GenDFAPacketizer.inc" |
25 | |
26 | #define GET_INSTRINFO_CTOR_DTOR |
27 | #define GET_INSTRMAP_INFO |
28 | #define GET_INSTRINFO_NAMED_OPS |
29 | #include "R600GenInstrInfo.inc" |
30 | |
31 | R600InstrInfo::R600InstrInfo(const R600Subtarget &ST) |
32 | : R600GenInstrInfo(-1, -1), RI(), ST(ST) {} |
33 | |
34 | bool R600InstrInfo::isVector(const MachineInstr &MI) const { |
35 | return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; |
36 | } |
37 | |
38 | void R600InstrInfo::copyPhysReg(MachineBasicBlock &MBB, |
39 | MachineBasicBlock::iterator MI, |
40 | const DebugLoc &DL, MCRegister DestReg, |
41 | MCRegister SrcReg, bool KillSrc) const { |
42 | unsigned VectorComponents = 0; |
43 | if ((R600::R600_Reg128RegClass.contains(DestReg) || |
44 | R600::R600_Reg128VerticalRegClass.contains(DestReg)) && |
45 | (R600::R600_Reg128RegClass.contains(SrcReg) || |
46 | R600::R600_Reg128VerticalRegClass.contains(SrcReg))) { |
47 | VectorComponents = 4; |
48 | } else if((R600::R600_Reg64RegClass.contains(DestReg) || |
49 | R600::R600_Reg64VerticalRegClass.contains(DestReg)) && |
50 | (R600::R600_Reg64RegClass.contains(SrcReg) || |
51 | R600::R600_Reg64VerticalRegClass.contains(SrcReg))) { |
52 | VectorComponents = 2; |
53 | } |
54 | |
55 | if (VectorComponents > 0) { |
56 | for (unsigned I = 0; I < VectorComponents; I++) { |
57 | unsigned SubRegIndex = R600RegisterInfo::getSubRegFromChannel(I); |
58 | buildDefaultInstruction(MBB, MI, R600::MOV, |
59 | RI.getSubReg(DestReg, SubRegIndex), |
60 | RI.getSubReg(SrcReg, SubRegIndex)) |
61 | .addReg(DestReg, |
62 | RegState::Define | RegState::Implicit); |
63 | } |
64 | } else { |
65 | MachineInstr *NewMI = buildDefaultInstruction(MBB, MI, R600::MOV, |
66 | DestReg, SrcReg); |
67 | NewMI->getOperand(getOperandIdx(*NewMI, R600::OpName::src0)) |
68 | .setIsKill(KillSrc); |
69 | } |
70 | } |
71 | |
72 | |
73 | bool R600InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB, |
74 | MachineBasicBlock::iterator MBBI) const { |
75 | for (MachineInstr::const_mop_iterator I = MBBI->operands_begin(), |
76 | E = MBBI->operands_end(); I != E; ++I) { |
77 | if (I->isReg() && !I->getReg().isVirtual() && I->isUse() && |
78 | RI.isPhysRegLiveAcrossClauses(I->getReg())) |
79 | return false; |
80 | } |
81 | return true; |
82 | } |
83 | |
84 | bool R600InstrInfo::isMov(unsigned Opcode) const { |
85 | switch(Opcode) { |
86 | default: |
87 | return false; |
88 | case R600::MOV: |
89 | case R600::MOV_IMM_F32: |
90 | case R600::MOV_IMM_I32: |
91 | return true; |
92 | } |
93 | } |
94 | |
95 | bool R600InstrInfo::isReductionOp(unsigned Opcode) const { |
96 | return false; |
97 | } |
98 | |
99 | bool R600InstrInfo::isCubeOp(unsigned Opcode) const { |
100 | switch(Opcode) { |
101 | default: return false; |
102 | case R600::CUBE_r600_pseudo: |
103 | case R600::CUBE_r600_real: |
104 | case R600::CUBE_eg_pseudo: |
105 | case R600::CUBE_eg_real: |
106 | return true; |
107 | } |
108 | } |
109 | |
110 | bool R600InstrInfo::isALUInstr(unsigned Opcode) const { |
111 | unsigned TargetFlags = get(Opcode).TSFlags; |
112 | |
113 | return (TargetFlags & R600_InstFlag::ALU_INST); |
114 | } |
115 | |
116 | bool R600InstrInfo::hasInstrModifiers(unsigned Opcode) const { |
117 | unsigned TargetFlags = get(Opcode).TSFlags; |
118 | |
119 | return ((TargetFlags & R600_InstFlag::OP1) | |
120 | (TargetFlags & R600_InstFlag::OP2) | |
121 | (TargetFlags & R600_InstFlag::OP3)); |
122 | } |
123 | |
124 | bool R600InstrInfo::isLDSInstr(unsigned Opcode) const { |
125 | unsigned TargetFlags = get(Opcode).TSFlags; |
126 | |
127 | return ((TargetFlags & R600_InstFlag::LDS_1A) | |
128 | (TargetFlags & R600_InstFlag::LDS_1A1D) | |
129 | (TargetFlags & R600_InstFlag::LDS_1A2D)); |
130 | } |
131 | |
132 | bool R600InstrInfo::isLDSRetInstr(unsigned Opcode) const { |
133 | return isLDSInstr(Opcode) && getOperandIdx(Opcode, R600::OpName::dst) != -1; |
134 | } |
135 | |
136 | bool R600InstrInfo::canBeConsideredALU(const MachineInstr &MI) const { |
137 | if (isALUInstr(MI.getOpcode())) |
138 | return true; |
139 | if (isVector(MI) || isCubeOp(MI.getOpcode())) |
140 | return true; |
141 | switch (MI.getOpcode()) { |
142 | case R600::PRED_X: |
143 | case R600::INTERP_PAIR_XY: |
144 | case R600::INTERP_PAIR_ZW: |
145 | case R600::INTERP_VEC_LOAD: |
146 | case R600::COPY: |
147 | case R600::DOT_4: |
148 | return true; |
149 | default: |
150 | return false; |
151 | } |
152 | } |
153 | |
154 | bool R600InstrInfo::isTransOnly(unsigned Opcode) const { |
155 | if (ST.hasCaymanISA()) |
156 | return false; |
157 | return (get(Opcode).getSchedClass() == R600::Sched::TransALU); |
158 | } |
159 | |
160 | bool R600InstrInfo::isTransOnly(const MachineInstr &MI) const { |
161 | return isTransOnly(MI.getOpcode()); |
162 | } |
163 | |
164 | bool R600InstrInfo::isVectorOnly(unsigned Opcode) const { |
165 | return (get(Opcode).getSchedClass() == R600::Sched::VecALU); |
166 | } |
167 | |
168 | bool R600InstrInfo::isVectorOnly(const MachineInstr &MI) const { |
169 | return isVectorOnly(MI.getOpcode()); |
170 | } |
171 | |
172 | bool R600InstrInfo::isExport(unsigned Opcode) const { |
173 | return (get(Opcode).TSFlags & R600_InstFlag::IS_EXPORT); |
174 | } |
175 | |
176 | bool R600InstrInfo::usesVertexCache(unsigned Opcode) const { |
177 | return ST.hasVertexCache() && IS_VTX(get(Opcode)); |
178 | } |
179 | |
180 | bool R600InstrInfo::usesVertexCache(const MachineInstr &MI) const { |
181 | const MachineFunction *MF = MI.getParent()->getParent(); |
182 | return !AMDGPU::isCompute(MF->getFunction().getCallingConv()) && |
183 | usesVertexCache(MI.getOpcode()); |
184 | } |
185 | |
186 | bool R600InstrInfo::usesTextureCache(unsigned Opcode) const { |
187 | return (!ST.hasVertexCache() && IS_VTX(get(Opcode))) || IS_TEX(get(Opcode)); |
188 | } |
189 | |
190 | bool R600InstrInfo::usesTextureCache(const MachineInstr &MI) const { |
191 | const MachineFunction *MF = MI.getParent()->getParent(); |
192 | return (AMDGPU::isCompute(MF->getFunction().getCallingConv()) && |
193 | usesVertexCache(MI.getOpcode())) || |
194 | usesTextureCache(MI.getOpcode()); |
195 | } |
196 | |
197 | bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const { |
198 | switch (Opcode) { |
199 | case R600::KILLGT: |
200 | case R600::GROUP_BARRIER: |
201 | return true; |
202 | default: |
203 | return false; |
204 | } |
205 | } |
206 | |
207 | bool R600InstrInfo::usesAddressRegister(MachineInstr &MI) const { |
208 | return MI.findRegisterUseOperandIdx(R600::AR_X, false, &RI) != -1; |
209 | } |
210 | |
211 | bool R600InstrInfo::definesAddressRegister(MachineInstr &MI) const { |
212 | return MI.findRegisterDefOperandIdx(R600::AR_X, false, false, &RI) != -1; |
213 | } |
214 | |
215 | bool R600InstrInfo::readsLDSSrcReg(const MachineInstr &MI) const { |
216 | if (!isALUInstr(MI.getOpcode())) { |
217 | return false; |
218 | } |
219 | for (MachineInstr::const_mop_iterator I = MI.operands_begin(), |
220 | E = MI.operands_end(); |
221 | I != E; ++I) { |
222 | if (!I->isReg() || !I->isUse() || I->getReg().isVirtual()) |
223 | continue; |
224 | |
225 | if (R600::R600_LDS_SRC_REGRegClass.contains(I->getReg())) |
226 | return true; |
227 | } |
228 | return false; |
229 | } |
230 | |
231 | int R600InstrInfo::getSelIdx(unsigned Opcode, unsigned SrcIdx) const { |
232 | static const unsigned SrcSelTable[][2] = { |
233 | {R600::OpName::src0, R600::OpName::src0_sel}, |
234 | {R600::OpName::src1, R600::OpName::src1_sel}, |
235 | {R600::OpName::src2, R600::OpName::src2_sel}, |
236 | {R600::OpName::src0_X, R600::OpName::src0_sel_X}, |
237 | {R600::OpName::src0_Y, R600::OpName::src0_sel_Y}, |
238 | {R600::OpName::src0_Z, R600::OpName::src0_sel_Z}, |
239 | {R600::OpName::src0_W, R600::OpName::src0_sel_W}, |
240 | {R600::OpName::src1_X, R600::OpName::src1_sel_X}, |
241 | {R600::OpName::src1_Y, R600::OpName::src1_sel_Y}, |
242 | {R600::OpName::src1_Z, R600::OpName::src1_sel_Z}, |
243 | {R600::OpName::src1_W, R600::OpName::src1_sel_W} |
244 | }; |
245 | |
246 | for (const auto &Row : SrcSelTable) { |
247 | if (getOperandIdx(Opcode, Row[0]) == (int)SrcIdx) { |
248 | return getOperandIdx(Opcode, Row[1]); |
249 | } |
250 | } |
251 | return -1; |
252 | } |
253 | |
254 | SmallVector<std::pair<MachineOperand *, int64_t>, 3> |
255 | R600InstrInfo::getSrcs(MachineInstr &MI) const { |
256 | SmallVector<std::pair<MachineOperand *, int64_t>, 3> Result; |
257 | |
258 | if (MI.getOpcode() == R600::DOT_4) { |
259 | static const unsigned OpTable[8][2] = { |
260 | {R600::OpName::src0_X, R600::OpName::src0_sel_X}, |
261 | {R600::OpName::src0_Y, R600::OpName::src0_sel_Y}, |
262 | {R600::OpName::src0_Z, R600::OpName::src0_sel_Z}, |
263 | {R600::OpName::src0_W, R600::OpName::src0_sel_W}, |
264 | {R600::OpName::src1_X, R600::OpName::src1_sel_X}, |
265 | {R600::OpName::src1_Y, R600::OpName::src1_sel_Y}, |
266 | {R600::OpName::src1_Z, R600::OpName::src1_sel_Z}, |
267 | {R600::OpName::src1_W, R600::OpName::src1_sel_W}, |
268 | }; |
269 | |
270 | for (unsigned j = 0; j < 8; j++) { |
271 | MachineOperand &MO = |
272 | MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][0])); |
273 | Register Reg = MO.getReg(); |
274 | if (Reg == R600::ALU_CONST) { |
275 | MachineOperand &Sel = |
276 | MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1])); |
277 | Result.push_back(std::make_pair(&MO, Sel.getImm())); |
278 | continue; |
279 | } |
280 | |
281 | } |
282 | return Result; |
283 | } |
284 | |
285 | static const unsigned OpTable[3][2] = { |
286 | {R600::OpName::src0, R600::OpName::src0_sel}, |
287 | {R600::OpName::src1, R600::OpName::src1_sel}, |
288 | {R600::OpName::src2, R600::OpName::src2_sel}, |
289 | }; |
290 | |
291 | for (unsigned j = 0; j < 3; j++) { |
292 | int SrcIdx = getOperandIdx(MI.getOpcode(), OpTable[j][0]); |
293 | if (SrcIdx < 0) |
294 | break; |
295 | MachineOperand &MO = MI.getOperand(SrcIdx); |
296 | Register Reg = MO.getReg(); |
297 | if (Reg == R600::ALU_CONST) { |
298 | MachineOperand &Sel = |
299 | MI.getOperand(getOperandIdx(MI.getOpcode(), OpTable[j][1])); |
300 | Result.push_back(std::make_pair(&MO, Sel.getImm())); |
301 | continue; |
302 | } |
303 | if (Reg == R600::ALU_LITERAL_X) { |
304 | MachineOperand &Operand = |
305 | MI.getOperand(getOperandIdx(MI.getOpcode(), R600::OpName::literal)); |
306 | if (Operand.isImm()) { |
307 | Result.push_back(std::make_pair(&MO, Operand.getImm())); |
308 | continue; |
309 | } |
310 | assert(Operand.isGlobal()); |
311 | } |
312 | Result.push_back(std::make_pair(&MO, 0)); |
313 | } |
314 | return Result; |
315 | } |
316 | |
317 | std::vector<std::pair<int, unsigned>> |
318 | R600InstrInfo::ExtractSrcs(MachineInstr &MI, |
319 | const DenseMap<unsigned, unsigned> &PV, |
320 | unsigned &ConstCount) const { |
321 | ConstCount = 0; |
322 | const std::pair<int, unsigned> DummyPair(-1, 0); |
323 | std::vector<std::pair<int, unsigned>> Result; |
324 | unsigned i = 0; |
325 | for (const auto &Src : getSrcs(MI)) { |
326 | ++i; |
327 | Register Reg = Src.first->getReg(); |
328 | int Index = RI.getEncodingValue(Reg) & 0xff; |
329 | if (Reg == R600::OQAP) { |
330 | Result.push_back(std::make_pair(Index, 0U)); |
331 | } |
332 | if (PV.find(Reg) != PV.end()) { |
333 | |
334 | Result.push_back(std::make_pair(255, 0U)); |
335 | continue; |
336 | } |
337 | if (Index > 127) { |
338 | ConstCount++; |
339 | Result.push_back(DummyPair); |
340 | continue; |
341 | } |
342 | unsigned Chan = RI.getHWRegChan(Reg); |
343 | Result.push_back(std::make_pair(Index, Chan)); |
344 | } |
345 | for (; i < 3; ++i) |
346 | Result.push_back(DummyPair); |
347 | return Result; |
348 | } |
349 | |
350 | static std::vector<std::pair<int, unsigned>> |
351 | Swizzle(std::vector<std::pair<int, unsigned>> Src, |
352 | R600InstrInfo::BankSwizzle Swz) { |
353 | if (Src[0] == Src[1]) |
354 | Src[1].first = -1; |
355 | switch (Swz) { |
356 | case R600InstrInfo::ALU_VEC_012_SCL_210: |
357 | break; |
358 | case R600InstrInfo::ALU_VEC_021_SCL_122: |
359 | std::swap(Src[1], Src[2]); |
360 | break; |
361 | case R600InstrInfo::ALU_VEC_102_SCL_221: |
362 | std::swap(Src[0], Src[1]); |
363 | break; |
364 | case R600InstrInfo::ALU_VEC_120_SCL_212: |
365 | std::swap(Src[0], Src[1]); |
366 | std::swap(Src[0], Src[2]); |
367 | break; |
368 | case R600InstrInfo::ALU_VEC_201: |
369 | std::swap(Src[0], Src[2]); |
370 | std::swap(Src[0], Src[1]); |
371 | break; |
372 | case R600InstrInfo::ALU_VEC_210: |
373 | std::swap(Src[0], Src[2]); |
374 | break; |
375 | } |
376 | return Src; |
377 | } |
378 | |
379 | static unsigned getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) { |
380 | assert(Op < 3 && "Out of range swizzle index"); |
381 | switch (Swz) { |
382 | case R600InstrInfo::ALU_VEC_012_SCL_210: { |
383 | unsigned Cycles[3] = { 2, 1, 0}; |
384 | return Cycles[Op]; |
385 | } |
386 | case R600InstrInfo::ALU_VEC_021_SCL_122: { |
387 | unsigned Cycles[3] = { 1, 2, 2}; |
388 | return Cycles[Op]; |
389 | } |
390 | case R600InstrInfo::ALU_VEC_120_SCL_212: { |
391 | unsigned Cycles[3] = { 2, 1, 2}; |
392 | return Cycles[Op]; |
393 | } |
394 | case R600InstrInfo::ALU_VEC_102_SCL_221: { |
395 | unsigned Cycles[3] = { 2, 2, 1}; |
396 | return Cycles[Op]; |
397 | } |
398 | default: |
399 | llvm_unreachable("Wrong Swizzle for Trans Slot"); |
400 | } |
401 | } |
402 | |
403 | |
404 | |
405 | |
406 | unsigned R600InstrInfo::isLegalUpTo( |
407 | const std::vector<std::vector<std::pair<int, unsigned>>> &IGSrcs, |
408 | const std::vector<R600InstrInfo::BankSwizzle> &Swz, |
409 | const std::vector<std::pair<int, unsigned>> &TransSrcs, |
410 | R600InstrInfo::BankSwizzle TransSwz) const { |
411 | int Vector[4][3]; |
412 | memset(Vector, -1, sizeof(Vector)); |
413 | for (unsigned i = 0, e = IGSrcs.size(); i < e; i++) { |
414 | const std::vector<std::pair<int, unsigned>> &Srcs = |
415 | Swizzle(IGSrcs[i], Swz[i]); |
416 | for (unsigned j = 0; j < 3; j++) { |
417 | const std::pair<int, unsigned> &Src = Srcs[j]; |
418 | if (Src.first < 0 || Src.first == 255) |
419 | continue; |
420 | if (Src.first == GET_REG_INDEX(RI.getEncodingValue(R600::OQAP))) { |
421 | if (Swz[i] != R600InstrInfo::ALU_VEC_012_SCL_210 && |
422 | Swz[i] != R600InstrInfo::ALU_VEC_021_SCL_122) { |
423 | |
424 | |
425 | return false; |
426 | } |
427 | |
428 | continue; |
429 | } |
430 | if (Vector[Src.second][j] < 0) |
431 | Vector[Src.second][j] = Src.first; |
432 | if (Vector[Src.second][j] != Src.first) |
433 | return i; |
434 | } |
435 | } |
436 | |
437 | for (unsigned i = 0, e = TransSrcs.size(); i < e; ++i) { |
438 | const std::pair<int, unsigned> &Src = TransSrcs[i]; |
439 | unsigned Cycle = getTransSwizzle(TransSwz, i); |
440 | if (Src.first < 0) |
441 | continue; |
442 | if (Src.first == 255) |
443 | continue; |
444 | if (Vector[Src.second][Cycle] < 0) |
445 | Vector[Src.second][Cycle] = Src.first; |
446 | if (Vector[Src.second][Cycle] != Src.first) |
447 | return IGSrcs.size() - 1; |
448 | } |
449 | return IGSrcs.size(); |
450 | } |
451 | |
452 | |
453 | |
454 | |
455 | static bool |
456 | NextPossibleSolution( |
457 | std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, |
458 | unsigned Idx) { |
459 | assert(Idx < SwzCandidate.size()); |
460 | int ResetIdx = Idx; |
461 | while (ResetIdx > -1 && SwzCandidate[ResetIdx] == R600InstrInfo::ALU_VEC_210) |
462 | ResetIdx --; |
463 | for (unsigned i = ResetIdx + 1, e = SwzCandidate.size(); i < e; i++) { |
464 | SwzCandidate[i] = R600InstrInfo::ALU_VEC_012_SCL_210; |
465 | } |
466 | if (ResetIdx == -1) |
467 | return false; |
468 | int NextSwizzle = SwzCandidate[ResetIdx] + 1; |
469 | SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle; |
470 | return true; |
471 | } |
472 | |
473 | |
474 | |
475 | bool R600InstrInfo::FindSwizzleForVectorSlot( |
476 | const std::vector<std::vector<std::pair<int, unsigned>>> &IGSrcs, |
477 | std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate, |
478 | const std::vector<std::pair<int, unsigned>> &TransSrcs, |
479 | R600InstrInfo::BankSwizzle TransSwz) const { |
480 | unsigned ValidUpTo = 0; |
481 | do { |
482 | ValidUpTo = isLegalUpTo(IGSrcs, SwzCandidate, TransSrcs, TransSwz); |
483 | if (ValidUpTo == IGSrcs.size()) |
484 | return true; |
485 | } while (NextPossibleSolution(SwzCandidate, ValidUpTo)); |
486 | return false; |
487 | } |
488 | |
489 | |
490 | |
491 | static bool |
492 | isConstCompatible(R600InstrInfo::BankSwizzle TransSwz, |
493 | const std::vector<std::pair<int, unsigned>> &TransOps, |
494 | unsigned ConstCount) { |
495 | |
496 | if (ConstCount > 2) |
497 | return false; |
498 | for (unsigned i = 0, e = TransOps.size(); i < e; ++i) { |
499 | const std::pair<int, unsigned> &Src = TransOps[i]; |
500 | unsigned Cycle = getTransSwizzle(TransSwz, i); |
501 | if (Src.first < 0) |
502 | continue; |
503 | if (ConstCount > 0 && Cycle == 0) |
504 | return false; |
505 | if (ConstCount > 1 && Cycle == 1) |
506 | return false; |
507 | } |
508 | return true; |
509 | } |
510 | |
511 | bool |
512 | R600InstrInfo::fitsReadPortLimitations(const std::vector<MachineInstr *> &IG, |
513 | const DenseMap<unsigned, unsigned> &PV, |
514 | std::vector<BankSwizzle> &ValidSwizzle, |
515 | bool isLastAluTrans) |
516 | const { |
517 | |
518 | |
519 | std::vector<std::vector<std::pair<int, unsigned>>> IGSrcs; |
520 | ValidSwizzle.clear(); |
521 | unsigned ConstCount; |
| 1 | 'ConstCount' declared without an initial value | |
|
522 | BankSwizzle TransBS = ALU_VEC_012_SCL_210; |
523 | for (unsigned i = 0, e = IG.size(); i < e; ++i) { |
| |
| 3 | | Loop condition is false. Execution continues on line 530 | |
|
524 | IGSrcs.push_back(ExtractSrcs(*IG[i], PV, ConstCount)); |
525 | unsigned Op = getOperandIdx(IG[i]->getOpcode(), |
526 | R600::OpName::bank_swizzle); |
527 | ValidSwizzle.push_back( (R600InstrInfo::BankSwizzle) |
528 | IG[i]->getOperand(Op).getImm()); |
529 | } |
530 | std::vector<std::pair<int, unsigned>> TransOps; |
531 | if (!isLastAluTrans) |
| 4 | | Assuming 'isLastAluTrans' is true | |
|
| |
532 | return FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, TransBS); |
533 | |
534 | TransOps = std::move(IGSrcs.back()); |
535 | IGSrcs.pop_back(); |
536 | ValidSwizzle.pop_back(); |
537 | |
538 | static const R600InstrInfo::BankSwizzle TransSwz[] = { |
539 | ALU_VEC_012_SCL_210, |
540 | ALU_VEC_021_SCL_122, |
541 | ALU_VEC_120_SCL_212, |
542 | ALU_VEC_102_SCL_221 |
543 | }; |
544 | for (unsigned i = 0; i < 4; i++) { |
| 6 | | Loop condition is true. Entering loop body | |
|
545 | TransBS = TransSwz[i]; |
546 | if (!isConstCompatible(TransBS, TransOps, ConstCount)) |
| 7 | | 3rd function call argument is an uninitialized value |
|
547 | continue; |
548 | bool Result = FindSwizzleForVectorSlot(IGSrcs, ValidSwizzle, TransOps, |
549 | TransBS); |
550 | if (Result) { |
551 | ValidSwizzle.push_back(TransBS); |
552 | return true; |
553 | } |
554 | } |
555 | |
556 | return false; |
557 | } |
558 | |
559 | bool |
560 | R600InstrInfo::fitsConstReadLimitations(const std::vector<unsigned> &Consts) |
561 | const { |
562 | assert (Consts.size() <= 12 && "Too many operands in instructions group"); |
563 | unsigned Pair1 = 0, Pair2 = 0; |
564 | for (unsigned i = 0, n = Consts.size(); i < n; ++i) { |
565 | unsigned ReadConstHalf = Consts[i] & 2; |
566 | unsigned ReadConstIndex = Consts[i] & (~3); |
567 | unsigned ReadHalfConst = ReadConstIndex | ReadConstHalf; |
568 | if (!Pair1) { |
569 | Pair1 = ReadHalfConst; |
570 | continue; |
571 | } |
572 | if (Pair1 == ReadHalfConst) |
573 | continue; |
574 | if (!Pair2) { |
575 | Pair2 = ReadHalfConst; |
576 | continue; |
577 | } |
578 | if (Pair2 != ReadHalfConst) |
579 | return false; |
580 | } |
581 | return true; |
582 | } |
583 | |
584 | bool |
585 | R600InstrInfo::fitsConstReadLimitations(const std::vector<MachineInstr *> &MIs) |
586 | const { |
587 | std::vector<unsigned> Consts; |
588 | SmallSet<int64_t, 4> Literals; |
589 | for (unsigned i = 0, n = MIs.size(); i < n; i++) { |
590 | MachineInstr &MI = *MIs[i]; |
591 | if (!isALUInstr(MI.getOpcode())) |
592 | continue; |
593 | |
594 | for (const auto &Src : getSrcs(MI)) { |
595 | if (Src.first->getReg() == R600::ALU_LITERAL_X) |
596 | Literals.insert(Src.second); |
597 | if (Literals.size() > 4) |
598 | return false; |
599 | if (Src.first->getReg() == R600::ALU_CONST) |
600 | Consts.push_back(Src.second); |
601 | if (R600::R600_KC0RegClass.contains(Src.first->getReg()) || |
602 | R600::R600_KC1RegClass.contains(Src.first->getReg())) { |
603 | unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff; |
604 | unsigned Chan = RI.getHWRegChan(Src.first->getReg()); |
605 | Consts.push_back((Index << 2) | Chan); |
606 | } |
607 | } |
608 | } |
609 | return fitsConstReadLimitations(Consts); |
610 | } |
611 | |
612 | DFAPacketizer * |
613 | R600InstrInfo::CreateTargetScheduleState(const TargetSubtargetInfo &STI) const { |
614 | const InstrItineraryData *II = STI.getInstrItineraryData(); |
615 | return static_cast<const R600Subtarget &>(STI).createDFAPacketizer(II); |
616 | } |
617 | |
618 | static bool |
619 | isPredicateSetter(unsigned Opcode) { |
620 | switch (Opcode) { |
621 | case R600::PRED_X: |
622 | return true; |
623 | default: |
624 | return false; |
625 | } |
626 | } |
627 | |
628 | static MachineInstr * |
629 | findFirstPredicateSetterFrom(MachineBasicBlock &MBB, |
630 | MachineBasicBlock::iterator I) { |
631 | while (I != MBB.begin()) { |
632 | --I; |
633 | MachineInstr &MI = *I; |
634 | if (isPredicateSetter(MI.getOpcode())) |
635 | return &MI; |
636 | } |
637 | |
638 | return nullptr; |
639 | } |
640 | |
641 | static |
642 | bool isJump(unsigned Opcode) { |
643 | return Opcode == R600::JUMP || Opcode == R600::JUMP_COND; |
644 | } |
645 | |
646 | static bool isBranch(unsigned Opcode) { |
647 | return Opcode == R600::BRANCH || Opcode == R600::BRANCH_COND_i32 || |
648 | Opcode == R600::BRANCH_COND_f32; |
649 | } |
650 | |
651 | bool R600InstrInfo::analyzeBranch(MachineBasicBlock &MBB, |
652 | MachineBasicBlock *&TBB, |
653 | MachineBasicBlock *&FBB, |
654 | SmallVectorImpl<MachineOperand> &Cond, |
655 | bool AllowModify) const { |
656 | |
657 | |
658 | |
659 | MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr(); |
660 | if (I == MBB.end()) |
661 | return false; |
662 | |
663 | |
664 | |
665 | if (isBranch(I->getOpcode())) |
666 | return true; |
667 | if (!isJump(I->getOpcode())) { |
668 | return false; |
669 | } |
670 | |
671 | |
672 | while (I != MBB.begin() && std::prev(I)->getOpcode() == R600::JUMP) { |
673 | MachineBasicBlock::iterator PriorI = std::prev(I); |
674 | if (AllowModify) |
675 | I->removeFromParent(); |
676 | I = PriorI; |
677 | } |
678 | MachineInstr &LastInst = *I; |
679 | |
680 | |
681 | unsigned LastOpc = LastInst.getOpcode(); |
682 | if (I == MBB.begin() || !isJump((--I)->getOpcode())) { |
683 | if (LastOpc == R600::JUMP) { |
684 | TBB = LastInst.getOperand(0).getMBB(); |
685 | return false; |
686 | } else if (LastOpc == R600::JUMP_COND) { |
687 | auto predSet = I; |
688 | while (!isPredicateSetter(predSet->getOpcode())) { |
689 | predSet = --I; |
690 | } |
691 | TBB = LastInst.getOperand(0).getMBB(); |
692 | Cond.push_back(predSet->getOperand(1)); |
693 | Cond.push_back(predSet->getOperand(2)); |
694 | Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false)); |
695 | return false; |
696 | } |
697 | return true; |
698 | } |
699 | |
700 | |
701 | MachineInstr &SecondLastInst = *I; |
702 | unsigned SecondLastOpc = SecondLastInst.getOpcode(); |
703 | |
704 | |
705 | if (SecondLastOpc == R600::JUMP_COND && LastOpc == R600::JUMP) { |
706 | auto predSet = --I; |
707 | while (!isPredicateSetter(predSet->getOpcode())) { |
708 | predSet = --I; |
709 | } |
710 | TBB = SecondLastInst.getOperand(0).getMBB(); |
711 | FBB = LastInst.getOperand(0).getMBB(); |
712 | Cond.push_back(predSet->getOperand(1)); |
713 | Cond.push_back(predSet->getOperand(2)); |
714 | Cond.push_back(MachineOperand::CreateReg(R600::PRED_SEL_ONE, false)); |
715 | return false; |
716 | } |
717 | |
718 | |
719 | return true; |
720 | } |
721 | |
722 | static |
723 | MachineBasicBlock::iterator FindLastAluClause(MachineBasicBlock &MBB) { |
724 | for (MachineBasicBlock::reverse_iterator It = MBB.rbegin(), E = MBB.rend(); |
725 | It != E; ++It) { |
726 | if (It->getOpcode() == R600::CF_ALU || |
727 | It->getOpcode() == R600::CF_ALU_PUSH_BEFORE) |
728 | return It.getReverse(); |
729 | } |
730 | return MBB.end(); |
731 | } |
732 | |
733 | unsigned R600InstrInfo::insertBranch(MachineBasicBlock &MBB, |
734 | MachineBasicBlock *TBB, |
735 | MachineBasicBlock *FBB, |
736 | ArrayRef<MachineOperand> Cond, |
737 | const DebugLoc &DL, |
738 | int *BytesAdded) const { |
739 | assert(TBB && "insertBranch must not be told to insert a fallthrough"); |
740 | assert(!BytesAdded && "code size not handled"); |
741 | |
742 | if (!FBB) { |
743 | if (Cond.empty()) { |
744 | BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(TBB); |
745 | return 1; |
746 | } else { |
747 | MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end()); |
748 | assert(PredSet && "No previous predicate !"); |
749 | addFlag(*PredSet, 0, MO_FLAG_PUSH); |
750 | PredSet->getOperand(2).setImm(Cond[1].getImm()); |
751 | |
752 | BuildMI(&MBB, DL, get(R600::JUMP_COND)) |
753 | .addMBB(TBB) |
754 | .addReg(R600::PREDICATE_BIT, RegState::Kill); |
755 | MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB); |
756 | if (CfAlu == MBB.end()) |
757 | return 1; |
758 | assert (CfAlu->getOpcode() == R600::CF_ALU); |
759 | CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE)); |
760 | return 1; |
761 | } |
762 | } else { |
763 | MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end()); |
764 | assert(PredSet && "No previous predicate !"); |
765 | addFlag(*PredSet, 0, MO_FLAG_PUSH); |
766 | PredSet->getOperand(2).setImm(Cond[1].getImm()); |
767 | BuildMI(&MBB, DL, get(R600::JUMP_COND)) |
768 | .addMBB(TBB) |
769 | .addReg(R600::PREDICATE_BIT, RegState::Kill); |
770 | BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(FBB); |
771 | MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB); |
772 | if (CfAlu == MBB.end()) |
773 | return 2; |
774 | assert (CfAlu->getOpcode() == R600::CF_ALU); |
775 | CfAlu->setDesc(get(R600::CF_ALU_PUSH_BEFORE)); |
776 | return 2; |
777 | } |
778 | } |
779 | |
780 | unsigned R600InstrInfo::removeBranch(MachineBasicBlock &MBB, |
781 | int *BytesRemoved) const { |
782 | assert(!BytesRemoved && "code size not handled"); |
783 | |
784 | |
785 | |
786 | |
787 | MachineBasicBlock::iterator I = MBB.end(); |
788 | |
789 | if (I == MBB.begin()) { |
790 | return 0; |
791 | } |
792 | --I; |
793 | switch (I->getOpcode()) { |
794 | default: |
795 | return 0; |
796 | case R600::JUMP_COND: { |
797 | MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I); |
798 | clearFlag(*predSet, 0, MO_FLAG_PUSH); |
799 | I->eraseFromParent(); |
800 | MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB); |
801 | if (CfAlu == MBB.end()) |
802 | break; |
803 | assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE); |
804 | CfAlu->setDesc(get(R600::CF_ALU)); |
805 | break; |
806 | } |
807 | case R600::JUMP: |
808 | I->eraseFromParent(); |
809 | break; |
810 | } |
811 | I = MBB.end(); |
812 | |
813 | if (I == MBB.begin()) { |
814 | return 1; |
815 | } |
816 | --I; |
817 | switch (I->getOpcode()) { |
818 | |
819 | default: |
820 | return 1; |
821 | case R600::JUMP_COND: { |
822 | MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I); |
823 | clearFlag(*predSet, 0, MO_FLAG_PUSH); |
824 | I->eraseFromParent(); |
825 | MachineBasicBlock::iterator CfAlu = FindLastAluClause(MBB); |
826 | if (CfAlu == MBB.end()) |
827 | break; |
828 | assert (CfAlu->getOpcode() == R600::CF_ALU_PUSH_BEFORE); |
829 | CfAlu->setDesc(get(R600::CF_ALU)); |
830 | break; |
831 | } |
832 | case R600::JUMP: |
833 | I->eraseFromParent(); |
834 | break; |
835 | } |
836 | return 2; |
837 | } |
838 | |
839 | bool R600InstrInfo::isPredicated(const MachineInstr &MI) const { |
840 | int idx = MI.findFirstPredOperandIdx(); |
841 | if (idx < 0) |
842 | return false; |
843 | |
844 | Register Reg = MI.getOperand(idx).getReg(); |
845 | switch (Reg) { |
846 | default: return false; |
847 | case R600::PRED_SEL_ONE: |
848 | case R600::PRED_SEL_ZERO: |
849 | case R600::PREDICATE_BIT: |
850 | return true; |
851 | } |
852 | } |
853 | |
854 | bool R600InstrInfo::isPredicable(const MachineInstr &MI) const { |
855 | |
856 | |
857 | |
858 | |
859 | |
860 | if (MI.getOpcode() == R600::KILLGT) { |
861 | return false; |
862 | } else if (MI.getOpcode() == R600::CF_ALU) { |
863 | |
864 | |
865 | if (MI.getParent()->begin() != MachineBasicBlock::const_iterator(MI)) |
866 | return false; |
867 | |
868 | return MI.getOperand(3).getImm() == 0 && MI.getOperand(4).getImm() == 0; |
869 | } else if (isVector(MI)) { |
870 | return false; |
871 | } else { |
872 | return TargetInstrInfo::isPredicable(MI); |
873 | } |
874 | } |
875 | |
876 | bool |
877 | R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB, |
878 | unsigned NumCycles, |
879 | unsigned ExtraPredCycles, |
880 | BranchProbability Probability) const{ |
881 | return true; |
882 | } |
883 | |
884 | bool |
885 | R600InstrInfo::isProfitableToIfCvt(MachineBasicBlock &TMBB, |
886 | unsigned NumTCycles, |
887 | unsigned ExtraTCycles, |
888 | MachineBasicBlock &FMBB, |
889 | unsigned NumFCycles, |
890 | unsigned ExtraFCycles, |
891 | BranchProbability Probability) const { |
892 | return true; |
893 | } |
894 | |
895 | bool |
896 | R600InstrInfo::isProfitableToDupForIfCvt(MachineBasicBlock &MBB, |
897 | unsigned NumCycles, |
898 | BranchProbability Probability) |
899 | const { |
900 | return true; |
901 | } |
902 | |
903 | bool |
904 | R600InstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB, |
905 | MachineBasicBlock &FMBB) const { |
906 | return false; |
907 | } |
908 | |
909 | bool |
910 | R600InstrInfo::reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { |
911 | MachineOperand &MO = Cond[1]; |
912 | switch (MO.getImm()) { |
913 | case R600::PRED_SETE_INT: |
914 | MO.setImm(R600::PRED_SETNE_INT); |
915 | break; |
916 | case R600::PRED_SETNE_INT: |
917 | MO.setImm(R600::PRED_SETE_INT); |
918 | break; |
919 | case R600::PRED_SETE: |
920 | MO.setImm(R600::PRED_SETNE); |
921 | break; |
922 | case R600::PRED_SETNE: |
923 | MO.setImm(R600::PRED_SETE); |
924 | break; |
925 | default: |
926 | return true; |
927 | } |
928 | |
929 | MachineOperand &MO2 = Cond[2]; |
930 | switch (MO2.getReg()) { |
931 | case R600::PRED_SEL_ZERO: |
932 | MO2.setReg(R600::PRED_SEL_ONE); |
933 | break; |
934 | case R600::PRED_SEL_ONE: |
935 | MO2.setReg(R600::PRED_SEL_ZERO); |
936 | break; |
937 | default: |
938 | return true; |
939 | } |
940 | return false; |
941 | } |
942 | |
943 | bool R600InstrInfo::ClobbersPredicate(MachineInstr &MI, |
944 | std::vector<MachineOperand> &Pred, |
945 | bool SkipDead) const { |
946 | return isPredicateSetter(MI.getOpcode()); |
947 | } |
948 | |
949 | bool R600InstrInfo::PredicateInstruction(MachineInstr &MI, |
950 | ArrayRef<MachineOperand> Pred) const { |
951 | int PIdx = MI.findFirstPredOperandIdx(); |
952 | |
953 | if (MI.getOpcode() == R600::CF_ALU) { |
954 | MI.getOperand(8).setImm(0); |
955 | return true; |
956 | } |
957 | |
958 | if (MI.getOpcode() == R600::DOT_4) { |
959 | MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_X)) |
960 | .setReg(Pred[2].getReg()); |
961 | MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_Y)) |
962 | .setReg(Pred[2].getReg()); |
963 | MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_Z)) |
964 | .setReg(Pred[2].getReg()); |
965 | MI.getOperand(getOperandIdx(MI, R600::OpName::pred_sel_W)) |
966 | .setReg(Pred[2].getReg()); |
967 | MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); |
968 | MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit); |
969 | return true; |
970 | } |
971 | |
972 | if (PIdx != -1) { |
973 | MachineOperand &PMO = MI.getOperand(PIdx); |
974 | PMO.setReg(Pred[2].getReg()); |
975 | MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI); |
976 | MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit); |
977 | return true; |
978 | } |
979 | |
980 | return false; |
981 | } |
982 | |
983 | unsigned int R600InstrInfo::getPredicationCost(const MachineInstr &) const { |
984 | return 2; |
985 | } |
986 | |
987 | unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, |
988 | const MachineInstr &, |
989 | unsigned *PredCost) const { |
990 | if (PredCost) |
991 | *PredCost = 2; |
992 | return 2; |
993 | } |
994 | |
995 | unsigned R600InstrInfo::calculateIndirectAddress(unsigned RegIndex, |
996 | unsigned Channel) const { |
997 | assert(Channel == 0); |
998 | return RegIndex; |
999 | } |
1000 | |
1001 | bool R600InstrInfo::expandPostRAPseudo(MachineInstr &MI) const { |
1002 | switch (MI.getOpcode()) { |
1003 | default: { |
1004 | MachineBasicBlock *MBB = MI.getParent(); |
1005 | int OffsetOpIdx = |
1006 | R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::addr); |
1007 | |
1008 | |
1009 | int RegOpIdx = OffsetOpIdx + 1; |
1010 | int ChanOpIdx = |
1011 | R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::chan); |
1012 | if (isRegisterLoad(MI)) { |
1013 | int DstOpIdx = |
1014 | R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::dst); |
1015 | unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); |
1016 | unsigned Channel = MI.getOperand(ChanOpIdx).getImm(); |
1017 | unsigned Address = calculateIndirectAddress(RegIndex, Channel); |
1018 | Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); |
1019 | if (OffsetReg == R600::INDIRECT_BASE_ADDR) { |
1020 | buildMovInstr(MBB, MI, MI.getOperand(DstOpIdx).getReg(), |
1021 | getIndirectAddrRegClass()->getRegister(Address)); |
1022 | } else { |
1023 | buildIndirectRead(MBB, MI, MI.getOperand(DstOpIdx).getReg(), Address, |
1024 | OffsetReg); |
1025 | } |
1026 | } else if (isRegisterStore(MI)) { |
1027 | int ValOpIdx = |
1028 | R600::getNamedOperandIdx(MI.getOpcode(), R600::OpName::val); |
1029 | unsigned RegIndex = MI.getOperand(RegOpIdx).getImm(); |
1030 | unsigned Channel = MI.getOperand(ChanOpIdx).getImm(); |
1031 | unsigned Address = calculateIndirectAddress(RegIndex, Channel); |
1032 | Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg(); |
1033 | if (OffsetReg == R600::INDIRECT_BASE_ADDR) { |
1034 | buildMovInstr(MBB, MI, getIndirectAddrRegClass()->getRegister(Address), |
1035 | MI.getOperand(ValOpIdx).getReg()); |
1036 | } else { |
1037 | buildIndirectWrite(MBB, MI, MI.getOperand(ValOpIdx).getReg(), |
1038 | calculateIndirectAddress(RegIndex, Channel), |
1039 | OffsetReg); |
1040 | } |
1041 | } else { |
1042 | return false; |
1043 | } |
1044 | |
1045 | MBB->erase(MI); |
1046 | return true; |
1047 | } |
1048 | case R600::R600_EXTRACT_ELT_V2: |
1049 | case R600::R600_EXTRACT_ELT_V4: |
1050 | buildIndirectRead(MI.getParent(), MI, MI.getOperand(0).getReg(), |
1051 | RI.getHWRegIndex(MI.getOperand(1).getReg()), |
1052 | MI.getOperand(2).getReg(), |
1053 | RI.getHWRegChan(MI.getOperand(1).getReg())); |
1054 | break; |
1055 | case R600::R600_INSERT_ELT_V2: |
1056 | case R600::R600_INSERT_ELT_V4: |
1057 | buildIndirectWrite(MI.getParent(), MI, MI.getOperand(2).getReg(), |
1058 | RI.getHWRegIndex(MI.getOperand(1).getReg()), |
1059 | MI.getOperand(3).getReg(), |
1060 | RI.getHWRegChan(MI.getOperand(1).getReg())); |
1061 | break; |
1062 | } |
1063 | MI.eraseFromParent(); |
1064 | return true; |
1065 | } |
1066 | |
1067 | void R600InstrInfo::reserveIndirectRegisters(BitVector &Reserved, |
1068 | const MachineFunction &MF, |
1069 | const R600RegisterInfo &TRI) const { |
1070 | const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>(); |
1071 | const R600FrameLowering *TFL = ST.getFrameLowering(); |
1072 | |
1073 | unsigned StackWidth = TFL->getStackWidth(MF); |
1074 | int End = getIndirectIndexEnd(MF); |
1075 | |
1076 | if (End == -1) |
1077 | return; |
1078 | |
1079 | for (int Index = getIndirectIndexBegin(MF); Index <= End; ++Index) { |
1080 | for (unsigned Chan = 0; Chan < StackWidth; ++Chan) { |
1081 | unsigned Reg = R600::R600_TReg32RegClass.getRegister((4 * Index) + Chan); |
1082 | TRI.reserveRegisterTuples(Reserved, Reg); |
1083 | } |
1084 | } |
1085 | } |
1086 | |
1087 | const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const { |
1088 | return &R600::R600_TReg32_XRegClass; |
1089 | } |
1090 | |
1091 | MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB, |
1092 | MachineBasicBlock::iterator I, |
1093 | unsigned ValueReg, unsigned Address, |
1094 | unsigned OffsetReg) const { |
1095 | return buildIndirectWrite(MBB, I, ValueReg, Address, OffsetReg, 0); |
1096 | } |
1097 | |
1098 | MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB, |
1099 | MachineBasicBlock::iterator I, |
1100 | unsigned ValueReg, unsigned Address, |
1101 | unsigned OffsetReg, |
1102 | unsigned AddrChan) const { |
1103 | unsigned AddrReg; |
1104 | switch (AddrChan) { |
1105 | default: llvm_unreachable("Invalid Channel"); |
1106 | case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; |
1107 | case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; |
1108 | case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; |
1109 | case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break; |
1110 | } |
1111 | MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, R600::MOVA_INT_eg, |
1112 | R600::AR_X, OffsetReg); |
1113 | setImmOperand(*MOVA, R600::OpName::write, 0); |
1114 | |
1115 | MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV, |
1116 | AddrReg, ValueReg) |
1117 | .addReg(R600::AR_X, |
1118 | RegState::Implicit | RegState::Kill); |
1119 | setImmOperand(*Mov, R600::OpName::dst_rel, 1); |
1120 | return Mov; |
1121 | } |
1122 | |
1123 | MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB, |
1124 | MachineBasicBlock::iterator I, |
1125 | unsigned ValueReg, unsigned Address, |
1126 | unsigned OffsetReg) const { |
1127 | return buildIndirectRead(MBB, I, ValueReg, Address, OffsetReg, 0); |
1128 | } |
1129 | |
1130 | MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB, |
1131 | MachineBasicBlock::iterator I, |
1132 | unsigned ValueReg, unsigned Address, |
1133 | unsigned OffsetReg, |
1134 | unsigned AddrChan) const { |
1135 | unsigned AddrReg; |
1136 | switch (AddrChan) { |
1137 | default: llvm_unreachable("Invalid Channel"); |
1138 | case 0: AddrReg = R600::R600_AddrRegClass.getRegister(Address); break; |
1139 | case 1: AddrReg = R600::R600_Addr_YRegClass.getRegister(Address); break; |
1140 | case 2: AddrReg = R600::R600_Addr_ZRegClass.getRegister(Address); break; |
1141 | case 3: AddrReg = R600::R600_Addr_WRegClass.getRegister(Address); break; |
1142 | } |
1143 | MachineInstr *MOVA = buildDefaultInstruction(*MBB, I, R600::MOVA_INT_eg, |
1144 | R600::AR_X, |
1145 | OffsetReg); |
1146 | setImmOperand(*MOVA, R600::OpName::write, 0); |
1147 | MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV, |
1148 | ValueReg, |
1149 | AddrReg) |
1150 | .addReg(R600::AR_X, |
1151 | RegState::Implicit | RegState::Kill); |
1152 | setImmOperand(*Mov, R600::OpName::src0_rel, 1); |
1153 | |
1154 | return Mov; |
1155 | } |
1156 | |
1157 | int R600InstrInfo::getIndirectIndexBegin(const MachineFunction &MF) const { |
1158 | const MachineRegisterInfo &MRI = MF.getRegInfo(); |
1159 | const MachineFrameInfo &MFI = MF.getFrameInfo(); |
1160 | int Offset = -1; |
1161 | |
1162 | if (MFI.getNumObjects() == 0) { |
1163 | return -1; |
1164 | } |
1165 | |
1166 | if (MRI.livein_empty()) { |
1167 | return 0; |
1168 | } |
1169 | |
1170 | const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass(); |
1171 | for (std::pair<unsigned, unsigned> LI : MRI.liveins()) { |
1172 | Register Reg = LI.first; |
1173 | if (Reg.isVirtual() || !IndirectRC->contains(Reg)) |
1174 | continue; |
1175 | |
1176 | unsigned RegIndex; |
1177 | unsigned RegEnd; |
1178 | for (RegIndex = 0, RegEnd = IndirectRC->getNumRegs(); RegIndex != RegEnd; |
1179 | ++RegIndex) { |
1180 | if (IndirectRC->getRegister(RegIndex) == (unsigned)Reg) |
1181 | break; |
1182 | } |
1183 | Offset = std::max(Offset, (int)RegIndex); |
1184 | } |
1185 | |
1186 | return Offset + 1; |
1187 | } |
1188 | |
1189 | int R600InstrInfo::getIndirectIndexEnd(const MachineFunction &MF) const { |
1190 | int Offset = 0; |
1191 | const MachineFrameInfo &MFI = MF.getFrameInfo(); |
1192 | |
1193 | |
1194 | if (MFI.hasVarSizedObjects()) { |
1195 | return -1; |
1196 | } |
1197 | |
1198 | if (MFI.getNumObjects() == 0) { |
1199 | return -1; |
1200 | } |
1201 | |
1202 | const R600Subtarget &ST = MF.getSubtarget<R600Subtarget>(); |
1203 | const R600FrameLowering *TFL = ST.getFrameLowering(); |
1204 | |
1205 | Register IgnoredFrameReg; |
1206 | Offset = TFL->getFrameIndexReference(MF, -1, IgnoredFrameReg).getFixed(); |
1207 | |
1208 | return getIndirectIndexBegin(MF) + Offset; |
1209 | } |
1210 | |
1211 | unsigned R600InstrInfo::getMaxAlusPerClause() const { |
1212 | return 115; |
1213 | } |
1214 | |
1215 | MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB, |
1216 | MachineBasicBlock::iterator I, |
1217 | unsigned Opcode, |
1218 | unsigned DstReg, |
1219 | unsigned Src0Reg, |
1220 | unsigned Src1Reg) const { |
1221 | MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode), |
1222 | DstReg); |
1223 | |
1224 | if (Src1Reg) { |
1225 | MIB.addImm(0) |
1226 | .addImm(0); |
1227 | } |
1228 | MIB.addImm(1) |
1229 | .addImm(0) |
1230 | .addImm(0) |
1231 | .addImm(0) |
1232 | .addReg(Src0Reg) |
1233 | .addImm(0) |
1234 | .addImm(0) |
1235 | .addImm(0) |
1236 | .addImm(-1); |
1237 | |
1238 | if (Src1Reg) { |
1239 | MIB.addReg(Src1Reg) |
1240 | .addImm(0) |
1241 | .addImm(0) |
1242 | .addImm(0) |
1243 | .addImm(-1); |
1244 | } |
1245 | |
1246 | |
1247 | |
1248 | MIB.addImm(1) |
1249 | .addReg(R600::PRED_SEL_OFF) |
1250 | .addImm(0) |
1251 | .addImm(0); |
1252 | |
1253 | return MIB; |
1254 | } |
1255 | |
1256 | #define OPERAND_CASE(Label) \ |
1257 | case Label: { \ |
1258 | static const unsigned Ops[] = \ |
1259 | { \ |
1260 | Label##_X, \ |
1261 | Label##_Y, \ |
1262 | Label##_Z, \ |
1263 | Label##_W \ |
1264 | }; \ |
1265 | return Ops[Slot]; \ |
1266 | } |
1267 | |
1268 | static unsigned getSlotedOps(unsigned Op, unsigned Slot) { |
1269 | switch (Op) { |
1270 | OPERAND_CASE(R600::OpName::update_exec_mask) |
1271 | OPERAND_CASE(R600::OpName::update_pred) |
1272 | OPERAND_CASE(R600::OpName::write) |
1273 | OPERAND_CASE(R600::OpName::omod) |
1274 | OPERAND_CASE(R600::OpName::dst_rel) |
1275 | OPERAND_CASE(R600::OpName::clamp) |
1276 | OPERAND_CASE(R600::OpName::src0) |
1277 | OPERAND_CASE(R600::OpName::src0_neg) |
1278 | OPERAND_CASE(R600::OpName::src0_rel) |
1279 | OPERAND_CASE(R600::OpName::src0_abs) |
1280 | OPERAND_CASE(R600::OpName::src0_sel) |
1281 | OPERAND_CASE(R600::OpName::src1) |
1282 | OPERAND_CASE(R600::OpName::src1_neg) |
1283 | OPERAND_CASE(R600::OpName::src1_rel) |
1284 | OPERAND_CASE(R600::OpName::src1_abs) |
1285 | OPERAND_CASE(R600::OpName::src1_sel) |
1286 | OPERAND_CASE(R600::OpName::pred_sel) |
1287 | default: |
1288 | llvm_unreachable("Wrong Operand"); |
1289 | } |
1290 | } |
1291 | |
1292 | #undef OPERAND_CASE |
1293 | |
1294 | MachineInstr *R600InstrInfo::buildSlotOfVectorInstruction( |
1295 | MachineBasicBlock &MBB, MachineInstr *MI, unsigned Slot, unsigned DstReg) |
1296 | const { |
1297 | assert (MI->getOpcode() == R600::DOT_4 && "Not Implemented"); |
1298 | unsigned Opcode; |
1299 | if (ST.getGeneration() <= AMDGPUSubtarget::R700) |
1300 | Opcode = R600::DOT4_r600; |
1301 | else |
1302 | Opcode = R600::DOT4_eg; |
1303 | MachineBasicBlock::iterator I = MI; |
1304 | MachineOperand &Src0 = MI->getOperand( |
1305 | getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src0, Slot))); |
1306 | MachineOperand &Src1 = MI->getOperand( |
1307 | getOperandIdx(MI->getOpcode(), getSlotedOps(R600::OpName::src1, Slot))); |
1308 | MachineInstr *MIB = buildDefaultInstruction( |
1309 | MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg()); |
1310 | static const unsigned Operands[14] = { |
1311 | R600::OpName::update_exec_mask, |
1312 | R600::OpName::update_pred, |
1313 | R600::OpName::write, |
1314 | R600::OpName::omod, |
1315 | R600::OpName::dst_rel, |
1316 | R600::OpName::clamp, |
1317 | R600::OpName::src0_neg, |
1318 | R600::OpName::src0_rel, |
1319 | R600::OpName::src0_abs, |
1320 | R600::OpName::src0_sel, |
1321 | R600::OpName::src1_neg, |
1322 | R600::OpName::src1_rel, |
1323 | R600::OpName::src1_abs, |
1324 | R600::OpName::src1_sel, |
1325 | }; |
1326 | |
1327 | MachineOperand &MO = MI->getOperand(getOperandIdx(MI->getOpcode(), |
1328 | getSlotedOps(R600::OpName::pred_sel, Slot))); |
1329 | MIB->getOperand(getOperandIdx(Opcode, R600::OpName::pred_sel)) |
1330 | .setReg(MO.getReg()); |
1331 | |
1332 | for (unsigned i = 0; i < 14; i++) { |
1333 | MachineOperand &MO = MI->getOperand( |
1334 | getOperandIdx(MI->getOpcode(), getSlotedOps(Operands[i], Slot))); |
1335 | assert (MO.isImm()); |
1336 | setImmOperand(*MIB, Operands[i], MO.getImm()); |
1337 | } |
1338 | MIB->getOperand(20).setImm(0); |
1339 | return MIB; |
1340 | } |
1341 | |
1342 | MachineInstr *R600InstrInfo::buildMovImm(MachineBasicBlock &BB, |
1343 | MachineBasicBlock::iterator I, |
1344 | unsigned DstReg, |
1345 | uint64_t Imm) const { |
1346 | MachineInstr *MovImm = buildDefaultInstruction(BB, I, R600::MOV, DstReg, |
1347 | R600::ALU_LITERAL_X); |
1348 | setImmOperand(*MovImm, R600::OpName::literal, Imm); |
1349 | return MovImm; |
1350 | } |
1351 | |
1352 | MachineInstr *R600InstrInfo::buildMovInstr(MachineBasicBlock *MBB, |
1353 | MachineBasicBlock::iterator I, |
1354 | unsigned DstReg, unsigned SrcReg) const { |
1355 | return buildDefaultInstruction(*MBB, I, R600::MOV, DstReg, SrcReg); |
1356 | } |
1357 | |
1358 | int R600InstrInfo::getOperandIdx(const MachineInstr &MI, unsigned Op) const { |
1359 | return getOperandIdx(MI.getOpcode(), Op); |
1360 | } |
1361 | |
1362 | int R600InstrInfo::getOperandIdx(unsigned Opcode, unsigned Op) const { |
1363 | return R600::getNamedOperandIdx(Opcode, Op); |
1364 | } |
1365 | |
1366 | void R600InstrInfo::setImmOperand(MachineInstr &MI, unsigned Op, |
1367 | int64_t Imm) const { |
1368 | int Idx = getOperandIdx(MI, Op); |
1369 | assert(Idx != -1 && "Operand not supported for this instruction."); |
1370 | assert(MI.getOperand(Idx).isImm()); |
1371 | MI.getOperand(Idx).setImm(Imm); |
1372 | } |
1373 | |
1374 | |
1375 | |
1376 | |
1377 | |
1378 | MachineOperand &R600InstrInfo::getFlagOp(MachineInstr &MI, unsigned SrcIdx, |
1379 | unsigned Flag) const { |
1380 | unsigned TargetFlags = get(MI.getOpcode()).TSFlags; |
1381 | int FlagIndex = 0; |
1382 | if (Flag != 0) { |
1383 | |
1384 | |
1385 | |
1386 | assert(HAS_NATIVE_OPERANDS(TargetFlags)); |
1387 | bool IsOP3 = (TargetFlags & R600_InstFlag::OP3) == R600_InstFlag::OP3; |
1388 | switch (Flag) { |
1389 | case MO_FLAG_CLAMP: |
1390 | FlagIndex = getOperandIdx(MI, R600::OpName::clamp); |
1391 | break; |
1392 | case MO_FLAG_MASK: |
1393 | FlagIndex = getOperandIdx(MI, R600::OpName::write); |
1394 | break; |
1395 | case MO_FLAG_NOT_LAST: |
1396 | case MO_FLAG_LAST: |
1397 | FlagIndex = getOperandIdx(MI, R600::OpName::last); |
1398 | break; |
1399 | case MO_FLAG_NEG: |
1400 | switch (SrcIdx) { |
1401 | case 0: |
1402 | FlagIndex = getOperandIdx(MI, R600::OpName::src0_neg); |
1403 | break; |
1404 | case 1: |
1405 | FlagIndex = getOperandIdx(MI, R600::OpName::src1_neg); |
1406 | break; |
1407 | case 2: |
1408 | FlagIndex = getOperandIdx(MI, R600::OpName::src2_neg); |
1409 | break; |
1410 | } |
1411 | break; |
1412 | |
1413 | case MO_FLAG_ABS: |
1414 | assert(!IsOP3 && "Cannot set absolute value modifier for OP3 " |
1415 | "instructions."); |
1416 | (void)IsOP3; |
1417 | switch (SrcIdx) { |
1418 | case 0: |
1419 | FlagIndex = getOperandIdx(MI, R600::OpName::src0_abs); |
1420 | break; |
1421 | case 1: |
1422 | FlagIndex = getOperandIdx(MI, R600::OpName::src1_abs); |
1423 | break; |
1424 | } |
1425 | break; |
1426 | |
1427 | default: |
1428 | FlagIndex = -1; |
1429 | break; |
1430 | } |
1431 | assert(FlagIndex != -1 && "Flag not supported for this instruction"); |
1432 | } else { |
1433 | FlagIndex = GET_FLAG_OPERAND_IDX(TargetFlags); |
1434 | assert(FlagIndex != 0 && |
1435 | "Instruction flags not supported for this instruction"); |
1436 | } |
1437 | |
1438 | MachineOperand &FlagOp = MI.getOperand(FlagIndex); |
1439 | assert(FlagOp.isImm()); |
1440 | return FlagOp; |
1441 | } |
1442 | |
1443 | void R600InstrInfo::addFlag(MachineInstr &MI, unsigned Operand, |
1444 | unsigned Flag) const { |
1445 | unsigned TargetFlags = get(MI.getOpcode()).TSFlags; |
1446 | if (Flag == 0) { |
1447 | return; |
1448 | } |
1449 | if (HAS_NATIVE_OPERANDS(TargetFlags)) { |
1450 | MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag); |
1451 | if (Flag == MO_FLAG_NOT_LAST) { |
1452 | clearFlag(MI, Operand, MO_FLAG_LAST); |
1453 | } else if (Flag == MO_FLAG_MASK) { |
1454 | clearFlag(MI, Operand, Flag); |
1455 | } else { |
1456 | FlagOp.setImm(1); |
1457 | } |
1458 | } else { |
1459 | MachineOperand &FlagOp = getFlagOp(MI, Operand); |
1460 | FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand))); |
1461 | } |
1462 | } |
1463 | |
1464 | void R600InstrInfo::clearFlag(MachineInstr &MI, unsigned Operand, |
1465 | unsigned Flag) const { |
1466 | unsigned TargetFlags = get(MI.getOpcode()).TSFlags; |
1467 | if (HAS_NATIVE_OPERANDS(TargetFlags)) { |
1468 | MachineOperand &FlagOp = getFlagOp(MI, Operand, Flag); |
1469 | FlagOp.setImm(0); |
1470 | } else { |
1471 | MachineOperand &FlagOp = getFlagOp(MI); |
1472 | unsigned InstFlags = FlagOp.getImm(); |
1473 | InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand)); |
1474 | FlagOp.setImm(InstFlags); |
1475 | } |
1476 | } |
1477 | |
1478 | unsigned R600InstrInfo::getAddressSpaceForPseudoSourceKind( |
1479 | unsigned Kind) const { |
1480 | switch (Kind) { |
1481 | case PseudoSourceValue::Stack: |
1482 | case PseudoSourceValue::FixedStack: |
1483 | return AMDGPUAS::PRIVATE_ADDRESS; |
1484 | case PseudoSourceValue::ConstantPool: |
1485 | case PseudoSourceValue::GOT: |
1486 | case PseudoSourceValue::JumpTable: |
1487 | case PseudoSourceValue::GlobalValueCallEntry: |
1488 | case PseudoSourceValue::ExternalSymbolCallEntry: |
1489 | case PseudoSourceValue::TargetCustom: |
1490 | return AMDGPUAS::CONSTANT_ADDRESS; |
1491 | } |
1492 | |
1493 | llvm_unreachable("Invalid pseudo source kind"); |
1494 | } |