clang -cc1 -cc1 -triple amd64-unknown-openbsd7.0 -analyze -disable-free -disable-llvm-verifier -discard-value-names -main-file-name X86PartialReduction.cpp -analyzer-store=region -analyzer-opt-analyze-nested-blocks -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=cplusplus -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -fno-rounding-math -mconstructor-aliases -munwind-tables -target-cpu x86-64 -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/gnu/usr.bin/clang/libLLVM/obj -resource-dir /usr/local/lib/clang/13.0.0 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/AMDGPU -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Analysis -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ASMParser -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/BinaryFormat -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitcode -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitcode -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Bitstream -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /include/llvm/CodeGen -I /include/llvm/CodeGen/PBQP -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/IR -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/IR -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Coroutines -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ProfileData/Coverage -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/CodeView -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/DWARF -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/MSF -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/PDB -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Demangle -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine/JITLink -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ExecutionEngine/Orc -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend/OpenACC -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Frontend/OpenMP -I /include/llvm/CodeGen/GlobalISel -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/IRReader -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/InstCombine -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/Transforms/InstCombine -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/LTO -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Linker -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/MC -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/MC/MCParser -I /include/llvm/CodeGen/MIRParser -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Object -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Option -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Passes -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ProfileData -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Scalar -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/ADT -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Support -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/DebugInfo/Symbolize -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Target -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Utils -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/Vectorize -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include/llvm/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86 -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include/llvm/Transforms/IPO -I /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/include -I /usr/src/gnu/usr.bin/clang/libLLVM/../include -I /usr/src/gnu/usr.bin/clang/libLLVM/obj -I /usr/src/gnu/usr.bin/clang/libLLVM/obj/../include -D NDEBUG -D __STDC_LIMIT_MACROS -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D LLVM_PREFIX="/usr" -internal-isystem /usr/include/c++/v1 -internal-isystem /usr/local/lib/clang/13.0.0/include -internal-externc-isystem /usr/include -O2 -Wno-unused-parameter -Wwrite-strings -Wno-missing-field-initializers -Wno-long-long -Wno-comment -std=c++14 -fdeprecated-macro -fdebug-compilation-dir=/usr/src/gnu/usr.bin/clang/libLLVM/obj -ferror-limit 19 -fvisibility-inlines-hidden -fwrapv -stack-protector 2 -fno-rtti -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -o /home/ben/Projects/vmm/scan-build/2022-01-12-194120-40624-1 -x c++ /usr/src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/Target/X86/X86PartialReduction.cpp
1 | |
2 | |
3 | |
4 | |
5 | |
6 | |
7 | |
8 | |
9 | |
10 | |
11 | |
12 | |
13 | |
14 | |
15 | #include "X86.h" |
16 | #include "llvm/Analysis/ValueTracking.h" |
17 | #include "llvm/CodeGen/TargetPassConfig.h" |
18 | #include "llvm/IR/Constants.h" |
19 | #include "llvm/IR/Instructions.h" |
20 | #include "llvm/IR/IntrinsicsX86.h" |
21 | #include "llvm/IR/IRBuilder.h" |
22 | #include "llvm/IR/Operator.h" |
23 | #include "llvm/Pass.h" |
24 | #include "X86TargetMachine.h" |
25 | |
26 | using namespace llvm; |
27 | |
28 | #define DEBUG_TYPE "x86-partial-reduction" |
29 | |
30 | namespace { |
31 | |
32 | class X86PartialReduction : public FunctionPass { |
33 | const DataLayout *DL; |
34 | const X86Subtarget *ST; |
35 | |
36 | public: |
37 | static char ID; |
38 | |
39 | X86PartialReduction() : FunctionPass(ID) { } |
40 | |
41 | bool runOnFunction(Function &Fn) override; |
42 | |
43 | void getAnalysisUsage(AnalysisUsage &AU) const override { |
44 | AU.setPreservesCFG(); |
45 | } |
46 | |
47 | StringRef getPassName() const override { |
48 | return "X86 Partial Reduction"; |
49 | } |
50 | |
51 | private: |
52 | bool tryMAddReplacement(Instruction *Op); |
53 | bool trySADReplacement(Instruction *Op); |
54 | }; |
55 | } |
56 | |
57 | FunctionPass *llvm::createX86PartialReductionPass() { |
58 | return new X86PartialReduction(); |
59 | } |
60 | |
61 | char X86PartialReduction::ID = 0; |
62 | |
63 | INITIALIZE_PASS(X86PartialReduction, DEBUG_TYPE, |
64 | "X86 Partial Reduction", false, false) |
65 | |
66 | bool X86PartialReduction::tryMAddReplacement(Instruction *Op) { |
67 | if (!ST->hasSSE2()) |
68 | return false; |
69 | |
70 | |
71 | if (cast<FixedVectorType>(Op->getType())->getNumElements() < 8) |
72 | return false; |
73 | |
74 | |
75 | if (!cast<VectorType>(Op->getType())->getElementType()->isIntegerTy(32)) |
76 | return false; |
77 | |
78 | auto *Mul = dyn_cast<BinaryOperator>(Op); |
79 | if (!Mul || Mul->getOpcode() != Instruction::Mul) |
80 | return false; |
81 | |
82 | Value *LHS = Mul->getOperand(0); |
83 | Value *RHS = Mul->getOperand(1); |
84 | |
85 | |
86 | |
87 | |
88 | |
89 | if (ST->hasSSE41()) { |
90 | if (LHS == RHS) { |
91 | if (!isa<Constant>(LHS) && !LHS->hasNUses(2)) |
92 | return false; |
93 | } else { |
94 | if (!isa<Constant>(LHS) && !LHS->hasOneUse()) |
95 | return false; |
96 | if (!isa<Constant>(RHS) && !RHS->hasOneUse()) |
97 | return false; |
98 | } |
99 | } |
100 | |
101 | auto CanShrinkOp = [&](Value *Op) { |
102 | auto IsFreeTruncation = [&](Value *Op) { |
103 | if (auto *Cast = dyn_cast<CastInst>(Op)) { |
104 | if (Cast->getParent() == Mul->getParent() && |
105 | (Cast->getOpcode() == Instruction::SExt || |
106 | Cast->getOpcode() == Instruction::ZExt) && |
107 | Cast->getOperand(0)->getType()->getScalarSizeInBits() <= 16) |
108 | return true; |
109 | } |
110 | |
111 | return isa<Constant>(Op); |
112 | }; |
113 | |
114 | |
115 | |
116 | if (IsFreeTruncation(Op) && |
117 | ComputeNumSignBits(Op, *DL, 0, nullptr, Mul) > 16) |
118 | return true; |
119 | |
120 | |
121 | |
122 | if (auto *BO = dyn_cast<BinaryOperator>(Op)) { |
123 | if (BO->getParent() == Mul->getParent() && |
124 | IsFreeTruncation(BO->getOperand(0)) && |
125 | IsFreeTruncation(BO->getOperand(1)) && |
126 | ComputeNumSignBits(Op, *DL, 0, nullptr, Mul) > 16) |
127 | return true; |
128 | } |
129 | |
130 | return false; |
131 | }; |
132 | |
133 | |
134 | if (!CanShrinkOp(LHS) && !CanShrinkOp(RHS)) |
135 | return false; |
136 | |
137 | IRBuilder<> Builder(Mul); |
138 | |
139 | auto *MulTy = cast<FixedVectorType>(Op->getType()); |
140 | unsigned NumElts = MulTy->getNumElements(); |
141 | |
142 | |
143 | |
144 | |
145 | SmallVector<int, 16> EvenMask(NumElts / 2); |
146 | SmallVector<int, 16> OddMask(NumElts / 2); |
147 | for (int i = 0, e = NumElts / 2; i != e; ++i) { |
148 | EvenMask[i] = i * 2; |
149 | OddMask[i] = i * 2 + 1; |
150 | } |
151 | |
152 | |
153 | Value *NewMul = Builder.CreateMul(Mul->getOperand(0), Mul->getOperand(1)); |
154 | Value *EvenElts = Builder.CreateShuffleVector(NewMul, NewMul, EvenMask); |
155 | Value *OddElts = Builder.CreateShuffleVector(NewMul, NewMul, OddMask); |
156 | Value *MAdd = Builder.CreateAdd(EvenElts, OddElts); |
157 | |
158 | |
159 | SmallVector<int, 32> ConcatMask(NumElts); |
160 | std::iota(ConcatMask.begin(), ConcatMask.end(), 0); |
161 | Value *Zero = Constant::getNullValue(MAdd->getType()); |
162 | Value *Concat = Builder.CreateShuffleVector(MAdd, Zero, ConcatMask); |
163 | |
164 | Mul->replaceAllUsesWith(Concat); |
165 | Mul->eraseFromParent(); |
166 | |
167 | return true; |
168 | } |
169 | |
170 | bool X86PartialReduction::trySADReplacement(Instruction *Op) { |
171 | if (!ST->hasSSE2()) |
| 12 | | Calling 'X86Subtarget::hasSSE2' | |
|
| 14 | | Returning from 'X86Subtarget::hasSSE2' | |
|
| |
172 | return false; |
173 | |
174 | |
175 | |
176 | if (!cast<VectorType>(Op->getType())->getElementType()->isIntegerTy(32)) |
| 16 | | The object is a 'VectorType' | |
|
| 17 | | Assuming the condition is false | |
|
| |
177 | return false; |
178 | |
179 | |
180 | auto *SI = dyn_cast<SelectInst>(Op); |
| 19 | | Assuming 'Op' is a 'SelectInst' | |
|
181 | if (!SI) |
| |
182 | return false; |
183 | |
184 | |
185 | Value *LHS, *RHS; |
186 | auto SPR = matchSelectPattern(SI, LHS, RHS); |
187 | if (SPR.Flavor != SPF_ABS) |
| 21 | | Assuming field 'Flavor' is equal to SPF_ABS | |
|
| |
188 | return false; |
189 | |
190 | |
191 | auto *Sub = dyn_cast<BinaryOperator>(LHS); |
| 23 | | Assuming 'LHS' is a 'BinaryOperator' | |
|
192 | if (!Sub || Sub->getOpcode() != Instruction::Sub) |
| 24 | | Assuming the condition is false | |
|
| |
193 | return false; |
194 | |
195 | |
196 | auto getZeroExtendedVal = [](Value *Op) -> Value * { |
197 | if (auto *ZExt = dyn_cast<ZExtInst>(Op)) |
| 27 | | Assuming 'ZExt' is non-null | |
|
| |
| 35 | | Assuming 'ZExt' is non-null | |
|
| |
198 | if (cast<VectorType>(ZExt->getOperand(0)->getType()) |
| 29 | | The object is a 'VectorType' | |
|
| 30 | | Assuming the condition is true | |
|
| |
| 37 | | The object is a 'VectorType' | |
|
| 38 | | Assuming the condition is true | |
|
| |
199 | ->getElementType() |
200 | ->isIntegerTy(8)) |
201 | return ZExt->getOperand(0); |
| 32 | | Returning pointer, which participates in a condition later | |
|
| 40 | | Returning pointer, which participates in a condition later | |
|
202 | |
203 | return nullptr; |
204 | }; |
205 | |
206 | |
207 | Value *Op0 = getZeroExtendedVal(Sub->getOperand(0)); |
| |
| 33 | | Returning from 'operator()' | |
|
208 | Value *Op1 = getZeroExtendedVal(Sub->getOperand(1)); |
| |
| 41 | | Returning from 'operator()' | |
|
209 | if (!Op0 || !Op1) |
| |
210 | return false; |
211 | |
212 | IRBuilder<> Builder(SI); |
213 | |
214 | auto *OpTy = cast<FixedVectorType>(Op->getType()); |
| 43 | | The object is a 'FixedVectorType' | |
|
215 | unsigned NumElts = OpTy->getNumElements(); |
216 | |
217 | unsigned IntrinsicNumElts; |
218 | Intrinsic::ID IID; |
219 | if (ST->hasBWI() && NumElts >= 64) { |
| 44 | | Assuming the condition is false | |
|
220 | IID = Intrinsic::x86_avx512_psad_bw_512; |
221 | IntrinsicNumElts = 64; |
222 | } else if (ST->hasAVX2() && NumElts >= 32) { |
223 | IID = Intrinsic::x86_avx2_psad_bw; |
224 | IntrinsicNumElts = 32; |
225 | } else { |
226 | IID = Intrinsic::x86_sse2_psad_bw; |
227 | IntrinsicNumElts = 16; |
228 | } |
229 | |
230 | Function *PSADBWFn = Intrinsic::getDeclaration(SI->getModule(), IID); |
231 | |
232 | if (NumElts < 16) { |
| 45 | | Assuming 'NumElts' is >= 16 | |
|
| |
233 | |
234 | SmallVector<int, 32> ConcatMask(16); |
235 | for (unsigned i = 0; i != NumElts; ++i) |
236 | ConcatMask[i] = i; |
237 | for (unsigned i = NumElts; i != 16; ++i) |
238 | ConcatMask[i] = (i % NumElts) + NumElts; |
239 | |
240 | Value *Zero = Constant::getNullValue(Op0->getType()); |
241 | Op0 = Builder.CreateShuffleVector(Op0, Zero, ConcatMask); |
242 | Op1 = Builder.CreateShuffleVector(Op1, Zero, ConcatMask); |
243 | NumElts = 16; |
244 | } |
245 | |
246 | |
247 | auto *I32Ty = |
248 | FixedVectorType::get(Builder.getInt32Ty(), IntrinsicNumElts / 4); |
249 | |
250 | assert(NumElts % IntrinsicNumElts == 0 && "Unexpected number of elements!"); |
251 | unsigned NumSplits = NumElts / IntrinsicNumElts; |
252 | |
253 | |
254 | SmallVector<Value *, 4> Ops(NumSplits); |
255 | for (unsigned i = 0; i != NumSplits; ++i) { |
| 47 | | Assuming 'i' is not equal to 'NumSplits' | |
|
| 48 | | Loop condition is true. Entering loop body | |
|
| 49 | | Assuming 'i' is equal to 'NumSplits' | |
|
| 50 | | Loop condition is false. Execution continues on line 264 | |
|
256 | SmallVector<int, 64> ExtractMask(IntrinsicNumElts); |
257 | std::iota(ExtractMask.begin(), ExtractMask.end(), i * IntrinsicNumElts); |
258 | Value *ExtractOp0 = Builder.CreateShuffleVector(Op0, Op0, ExtractMask); |
259 | Value *ExtractOp1 = Builder.CreateShuffleVector(Op1, Op0, ExtractMask); |
260 | Ops[i] = Builder.CreateCall(PSADBWFn, {ExtractOp0, ExtractOp1}); |
261 | Ops[i] = Builder.CreateBitCast(Ops[i], I32Ty); |
262 | } |
263 | |
264 | assert(isPowerOf2_32(NumSplits) && "Expected power of 2 splits"); |
265 | unsigned Stages = Log2_32(NumSplits); |
266 | for (unsigned s = Stages; s > 0; --s) { |
| |
| 52 | | Loop condition is false. Execution continues on line 278 | |
|
267 | unsigned NumConcatElts = |
268 | cast<FixedVectorType>(Ops[0]->getType())->getNumElements() * 2; |
269 | for (unsigned i = 0; i != 1U << (s - 1); ++i) { |
270 | SmallVector<int, 64> ConcatMask(NumConcatElts); |
271 | std::iota(ConcatMask.begin(), ConcatMask.end(), 0); |
272 | Ops[i] = Builder.CreateShuffleVector(Ops[i*2], Ops[i*2+1], ConcatMask); |
273 | } |
274 | } |
275 | |
276 | |
277 | |
278 | NumElts = cast<FixedVectorType>(OpTy)->getNumElements(); |
| 53 | | 'OpTy' is a 'FixedVectorType' | |
|
279 | if (NumElts == 2) { |
| |
280 | |
281 | Ops[0] = Builder.CreateShuffleVector(Ops[0], Ops[0], ArrayRef<int>{0, 1}); |
282 | } else if (NumElts >= 8) { |
| |
283 | SmallVector<int, 32> ConcatMask(NumElts); |
284 | unsigned SubElts = |
| 57 | | 'SubElts' initialized here | |
|
285 | cast<FixedVectorType>(Ops[0]->getType())->getNumElements(); |
| 56 | | The object is a 'FixedVectorType' | |
|
286 | for (unsigned i = 0; i != SubElts; ++i) |
| 58 | | Assuming 'i' is equal to 'SubElts' | |
|
| 59 | | Loop condition is false. Execution continues on line 288 | |
|
287 | ConcatMask[i] = i; |
288 | for (unsigned i = SubElts; i != NumElts; ++i) |
| 60 | | Loop condition is true. Entering loop body | |
|
289 | ConcatMask[i] = (i % SubElts) + SubElts; |
| |
290 | |
291 | Value *Zero = Constant::getNullValue(Ops[0]->getType()); |
292 | Ops[0] = Builder.CreateShuffleVector(Ops[0], Zero, ConcatMask); |
293 | } |
294 | |
295 | SI->replaceAllUsesWith(Ops[0]); |
296 | SI->eraseFromParent(); |
297 | |
298 | return true; |
299 | } |
300 | |
301 | |
302 | |
303 | static Value *matchAddReduction(const ExtractElementInst &EE) { |
304 | |
305 | auto *Index = dyn_cast<ConstantInt>(EE.getIndexOperand()); |
306 | if (!Index || !Index->isNullValue()) |
307 | return nullptr; |
308 | |
309 | const auto *BO = dyn_cast<BinaryOperator>(EE.getVectorOperand()); |
310 | if (!BO || BO->getOpcode() != Instruction::Add || !BO->hasOneUse()) |
311 | return nullptr; |
312 | |
313 | unsigned NumElems = cast<FixedVectorType>(BO->getType())->getNumElements(); |
314 | |
315 | if (!isPowerOf2_32(NumElems)) |
316 | return nullptr; |
317 | |
318 | const Value *Op = BO; |
319 | unsigned Stages = Log2_32(NumElems); |
320 | for (unsigned i = 0; i != Stages; ++i) { |
321 | const auto *BO = dyn_cast<BinaryOperator>(Op); |
322 | if (!BO || BO->getOpcode() != Instruction::Add) |
323 | return nullptr; |
324 | |
325 | |
326 | |
327 | if (i != 0 && !BO->hasNUses(2)) |
328 | return nullptr; |
329 | |
330 | Value *LHS = BO->getOperand(0); |
331 | Value *RHS = BO->getOperand(1); |
332 | |
333 | auto *Shuffle = dyn_cast<ShuffleVectorInst>(LHS); |
334 | if (Shuffle) { |
335 | Op = RHS; |
336 | } else { |
337 | Shuffle = dyn_cast<ShuffleVectorInst>(RHS); |
338 | Op = LHS; |
339 | } |
340 | |
341 | |
342 | |
343 | if (!Shuffle || Shuffle->getOperand(0) != Op) |
344 | return nullptr; |
345 | |
346 | |
347 | unsigned MaskEnd = 1 << i; |
348 | for (unsigned Index = 0; Index < MaskEnd; ++Index) |
349 | if (Shuffle->getMaskValue(Index) != (int)(MaskEnd + Index)) |
350 | return nullptr; |
351 | } |
352 | |
353 | return const_cast<Value *>(Op); |
354 | } |
355 | |
356 | |
357 | |
358 | |
359 | static bool isReachableFromPHI(PHINode *Phi, BinaryOperator *BO) { |
360 | |
361 | if (!Phi->hasOneUse()) |
362 | return false; |
363 | |
364 | Instruction *U = cast<Instruction>(*Phi->user_begin()); |
365 | if (U == BO) |
366 | return true; |
367 | |
368 | while (U->hasOneUse() && U->getOpcode() == BO->getOpcode()) |
369 | U = cast<Instruction>(*U->user_begin()); |
370 | |
371 | return U == BO; |
372 | } |
373 | |
374 | |
375 | |
376 | |
377 | |
378 | static void collectLeaves(Value *Root, SmallVectorImpl<Instruction *> &Leaves) { |
379 | SmallPtrSet<Value *, 8> Visited; |
380 | SmallVector<Value *, 8> Worklist; |
381 | Worklist.push_back(Root); |
382 | |
383 | while (!Worklist.empty()) { |
384 | Value *V = Worklist.pop_back_val(); |
385 | if (!Visited.insert(V).second) |
386 | continue; |
387 | |
388 | if (auto *PN = dyn_cast<PHINode>(V)) { |
389 | |
390 | |
391 | if (!PN->hasNUses(PN == Root ? 2 : 1)) |
392 | break; |
393 | |
394 | |
395 | append_range(Worklist, PN->incoming_values()); |
396 | |
397 | continue; |
398 | } |
399 | |
400 | if (auto *BO = dyn_cast<BinaryOperator>(V)) { |
401 | if (BO->getOpcode() == Instruction::Add) { |
402 | |
403 | if (BO->hasNUses(BO == Root ? 2 : 1)) { |
404 | append_range(Worklist, BO->operands()); |
405 | continue; |
406 | } |
407 | |
408 | |
409 | |
410 | if (BO->hasNUses(BO == Root ? 3 : 2)) { |
411 | PHINode *PN = nullptr; |
412 | for (auto *U : Root->users()) |
413 | if (auto *P = dyn_cast<PHINode>(U)) |
414 | if (!Visited.count(P)) |
415 | PN = P; |
416 | |
417 | |
418 | |
419 | if (!PN || PN->getNumIncomingValues() != 2) |
420 | continue; |
421 | |
422 | |
423 | if (!isReachableFromPHI(PN, BO)) |
424 | continue; |
425 | |
426 | |
427 | append_range(Worklist, BO->operands()); |
428 | } |
429 | } |
430 | } |
431 | |
432 | |
433 | if (auto *I = dyn_cast<Instruction>(V)) { |
434 | if (!V->hasNUses(I == Root ? 2 : 1)) |
435 | continue; |
436 | |
437 | |
438 | Leaves.push_back(I); |
439 | } |
440 | } |
441 | } |
442 | |
443 | bool X86PartialReduction::runOnFunction(Function &F) { |
444 | if (skipFunction(F)) |
| 1 | Assuming the condition is false | |
|
| |
445 | return false; |
446 | |
447 | auto *TPC = getAnalysisIfAvailable<TargetPassConfig>(); |
448 | if (!TPC) |
| 3 | | Assuming 'TPC' is non-null | |
|
| |
449 | return false; |
450 | |
451 | auto &TM = TPC->getTM<X86TargetMachine>(); |
452 | ST = TM.getSubtargetImpl(F); |
453 | |
454 | DL = &F.getParent()->getDataLayout(); |
455 | |
456 | bool MadeChange = false; |
457 | for (auto &BB : F) { |
458 | for (auto &I : BB) { |
459 | auto *EE = dyn_cast<ExtractElementInst>(&I); |
| 5 | | Assuming the object is a 'ExtractElementInst' | |
|
460 | if (!EE) |
| |
461 | continue; |
462 | |
463 | |
464 | |
465 | Value *Root = matchAddReduction(*EE); |
466 | if (!Root) |
| |
467 | continue; |
468 | |
469 | SmallVector<Instruction *, 8> Leaves; |
470 | collectLeaves(Root, Leaves); |
471 | |
472 | for (Instruction *I : Leaves) { |
| 8 | | Assuming '__begin3' is not equal to '__end3' | |
|
473 | if (tryMAddReplacement(I)) { |
| |
474 | MadeChange = true; |
475 | continue; |
476 | } |
477 | |
478 | |
479 | |
480 | if (I != Root && trySADReplacement(I)) |
| 10 | | Assuming 'I' is not equal to 'Root' | |
|
| 11 | | Calling 'X86PartialReduction::trySADReplacement' | |
|
481 | MadeChange = true; |
482 | } |
483 | } |
484 | } |
485 | |
486 | return MadeChange; |
487 | } |
1 | |
2 | |
3 | |
4 | |
5 | |
6 | |
7 | |
8 | |
9 | |
10 | |
11 | |
12 | |
13 | #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H |
14 | #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H |
15 | |
16 | #include "X86FrameLowering.h" |
17 | #include "X86ISelLowering.h" |
18 | #include "X86InstrInfo.h" |
19 | #include "X86SelectionDAGInfo.h" |
20 | #include "llvm/ADT/Triple.h" |
21 | #include "llvm/CodeGen/TargetSubtargetInfo.h" |
22 | #include "llvm/IR/CallingConv.h" |
23 | #include <climits> |
24 | #include <memory> |
25 | |
26 | #define GET_SUBTARGETINFO_HEADER |
27 | #include "X86GenSubtargetInfo.inc" |
28 | |
29 | namespace llvm { |
30 | |
31 | class CallLowering; |
32 | class GlobalValue; |
33 | class InstructionSelector; |
34 | class LegalizerInfo; |
35 | class RegisterBankInfo; |
36 | class StringRef; |
37 | class TargetMachine; |
38 | |
39 | |
40 | |
41 | namespace PICStyles { |
42 | |
43 | enum class Style { |
44 | StubPIC, |
45 | GOT, |
46 | RIPRel, |
47 | None |
48 | }; |
49 | |
50 | } |
51 | |
52 | class X86Subtarget final : public X86GenSubtargetInfo { |
53 | |
54 | |
55 | enum X86ProcFamilyEnum { |
56 | Others, |
57 | IntelAtom, |
58 | IntelSLM |
59 | }; |
60 | |
61 | enum X86SSEEnum { |
62 | NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F |
63 | }; |
64 | |
65 | enum X863DNowEnum { |
66 | NoThreeDNow, MMX, ThreeDNow, ThreeDNowA |
67 | }; |
68 | |
69 | |
70 | X86ProcFamilyEnum X86ProcFamily = Others; |
71 | |
72 | |
73 | PICStyles::Style PICStyle; |
74 | |
75 | const TargetMachine &TM; |
76 | |
77 | |
78 | X86SSEEnum X86SSELevel = NoSSE; |
79 | |
80 | |
81 | X863DNowEnum X863DNowLevel = NoThreeDNow; |
82 | |
83 | |
84 | bool HasX87 = false; |
85 | |
86 | |
87 | bool HasCmpxchg8b = false; |
88 | |
89 | |
90 | |
91 | bool HasNOPL = false; |
92 | |
93 | |
94 | |
95 | bool HasCMov = false; |
96 | |
97 | |
98 | bool HasX86_64 = false; |
99 | |
100 | |
101 | bool HasPOPCNT = false; |
102 | |
103 | |
104 | bool HasSSE4A = false; |
105 | |
106 | |
107 | bool HasAES = false; |
108 | bool HasVAES = false; |
109 | |
110 | |
111 | bool HasFXSR = false; |
112 | |
113 | |
114 | bool HasXSAVE = false; |
115 | |
116 | |
117 | bool HasXSAVEOPT = false; |
118 | |
119 | |
120 | bool HasXSAVEC = false; |
121 | |
122 | |
123 | bool HasXSAVES = false; |
124 | |
125 | |
126 | bool HasPCLMUL = false; |
127 | bool HasVPCLMULQDQ = false; |
128 | |
129 | |
130 | bool HasGFNI = false; |
131 | |
132 | |
133 | bool HasFMA = false; |
134 | |
135 | |
136 | bool HasFMA4 = false; |
137 | |
138 | |
139 | bool HasXOP = false; |
140 | |
141 | |
142 | bool HasTBM = false; |
143 | |
144 | |
145 | bool HasLWP = false; |
146 | |
147 | |
148 | bool HasMOVBE = false; |
149 | |
150 | |
151 | bool HasRDRAND = false; |
152 | |
153 | |
154 | bool HasF16C = false; |
155 | |
156 | |
157 | bool HasFSGSBase = false; |
158 | |
159 | |
160 | bool HasLZCNT = false; |
161 | |
162 | |
163 | bool HasBMI = false; |
164 | |
165 | |
166 | bool HasBMI2 = false; |
167 | |
168 | |
169 | bool HasVBMI = false; |
170 | |
171 | |
172 | bool HasVBMI2 = false; |
173 | |
174 | |
175 | bool HasIFMA = false; |
176 | |
177 | |
178 | bool HasRTM = false; |
179 | |
180 | |
181 | bool HasADX = false; |
182 | |
183 | |
184 | bool HasSHA = false; |
185 | |
186 | |
187 | bool HasPRFCHW = false; |
188 | |
189 | |
190 | bool HasRDSEED = false; |
191 | |
192 | |
193 | bool HasLAHFSAHF64 = false; |
194 | |
195 | |
196 | bool HasMWAITX = false; |
197 | |
198 | |
199 | bool HasCLZERO = false; |
200 | |
201 | |
202 | bool HasCLDEMOTE = false; |
203 | |
204 | |
205 | bool HasMOVDIRI = false; |
206 | |
207 | |
208 | bool HasMOVDIR64B = false; |
209 | |
210 | |
211 | bool HasPTWRITE = false; |
212 | |
213 | |
214 | bool HasPREFETCHWT1 = false; |
215 | |
216 | |
217 | bool IsSHLDSlow = false; |
218 | |
219 | |
220 | |
221 | bool IsPMULLDSlow = false; |
222 | |
223 | |
224 | bool IsPMADDWDSlow = false; |
225 | |
226 | |
227 | bool IsUAMem16Slow = false; |
228 | |
229 | |
230 | bool IsUAMem32Slow = false; |
231 | |
232 | |
233 | |
234 | bool HasSSEUnalignedMem = false; |
235 | |
236 | |
237 | |
238 | bool HasCmpxchg16b = false; |
239 | |
240 | |
241 | |
242 | bool UseLeaForSP = false; |
243 | |
244 | |
245 | bool HasPOPCNTFalseDeps = false; |
246 | |
247 | |
248 | bool HasLZCNTFalseDeps = false; |
249 | |
250 | |
251 | |
252 | bool HasFastVariableCrossLaneShuffle = false; |
253 | |
254 | |
255 | |
256 | bool HasFastVariablePerLaneShuffle = false; |
257 | |
258 | |
259 | |
260 | bool InsertVZEROUPPER = false; |
261 | |
262 | |
263 | |
264 | bool HasFast7ByteNOP = false; |
265 | |
266 | |
267 | |
268 | bool HasFast11ByteNOP = false; |
269 | |
270 | |
271 | |
272 | bool HasFast15ByteNOP = false; |
273 | |
274 | |
275 | |
276 | bool HasFastGather = false; |
277 | |
278 | |
279 | |
280 | bool HasFastScalarFSQRT = false; |
281 | |
282 | |
283 | |
284 | bool HasFastVectorFSQRT = false; |
285 | |
286 | |
287 | |
288 | bool HasSlowDivide32 = false; |
289 | |
290 | |
291 | |
292 | bool HasSlowDivide64 = false; |
293 | |
294 | |
295 | bool HasFastLZCNT = false; |
296 | |
297 | |
298 | bool HasFastSHLDRotate = false; |
299 | |
300 | |
301 | bool HasMacroFusion = false; |
302 | |
303 | |
304 | bool HasBranchFusion = false; |
305 | |
306 | |
307 | bool HasERMSB = false; |
308 | |
309 | |
310 | bool HasFSRM = false; |
311 | |
312 | |
313 | |
314 | bool PadShortFunctions = false; |
315 | |
316 | |
317 | |
318 | bool SlowTwoMemOps = false; |
319 | |
320 | |
321 | |
322 | bool LEAUsesAG = false; |
323 | |
324 | |
325 | bool SlowLEA = false; |
326 | |
327 | |
328 | |
329 | |
330 | bool Slow3OpsLEA = false; |
331 | |
332 | |
333 | bool SlowIncDec = false; |
334 | |
335 | |
336 | bool HasPFI = false; |
337 | |
338 | |
339 | bool HasERI = false; |
340 | |
341 | |
342 | bool HasCDI = false; |
343 | |
344 | |
345 | bool HasVPOPCNTDQ = false; |
346 | |
347 | |
348 | bool HasDQI = false; |
349 | |
350 | |
351 | bool HasBWI = false; |
352 | |
353 | |
354 | bool HasVLX = false; |
355 | |
356 | |
357 | bool HasPKU = false; |
358 | |
359 | |
360 | bool HasVNNI = false; |
361 | |
362 | |
363 | bool HasAVXVNNI = false; |
364 | |
365 | |
366 | bool HasBF16 = false; |
367 | |
368 | |
369 | bool HasENQCMD = false; |
370 | |
371 | |
372 | bool HasBITALG = false; |
373 | |
374 | |
375 | bool HasVP2INTERSECT = false; |
376 | |
377 | |
378 | |
379 | bool HasSHSTK = false; |
380 | |
381 | |
382 | bool HasINVPCID = false; |
383 | |
384 | |
385 | bool HasSGX = false; |
386 | |
387 | |
388 | bool HasCLFLUSHOPT = false; |
389 | |
390 | |
391 | bool HasCLWB = false; |
392 | |
393 | |
394 | bool HasWBNOINVD = false; |
395 | |
396 | |
397 | bool HasRDPID = false; |
398 | |
399 | |
400 | bool HasWAITPKG = false; |
401 | |
402 | |
403 | bool HasPCONFIG = false; |
404 | |
405 | |
406 | bool HasKL = false; |
407 | |
408 | |
409 | bool HasWIDEKL = false; |
410 | |
411 | |
412 | bool HasHRESET = false; |
413 | |
414 | |
415 | bool HasSERIALIZE = false; |
416 | |
417 | |
418 | bool HasTSXLDTRK = false; |
419 | |
420 | |
421 | bool HasAMXTILE = false; |
422 | bool HasAMXBF16 = false; |
423 | bool HasAMXINT8 = false; |
424 | |
425 | |
426 | bool HasUINTR = false; |
427 | |
428 | |
429 | bool HasFastBEXTR = false; |
430 | |
431 | |
432 | bool HasFastHorizontalOps = false; |
433 | |
434 | |
435 | bool HasFastScalarShiftMasks = false; |
436 | |
437 | |
438 | bool HasFastVectorShiftMasks = false; |
439 | |
440 | |
441 | bool HasFastMOVBE = false; |
442 | |
443 | |
444 | |
445 | bool UseRetpolineIndirectCalls = false; |
446 | |
447 | |
448 | |
449 | bool UseRetpolineIndirectBranches = false; |
450 | |
451 | |
452 | |
453 | bool DeprecatedUseRetpoline = false; |
454 | |
455 | |
456 | |
457 | bool UseRetpolineExternalThunk = false; |
458 | |
459 | |
460 | |
461 | |
462 | |
463 | bool UseLVIControlFlowIntegrity = false; |
464 | |
465 | |
466 | bool UseSpeculativeExecutionSideEffectSuppression = false; |
467 | |
468 | |
469 | |
470 | bool UseLVILoadHardening = false; |
471 | |
472 | |
473 | bool UseSoftFloat = false; |
474 | |
475 | |
476 | bool UseAA = false; |
477 | |
478 | |
479 | |
480 | Align stackAlignment = Align(4); |
481 | |
482 | Align TileConfigAlignment = Align(4); |
483 | |
484 | |
485 | bool SaveArgs = false; |
486 | |
487 | |
488 | |
489 | |
490 | unsigned MaxInlineSizeThreshold = 128; |
491 | |
492 | |
493 | bool Prefer128Bit = false; |
494 | |
495 | |
496 | bool Prefer256Bit = false; |
497 | |
498 | |
499 | bool PreferMaskRegisters = false; |
500 | |
501 | |
502 | bool UseGLMDivSqrtCosts = false; |
503 | |
504 | |
505 | Triple TargetTriple; |
506 | |
507 | |
508 | std::unique_ptr<CallLowering> CallLoweringInfo; |
509 | std::unique_ptr<LegalizerInfo> Legalizer; |
510 | std::unique_ptr<RegisterBankInfo> RegBankInfo; |
511 | std::unique_ptr<InstructionSelector> InstSelector; |
512 | |
513 | private: |
514 | |
515 | MaybeAlign StackAlignOverride; |
516 | |
517 | |
518 | unsigned PreferVectorWidthOverride; |
519 | |
520 | |
521 | |
522 | unsigned PreferVectorWidth = UINT32_MAX; |
523 | |
524 | |
525 | unsigned RequiredVectorWidth; |
526 | |
527 | |
528 | bool In64BitMode = false; |
529 | |
530 | |
531 | bool In32BitMode = false; |
532 | |
533 | |
534 | bool In16BitMode = false; |
535 | |
536 | X86SelectionDAGInfo TSInfo; |
537 | |
538 | |
539 | X86InstrInfo InstrInfo; |
540 | X86TargetLowering TLInfo; |
541 | X86FrameLowering FrameLowering; |
542 | |
543 | public: |
544 | |
545 | |
546 | |
547 | X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, |
548 | const X86TargetMachine &TM, MaybeAlign StackAlignOverride, |
549 | unsigned PreferVectorWidthOverride, |
550 | unsigned RequiredVectorWidth); |
551 | |
552 | const X86TargetLowering *getTargetLowering() const override { |
553 | return &TLInfo; |
554 | } |
555 | |
556 | const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; } |
557 | |
558 | const X86FrameLowering *getFrameLowering() const override { |
559 | return &FrameLowering; |
560 | } |
561 | |
562 | const X86SelectionDAGInfo *getSelectionDAGInfo() const override { |
563 | return &TSInfo; |
564 | } |
565 | |
566 | const X86RegisterInfo *getRegisterInfo() const override { |
567 | return &getInstrInfo()->getRegisterInfo(); |
568 | } |
569 | |
570 | bool getSaveArgs() const { return SaveArgs; } |
571 | |
572 | unsigned getTileConfigSize() const { return 64; } |
573 | Align getTileConfigAlignment() const { return TileConfigAlignment; } |
574 | |
575 | |
576 | |
577 | |
578 | Align getStackAlignment() const { return stackAlignment; } |
579 | |
580 | |
581 | |
582 | unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; } |
583 | |
584 | |
585 | |
586 | void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); |
587 | |
588 | |
589 | const CallLowering *getCallLowering() const override; |
590 | InstructionSelector *getInstructionSelector() const override; |
591 | const LegalizerInfo *getLegalizerInfo() const override; |
592 | const RegisterBankInfo *getRegBankInfo() const override; |
593 | |
594 | private: |
595 | |
596 | |
597 | X86Subtarget &initializeSubtargetDependencies(StringRef CPU, |
598 | StringRef TuneCPU, |
599 | StringRef FS); |
600 | void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); |
601 | |
602 | public: |
603 | |
604 | bool is64Bit() const { |
605 | return In64BitMode; |
606 | } |
607 | |
608 | bool is32Bit() const { |
609 | return In32BitMode; |
610 | } |
611 | |
612 | bool is16Bit() const { |
613 | return In16BitMode; |
614 | } |
615 | |
616 | |
617 | bool isTarget64BitILP32() const { |
618 | return In64BitMode && (TargetTriple.isX32() || TargetTriple.isOSNaCl()); |
619 | } |
620 | |
621 | |
622 | bool isTarget64BitLP64() const { |
623 | return In64BitMode && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl()); |
624 | } |
625 | |
626 | PICStyles::Style getPICStyle() const { return PICStyle; } |
627 | void setPICStyle(PICStyles::Style Style) { PICStyle = Style; } |
628 | |
629 | bool hasX87() const { return HasX87; } |
630 | bool hasCmpxchg8b() const { return HasCmpxchg8b; } |
631 | bool hasNOPL() const { return HasNOPL; } |
632 | |
633 | |
634 | bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); } |
635 | bool hasSSE1() const { return X86SSELevel >= SSE1; } |
636 | bool hasSSE2() const { return X86SSELevel >= SSE2; } |
| 13 | | Returning the value 1, which participates in a condition later | |
|
637 | bool hasSSE3() const { return X86SSELevel >= SSE3; } |
638 | bool hasSSSE3() const { return X86SSELevel >= SSSE3; } |
639 | bool hasSSE41() const { return X86SSELevel >= SSE41; } |
640 | bool hasSSE42() const { return X86SSELevel >= SSE42; } |
641 | bool hasAVX() const { return X86SSELevel >= AVX; } |
642 | bool hasAVX2() const { return X86SSELevel >= AVX2; } |
643 | bool hasAVX512() const { return X86SSELevel >= AVX512F; } |
644 | bool hasInt256() const { return hasAVX2(); } |
645 | bool hasSSE4A() const { return HasSSE4A; } |
646 | bool hasMMX() const { return X863DNowLevel >= MMX; } |
647 | bool has3DNow() const { return X863DNowLevel >= ThreeDNow; } |
648 | bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; } |
649 | bool hasPOPCNT() const { return HasPOPCNT; } |
650 | bool hasAES() const { return HasAES; } |
651 | bool hasVAES() const { return HasVAES; } |
652 | bool hasFXSR() const { return HasFXSR; } |
653 | bool hasXSAVE() const { return HasXSAVE; } |
654 | bool hasXSAVEOPT() const { return HasXSAVEOPT; } |
655 | bool hasXSAVEC() const { return HasXSAVEC; } |
656 | bool hasXSAVES() const { return HasXSAVES; } |
657 | bool hasPCLMUL() const { return HasPCLMUL; } |
658 | bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; } |
659 | bool hasGFNI() const { return HasGFNI; } |
660 | |
661 | |
662 | bool hasFMA() const { return HasFMA; } |
663 | bool hasFMA4() const { return HasFMA4; } |
664 | bool hasAnyFMA() const { return hasFMA() || hasFMA4(); } |
665 | bool hasXOP() const { return HasXOP; } |
666 | bool hasTBM() const { return HasTBM; } |
667 | bool hasLWP() const { return HasLWP; } |
668 | bool hasMOVBE() const { return HasMOVBE; } |
669 | bool hasRDRAND() const { return HasRDRAND; } |
670 | bool hasF16C() const { return HasF16C; } |
671 | bool hasFSGSBase() const { return HasFSGSBase; } |
672 | bool hasLZCNT() const { return HasLZCNT; } |
673 | bool hasBMI() const { return HasBMI; } |
674 | bool hasBMI2() const { return HasBMI2; } |
675 | bool hasVBMI() const { return HasVBMI; } |
676 | bool hasVBMI2() const { return HasVBMI2; } |
677 | bool hasIFMA() const { return HasIFMA; } |
678 | bool hasRTM() const { return HasRTM; } |
679 | bool hasADX() const { return HasADX; } |
680 | bool hasSHA() const { return HasSHA; } |
681 | bool hasPRFCHW() const { return HasPRFCHW; } |
682 | bool hasPREFETCHWT1() const { return HasPREFETCHWT1; } |
683 | bool hasPrefetchW() const { |
684 | |
685 | |
686 | |
687 | |
688 | return has3DNow() || hasPRFCHW() || hasPREFETCHWT1(); |
689 | } |
690 | bool hasSSEPrefetch() const { |
691 | |
692 | |
693 | |
694 | return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1(); |
695 | } |
696 | bool hasRDSEED() const { return HasRDSEED; } |
697 | bool hasLAHFSAHF() const { return HasLAHFSAHF64 || !is64Bit(); } |
698 | bool hasMWAITX() const { return HasMWAITX; } |
699 | bool hasCLZERO() const { return HasCLZERO; } |
700 | bool hasCLDEMOTE() const { return HasCLDEMOTE; } |
701 | bool hasMOVDIRI() const { return HasMOVDIRI; } |
702 | bool hasMOVDIR64B() const { return HasMOVDIR64B; } |
703 | bool hasPTWRITE() const { return HasPTWRITE; } |
704 | bool isSHLDSlow() const { return IsSHLDSlow; } |
705 | bool isPMULLDSlow() const { return IsPMULLDSlow; } |
706 | bool isPMADDWDSlow() const { return IsPMADDWDSlow; } |
707 | bool isUnalignedMem16Slow() const { return IsUAMem16Slow; } |
708 | bool isUnalignedMem32Slow() const { return IsUAMem32Slow; } |
709 | bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; } |
710 | bool hasCmpxchg16b() const { return HasCmpxchg16b && is64Bit(); } |
711 | bool useLeaForSP() const { return UseLeaForSP; } |
712 | bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; } |
713 | bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; } |
714 | bool hasFastVariableCrossLaneShuffle() const { |
715 | return HasFastVariableCrossLaneShuffle; |
716 | } |
717 | bool hasFastVariablePerLaneShuffle() const { |
718 | return HasFastVariablePerLaneShuffle; |
719 | } |
720 | bool insertVZEROUPPER() const { return InsertVZEROUPPER; } |
721 | bool hasFastGather() const { return HasFastGather; } |
722 | bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; } |
723 | bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; } |
724 | bool hasFastLZCNT() const { return HasFastLZCNT; } |
725 | bool hasFastSHLDRotate() const { return HasFastSHLDRotate; } |
726 | bool hasFastBEXTR() const { return HasFastBEXTR; } |
727 | bool hasFastHorizontalOps() const { return HasFastHorizontalOps; } |
728 | bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; } |
729 | bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; } |
730 | bool hasFastMOVBE() const { return HasFastMOVBE; } |
731 | bool hasMacroFusion() const { return HasMacroFusion; } |
732 | bool hasBranchFusion() const { return HasBranchFusion; } |
733 | bool hasERMSB() const { return HasERMSB; } |
734 | bool hasFSRM() const { return HasFSRM; } |
735 | bool hasSlowDivide32() const { return HasSlowDivide32; } |
736 | bool hasSlowDivide64() const { return HasSlowDivide64; } |
737 | bool padShortFunctions() const { return PadShortFunctions; } |
738 | bool slowTwoMemOps() const { return SlowTwoMemOps; } |
739 | bool LEAusesAG() const { return LEAUsesAG; } |
740 | bool slowLEA() const { return SlowLEA; } |
741 | bool slow3OpsLEA() const { return Slow3OpsLEA; } |
742 | bool slowIncDec() const { return SlowIncDec; } |
743 | bool hasCDI() const { return HasCDI; } |
744 | bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; } |
745 | bool hasPFI() const { return HasPFI; } |
746 | bool hasERI() const { return HasERI; } |
747 | bool hasDQI() const { return HasDQI; } |
748 | bool hasBWI() const { return HasBWI; } |
749 | bool hasVLX() const { return HasVLX; } |
750 | bool hasPKU() const { return HasPKU; } |
751 | bool hasVNNI() const { return HasVNNI; } |
752 | bool hasBF16() const { return HasBF16; } |
753 | bool hasVP2INTERSECT() const { return HasVP2INTERSECT; } |
754 | bool hasBITALG() const { return HasBITALG; } |
755 | bool hasSHSTK() const { return HasSHSTK; } |
756 | bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; } |
757 | bool hasCLWB() const { return HasCLWB; } |
758 | bool hasWBNOINVD() const { return HasWBNOINVD; } |
759 | bool hasRDPID() const { return HasRDPID; } |
760 | bool hasWAITPKG() const { return HasWAITPKG; } |
761 | bool hasPCONFIG() const { return HasPCONFIG; } |
762 | bool hasSGX() const { return HasSGX; } |
763 | bool hasINVPCID() const { return HasINVPCID; } |
764 | bool hasENQCMD() const { return HasENQCMD; } |
765 | bool hasKL() const { return HasKL; } |
766 | bool hasWIDEKL() const { return HasWIDEKL; } |
767 | bool hasHRESET() const { return HasHRESET; } |
768 | bool hasSERIALIZE() const { return HasSERIALIZE; } |
769 | bool hasTSXLDTRK() const { return HasTSXLDTRK; } |
770 | bool hasUINTR() const { return HasUINTR; } |
771 | bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; } |
772 | bool useRetpolineIndirectBranches() const { |
773 | return UseRetpolineIndirectBranches; |
774 | } |
775 | bool hasAVXVNNI() const { return HasAVXVNNI; } |
776 | bool hasAMXTILE() const { return HasAMXTILE; } |
777 | bool hasAMXBF16() const { return HasAMXBF16; } |
778 | bool hasAMXINT8() const { return HasAMXINT8; } |
779 | bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; } |
780 | |
781 | |
782 | |
783 | |
784 | bool useIndirectThunkCalls() const { |
785 | return useRetpolineIndirectCalls() || useLVIControlFlowIntegrity(); |
786 | } |
787 | bool useIndirectThunkBranches() const { |
788 | return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity(); |
789 | } |
790 | |
791 | bool preferMaskRegisters() const { return PreferMaskRegisters; } |
792 | bool useGLMDivSqrtCosts() const { return UseGLMDivSqrtCosts; } |
793 | bool useLVIControlFlowIntegrity() const { return UseLVIControlFlowIntegrity; } |
794 | bool useLVILoadHardening() const { return UseLVILoadHardening; } |
795 | bool useSpeculativeExecutionSideEffectSuppression() const { |
796 | return UseSpeculativeExecutionSideEffectSuppression; |
797 | } |
798 | |
799 | unsigned getPreferVectorWidth() const { return PreferVectorWidth; } |
800 | unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; } |
801 | |
802 | |
803 | |
804 | |
805 | |
806 | bool canExtendTo512DQ() const { |
807 | return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512); |
808 | } |
809 | bool canExtendTo512BW() const { |
810 | return hasBWI() && canExtendTo512DQ(); |
811 | } |
812 | |
813 | |
814 | |
815 | bool useAVX512Regs() const { |
816 | return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256); |
817 | } |
818 | |
819 | bool useBWIRegs() const { |
820 | return hasBWI() && useAVX512Regs(); |
821 | } |
822 | |
823 | bool isXRaySupported() const override { return is64Bit(); } |
824 | |
825 | |
826 | bool isAtom() const { return X86ProcFamily == IntelAtom; } |
827 | bool isSLM() const { return X86ProcFamily == IntelSLM; } |
828 | bool useSoftFloat() const { return UseSoftFloat; } |
829 | bool useAA() const override { return UseAA; } |
830 | |
831 | |
832 | |
833 | |
834 | bool hasMFence() const { return hasSSE2() || is64Bit(); } |
835 | |
836 | const Triple &getTargetTriple() const { return TargetTriple; } |
837 | |
838 | bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } |
839 | bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); } |
840 | bool isTargetOpenBSD() const { return TargetTriple.isOSOpenBSD(); } |
841 | bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); } |
842 | bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); } |
843 | bool isTargetPS4() const { return TargetTriple.isPS4CPU(); } |
844 | |
845 | bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } |
846 | bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } |
847 | bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } |
848 | |
849 | bool isTargetLinux() const { return TargetTriple.isOSLinux(); } |
850 | bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); } |
851 | bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); } |
852 | bool isTargetAndroid() const { return TargetTriple.isAndroid(); } |
853 | bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } |
854 | bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); } |
855 | bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); } |
856 | bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); } |
857 | bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); } |
858 | |
859 | bool isTargetWindowsMSVC() const { |
860 | return TargetTriple.isWindowsMSVCEnvironment(); |
861 | } |
862 | |
863 | bool isTargetWindowsCoreCLR() const { |
864 | return TargetTriple.isWindowsCoreCLREnvironment(); |
865 | } |
866 | |
867 | bool isTargetWindowsCygwin() const { |
868 | return TargetTriple.isWindowsCygwinEnvironment(); |
869 | } |
870 | |
871 | bool isTargetWindowsGNU() const { |
872 | return TargetTriple.isWindowsGNUEnvironment(); |
873 | } |
874 | |
875 | bool isTargetWindowsItanium() const { |
876 | return TargetTriple.isWindowsItaniumEnvironment(); |
877 | } |
878 | |
879 | bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); } |
880 | |
881 | bool isOSWindows() const { return TargetTriple.isOSWindows(); } |
882 | |
883 | bool isTargetWin64() const { return In64BitMode && isOSWindows(); } |
884 | |
885 | bool isTargetWin32() const { return !In64BitMode && isOSWindows(); } |
886 | |
887 | bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; } |
888 | bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; } |
889 | |
890 | bool isPICStyleStubPIC() const { |
891 | return PICStyle == PICStyles::Style::StubPIC; |
892 | } |
893 | |
894 | bool isPositionIndependent() const; |
895 | |
896 | bool isCallingConvWin64(CallingConv::ID CC) const { |
897 | switch (CC) { |
898 | |
899 | case CallingConv::C: |
900 | case CallingConv::Fast: |
901 | case CallingConv::Tail: |
902 | case CallingConv::Swift: |
903 | case CallingConv::SwiftTail: |
904 | case CallingConv::X86_FastCall: |
905 | case CallingConv::X86_StdCall: |
906 | case CallingConv::X86_ThisCall: |
907 | case CallingConv::X86_VectorCall: |
908 | case CallingConv::Intel_OCL_BI: |
909 | return isTargetWin64(); |
910 | |
911 | case CallingConv::Win64: |
912 | return true; |
913 | |
914 | case CallingConv::X86_64_SysV: |
915 | return false; |
916 | |
917 | default: |
918 | return false; |
919 | } |
920 | } |
921 | |
922 | |
923 | |
924 | unsigned char classifyLocalReference(const GlobalValue *GV) const; |
925 | |
926 | unsigned char classifyGlobalReference(const GlobalValue *GV, |
927 | const Module &M) const; |
928 | unsigned char classifyGlobalReference(const GlobalValue *GV) const; |
929 | |
930 | |
931 | unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, |
932 | const Module &M) const; |
933 | unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const; |
934 | |
935 | |
936 | |
937 | unsigned char classifyBlockAddressReference() const; |
938 | |
939 | |
940 | bool isLegalToCallImmediateAddr() const; |
941 | |
942 | |
943 | |
944 | bool enableIndirectBrExpand() const override { |
945 | return useIndirectThunkBranches(); |
946 | } |
947 | |
948 | |
949 | bool enableMachineScheduler() const override { return true; } |
950 | |
951 | bool enableEarlyIfConversion() const override; |
952 | |
953 | void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>> |
954 | &Mutations) const override; |
955 | |
956 | AntiDepBreakMode getAntiDepBreakMode() const override { |
957 | return TargetSubtargetInfo::ANTIDEP_CRITICAL; |
958 | } |
959 | |
960 | bool enableAdvancedRASplitCost() const override { return false; } |
961 | }; |
962 | |
963 | } |
964 | |
965 | #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H |