File: | src/gnu/usr.bin/clang/libLLVM/../../../llvm/llvm/lib/CodeGen/InlineSpiller.cpp |
Warning: | line 492, column 55 The left operand of '==' is a garbage value |
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1 | //===- InlineSpiller.cpp - Insert spills and restores inline --------------===// | |||
2 | // | |||
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. | |||
4 | // See https://llvm.org/LICENSE.txt for license information. | |||
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | |||
6 | // | |||
7 | //===----------------------------------------------------------------------===// | |||
8 | // | |||
9 | // The inline spiller modifies the machine function directly instead of | |||
10 | // inserting spills and restores in VirtRegMap. | |||
11 | // | |||
12 | //===----------------------------------------------------------------------===// | |||
13 | ||||
14 | #include "SplitKit.h" | |||
15 | #include "llvm/ADT/ArrayRef.h" | |||
16 | #include "llvm/ADT/DenseMap.h" | |||
17 | #include "llvm/ADT/MapVector.h" | |||
18 | #include "llvm/ADT/None.h" | |||
19 | #include "llvm/ADT/STLExtras.h" | |||
20 | #include "llvm/ADT/SetVector.h" | |||
21 | #include "llvm/ADT/SmallPtrSet.h" | |||
22 | #include "llvm/ADT/SmallVector.h" | |||
23 | #include "llvm/ADT/Statistic.h" | |||
24 | #include "llvm/Analysis/AliasAnalysis.h" | |||
25 | #include "llvm/CodeGen/LiveInterval.h" | |||
26 | #include "llvm/CodeGen/LiveIntervalCalc.h" | |||
27 | #include "llvm/CodeGen/LiveIntervals.h" | |||
28 | #include "llvm/CodeGen/LiveRangeEdit.h" | |||
29 | #include "llvm/CodeGen/LiveStacks.h" | |||
30 | #include "llvm/CodeGen/MachineBasicBlock.h" | |||
31 | #include "llvm/CodeGen/MachineBlockFrequencyInfo.h" | |||
32 | #include "llvm/CodeGen/MachineDominators.h" | |||
33 | #include "llvm/CodeGen/MachineFunction.h" | |||
34 | #include "llvm/CodeGen/MachineFunctionPass.h" | |||
35 | #include "llvm/CodeGen/MachineInstr.h" | |||
36 | #include "llvm/CodeGen/MachineInstrBuilder.h" | |||
37 | #include "llvm/CodeGen/MachineInstrBundle.h" | |||
38 | #include "llvm/CodeGen/MachineLoopInfo.h" | |||
39 | #include "llvm/CodeGen/MachineOperand.h" | |||
40 | #include "llvm/CodeGen/MachineRegisterInfo.h" | |||
41 | #include "llvm/CodeGen/SlotIndexes.h" | |||
42 | #include "llvm/CodeGen/Spiller.h" | |||
43 | #include "llvm/CodeGen/StackMaps.h" | |||
44 | #include "llvm/CodeGen/TargetInstrInfo.h" | |||
45 | #include "llvm/CodeGen/TargetOpcodes.h" | |||
46 | #include "llvm/CodeGen/TargetRegisterInfo.h" | |||
47 | #include "llvm/CodeGen/TargetSubtargetInfo.h" | |||
48 | #include "llvm/CodeGen/VirtRegMap.h" | |||
49 | #include "llvm/Config/llvm-config.h" | |||
50 | #include "llvm/Support/BlockFrequency.h" | |||
51 | #include "llvm/Support/BranchProbability.h" | |||
52 | #include "llvm/Support/CommandLine.h" | |||
53 | #include "llvm/Support/Compiler.h" | |||
54 | #include "llvm/Support/Debug.h" | |||
55 | #include "llvm/Support/ErrorHandling.h" | |||
56 | #include "llvm/Support/raw_ostream.h" | |||
57 | #include <cassert> | |||
58 | #include <iterator> | |||
59 | #include <tuple> | |||
60 | #include <utility> | |||
61 | #include <vector> | |||
62 | ||||
63 | using namespace llvm; | |||
64 | ||||
65 | #define DEBUG_TYPE"regalloc" "regalloc" | |||
66 | ||||
67 | STATISTIC(NumSpilledRanges, "Number of spilled live ranges")static llvm::Statistic NumSpilledRanges = {"regalloc", "NumSpilledRanges" , "Number of spilled live ranges"}; | |||
68 | STATISTIC(NumSnippets, "Number of spilled snippets")static llvm::Statistic NumSnippets = {"regalloc", "NumSnippets" , "Number of spilled snippets"}; | |||
69 | STATISTIC(NumSpills, "Number of spills inserted")static llvm::Statistic NumSpills = {"regalloc", "NumSpills", "Number of spills inserted" }; | |||
70 | STATISTIC(NumSpillsRemoved, "Number of spills removed")static llvm::Statistic NumSpillsRemoved = {"regalloc", "NumSpillsRemoved" , "Number of spills removed"}; | |||
71 | STATISTIC(NumReloads, "Number of reloads inserted")static llvm::Statistic NumReloads = {"regalloc", "NumReloads" , "Number of reloads inserted"}; | |||
72 | STATISTIC(NumReloadsRemoved, "Number of reloads removed")static llvm::Statistic NumReloadsRemoved = {"regalloc", "NumReloadsRemoved" , "Number of reloads removed"}; | |||
73 | STATISTIC(NumFolded, "Number of folded stack accesses")static llvm::Statistic NumFolded = {"regalloc", "NumFolded", "Number of folded stack accesses" }; | |||
74 | STATISTIC(NumFoldedLoads, "Number of folded loads")static llvm::Statistic NumFoldedLoads = {"regalloc", "NumFoldedLoads" , "Number of folded loads"}; | |||
75 | STATISTIC(NumRemats, "Number of rematerialized defs for spilling")static llvm::Statistic NumRemats = {"regalloc", "NumRemats", "Number of rematerialized defs for spilling" }; | |||
76 | ||||
77 | static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden, | |||
78 | cl::desc("Disable inline spill hoisting")); | |||
79 | static cl::opt<bool> | |||
80 | RestrictStatepointRemat("restrict-statepoint-remat", | |||
81 | cl::init(false), cl::Hidden, | |||
82 | cl::desc("Restrict remat for statepoint operands")); | |||
83 | ||||
84 | namespace { | |||
85 | ||||
86 | class HoistSpillHelper : private LiveRangeEdit::Delegate { | |||
87 | MachineFunction &MF; | |||
88 | LiveIntervals &LIS; | |||
89 | LiveStacks &LSS; | |||
90 | AliasAnalysis *AA; | |||
91 | MachineDominatorTree &MDT; | |||
92 | MachineLoopInfo &Loops; | |||
93 | VirtRegMap &VRM; | |||
94 | MachineRegisterInfo &MRI; | |||
95 | const TargetInstrInfo &TII; | |||
96 | const TargetRegisterInfo &TRI; | |||
97 | const MachineBlockFrequencyInfo &MBFI; | |||
98 | ||||
99 | InsertPointAnalysis IPA; | |||
100 | ||||
101 | // Map from StackSlot to the LiveInterval of the original register. | |||
102 | // Note the LiveInterval of the original register may have been deleted | |||
103 | // after it is spilled. We keep a copy here to track the range where | |||
104 | // spills can be moved. | |||
105 | DenseMap<int, std::unique_ptr<LiveInterval>> StackSlotToOrigLI; | |||
106 | ||||
107 | // Map from pair of (StackSlot and Original VNI) to a set of spills which | |||
108 | // have the same stackslot and have equal values defined by Original VNI. | |||
109 | // These spills are mergeable and are hoist candiates. | |||
110 | using MergeableSpillsMap = | |||
111 | MapVector<std::pair<int, VNInfo *>, SmallPtrSet<MachineInstr *, 16>>; | |||
112 | MergeableSpillsMap MergeableSpills; | |||
113 | ||||
114 | /// This is the map from original register to a set containing all its | |||
115 | /// siblings. To hoist a spill to another BB, we need to find out a live | |||
116 | /// sibling there and use it as the source of the new spill. | |||
117 | DenseMap<Register, SmallSetVector<Register, 16>> Virt2SiblingsMap; | |||
118 | ||||
119 | bool isSpillCandBB(LiveInterval &OrigLI, VNInfo &OrigVNI, | |||
120 | MachineBasicBlock &BB, Register &LiveReg); | |||
121 | ||||
122 | void rmRedundantSpills( | |||
123 | SmallPtrSet<MachineInstr *, 16> &Spills, | |||
124 | SmallVectorImpl<MachineInstr *> &SpillsToRm, | |||
125 | DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill); | |||
126 | ||||
127 | void getVisitOrders( | |||
128 | MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills, | |||
129 | SmallVectorImpl<MachineDomTreeNode *> &Orders, | |||
130 | SmallVectorImpl<MachineInstr *> &SpillsToRm, | |||
131 | DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep, | |||
132 | DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill); | |||
133 | ||||
134 | void runHoistSpills(LiveInterval &OrigLI, VNInfo &OrigVNI, | |||
135 | SmallPtrSet<MachineInstr *, 16> &Spills, | |||
136 | SmallVectorImpl<MachineInstr *> &SpillsToRm, | |||
137 | DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns); | |||
138 | ||||
139 | public: | |||
140 | HoistSpillHelper(MachineFunctionPass &pass, MachineFunction &mf, | |||
141 | VirtRegMap &vrm) | |||
142 | : MF(mf), LIS(pass.getAnalysis<LiveIntervals>()), | |||
143 | LSS(pass.getAnalysis<LiveStacks>()), | |||
144 | AA(&pass.getAnalysis<AAResultsWrapperPass>().getAAResults()), | |||
145 | MDT(pass.getAnalysis<MachineDominatorTree>()), | |||
146 | Loops(pass.getAnalysis<MachineLoopInfo>()), VRM(vrm), | |||
147 | MRI(mf.getRegInfo()), TII(*mf.getSubtarget().getInstrInfo()), | |||
148 | TRI(*mf.getSubtarget().getRegisterInfo()), | |||
149 | MBFI(pass.getAnalysis<MachineBlockFrequencyInfo>()), | |||
150 | IPA(LIS, mf.getNumBlockIDs()) {} | |||
151 | ||||
152 | void addToMergeableSpills(MachineInstr &Spill, int StackSlot, | |||
153 | unsigned Original); | |||
154 | bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot); | |||
155 | void hoistAllSpills(); | |||
156 | void LRE_DidCloneVirtReg(Register, Register) override; | |||
157 | }; | |||
158 | ||||
159 | class InlineSpiller : public Spiller { | |||
160 | MachineFunction &MF; | |||
161 | LiveIntervals &LIS; | |||
162 | LiveStacks &LSS; | |||
163 | AliasAnalysis *AA; | |||
164 | MachineDominatorTree &MDT; | |||
165 | MachineLoopInfo &Loops; | |||
166 | VirtRegMap &VRM; | |||
167 | MachineRegisterInfo &MRI; | |||
168 | const TargetInstrInfo &TII; | |||
169 | const TargetRegisterInfo &TRI; | |||
170 | const MachineBlockFrequencyInfo &MBFI; | |||
171 | ||||
172 | // Variables that are valid during spill(), but used by multiple methods. | |||
173 | LiveRangeEdit *Edit; | |||
174 | LiveInterval *StackInt; | |||
175 | int StackSlot; | |||
176 | Register Original; | |||
177 | ||||
178 | // All registers to spill to StackSlot, including the main register. | |||
179 | SmallVector<Register, 8> RegsToSpill; | |||
180 | ||||
181 | // All COPY instructions to/from snippets. | |||
182 | // They are ignored since both operands refer to the same stack slot. | |||
183 | SmallPtrSet<MachineInstr*, 8> SnippetCopies; | |||
184 | ||||
185 | // Values that failed to remat at some point. | |||
186 | SmallPtrSet<VNInfo*, 8> UsedValues; | |||
187 | ||||
188 | // Dead defs generated during spilling. | |||
189 | SmallVector<MachineInstr*, 8> DeadDefs; | |||
190 | ||||
191 | // Object records spills information and does the hoisting. | |||
192 | HoistSpillHelper HSpiller; | |||
193 | ||||
194 | // Live range weight calculator. | |||
195 | VirtRegAuxInfo &VRAI; | |||
196 | ||||
197 | ~InlineSpiller() override = default; | |||
198 | ||||
199 | public: | |||
200 | InlineSpiller(MachineFunctionPass &Pass, MachineFunction &MF, VirtRegMap &VRM, | |||
201 | VirtRegAuxInfo &VRAI) | |||
202 | : MF(MF), LIS(Pass.getAnalysis<LiveIntervals>()), | |||
203 | LSS(Pass.getAnalysis<LiveStacks>()), | |||
204 | AA(&Pass.getAnalysis<AAResultsWrapperPass>().getAAResults()), | |||
205 | MDT(Pass.getAnalysis<MachineDominatorTree>()), | |||
206 | Loops(Pass.getAnalysis<MachineLoopInfo>()), VRM(VRM), | |||
207 | MRI(MF.getRegInfo()), TII(*MF.getSubtarget().getInstrInfo()), | |||
208 | TRI(*MF.getSubtarget().getRegisterInfo()), | |||
209 | MBFI(Pass.getAnalysis<MachineBlockFrequencyInfo>()), | |||
210 | HSpiller(Pass, MF, VRM), VRAI(VRAI) {} | |||
211 | ||||
212 | void spill(LiveRangeEdit &) override; | |||
213 | void postOptimization() override; | |||
214 | ||||
215 | private: | |||
216 | bool isSnippet(const LiveInterval &SnipLI); | |||
217 | void collectRegsToSpill(); | |||
218 | ||||
219 | bool isRegToSpill(Register Reg) { return is_contained(RegsToSpill, Reg); } | |||
220 | ||||
221 | bool isSibling(Register Reg); | |||
222 | bool hoistSpillInsideBB(LiveInterval &SpillLI, MachineInstr &CopyMI); | |||
223 | void eliminateRedundantSpills(LiveInterval &LI, VNInfo *VNI); | |||
224 | ||||
225 | void markValueUsed(LiveInterval*, VNInfo*); | |||
226 | bool canGuaranteeAssignmentAfterRemat(Register VReg, MachineInstr &MI); | |||
227 | bool reMaterializeFor(LiveInterval &, MachineInstr &MI); | |||
228 | void reMaterializeAll(); | |||
229 | ||||
230 | bool coalesceStackAccess(MachineInstr *MI, Register Reg); | |||
231 | bool foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>>, | |||
232 | MachineInstr *LoadMI = nullptr); | |||
233 | void insertReload(Register VReg, SlotIndex, MachineBasicBlock::iterator MI); | |||
234 | void insertSpill(Register VReg, bool isKill, MachineBasicBlock::iterator MI); | |||
235 | ||||
236 | void spillAroundUses(Register Reg); | |||
237 | void spillAll(); | |||
238 | }; | |||
239 | ||||
240 | } // end anonymous namespace | |||
241 | ||||
242 | Spiller::~Spiller() = default; | |||
243 | ||||
244 | void Spiller::anchor() {} | |||
245 | ||||
246 | Spiller *llvm::createInlineSpiller(MachineFunctionPass &Pass, | |||
247 | MachineFunction &MF, VirtRegMap &VRM, | |||
248 | VirtRegAuxInfo &VRAI) { | |||
249 | return new InlineSpiller(Pass, MF, VRM, VRAI); | |||
250 | } | |||
251 | ||||
252 | //===----------------------------------------------------------------------===// | |||
253 | // Snippets | |||
254 | //===----------------------------------------------------------------------===// | |||
255 | ||||
256 | // When spilling a virtual register, we also spill any snippets it is connected | |||
257 | // to. The snippets are small live ranges that only have a single real use, | |||
258 | // leftovers from live range splitting. Spilling them enables memory operand | |||
259 | // folding or tightens the live range around the single use. | |||
260 | // | |||
261 | // This minimizes register pressure and maximizes the store-to-load distance for | |||
262 | // spill slots which can be important in tight loops. | |||
263 | ||||
264 | /// isFullCopyOf - If MI is a COPY to or from Reg, return the other register, | |||
265 | /// otherwise return 0. | |||
266 | static Register isFullCopyOf(const MachineInstr &MI, Register Reg) { | |||
267 | if (!MI.isFullCopy()) | |||
268 | return Register(); | |||
269 | if (MI.getOperand(0).getReg() == Reg) | |||
270 | return MI.getOperand(1).getReg(); | |||
271 | if (MI.getOperand(1).getReg() == Reg) | |||
272 | return MI.getOperand(0).getReg(); | |||
273 | return Register(); | |||
274 | } | |||
275 | ||||
276 | static void getVDefInterval(const MachineInstr &MI, LiveIntervals &LIS) { | |||
277 | for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) { | |||
278 | const MachineOperand &MO = MI.getOperand(I); | |||
279 | if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg())) | |||
280 | LIS.getInterval(MO.getReg()); | |||
281 | } | |||
282 | } | |||
283 | ||||
284 | /// isSnippet - Identify if a live interval is a snippet that should be spilled. | |||
285 | /// It is assumed that SnipLI is a virtual register with the same original as | |||
286 | /// Edit->getReg(). | |||
287 | bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) { | |||
288 | Register Reg = Edit->getReg(); | |||
289 | ||||
290 | // A snippet is a tiny live range with only a single instruction using it | |||
291 | // besides copies to/from Reg or spills/fills. We accept: | |||
292 | // | |||
293 | // %snip = COPY %Reg / FILL fi# | |||
294 | // %snip = USE %snip | |||
295 | // %Reg = COPY %snip / SPILL %snip, fi# | |||
296 | // | |||
297 | if (SnipLI.getNumValNums() > 2 || !LIS.intervalIsInOneMBB(SnipLI)) | |||
298 | return false; | |||
299 | ||||
300 | MachineInstr *UseMI = nullptr; | |||
301 | ||||
302 | // Check that all uses satisfy our criteria. | |||
303 | for (MachineRegisterInfo::reg_instr_nodbg_iterator | |||
304 | RI = MRI.reg_instr_nodbg_begin(SnipLI.reg()), | |||
305 | E = MRI.reg_instr_nodbg_end(); | |||
306 | RI != E;) { | |||
307 | MachineInstr &MI = *RI++; | |||
308 | ||||
309 | // Allow copies to/from Reg. | |||
310 | if (isFullCopyOf(MI, Reg)) | |||
311 | continue; | |||
312 | ||||
313 | // Allow stack slot loads. | |||
314 | int FI; | |||
315 | if (SnipLI.reg() == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot) | |||
316 | continue; | |||
317 | ||||
318 | // Allow stack slot stores. | |||
319 | if (SnipLI.reg() == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) | |||
320 | continue; | |||
321 | ||||
322 | // Allow a single additional instruction. | |||
323 | if (UseMI && &MI != UseMI) | |||
324 | return false; | |||
325 | UseMI = &MI; | |||
326 | } | |||
327 | return true; | |||
328 | } | |||
329 | ||||
330 | /// collectRegsToSpill - Collect live range snippets that only have a single | |||
331 | /// real use. | |||
332 | void InlineSpiller::collectRegsToSpill() { | |||
333 | Register Reg = Edit->getReg(); | |||
334 | ||||
335 | // Main register always spills. | |||
336 | RegsToSpill.assign(1, Reg); | |||
337 | SnippetCopies.clear(); | |||
338 | ||||
339 | // Snippets all have the same original, so there can't be any for an original | |||
340 | // register. | |||
341 | if (Original == Reg) | |||
342 | return; | |||
343 | ||||
344 | for (MachineRegisterInfo::reg_instr_iterator | |||
345 | RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); RI != E; ) { | |||
346 | MachineInstr &MI = *RI++; | |||
347 | Register SnipReg = isFullCopyOf(MI, Reg); | |||
348 | if (!isSibling(SnipReg)) | |||
349 | continue; | |||
350 | LiveInterval &SnipLI = LIS.getInterval(SnipReg); | |||
351 | if (!isSnippet(SnipLI)) | |||
352 | continue; | |||
353 | SnippetCopies.insert(&MI); | |||
354 | if (isRegToSpill(SnipReg)) | |||
355 | continue; | |||
356 | RegsToSpill.push_back(SnipReg); | |||
357 | LLVM_DEBUG(dbgs() << "\talso spill snippet " << SnipLI << '\n')do { } while (false); | |||
358 | ++NumSnippets; | |||
359 | } | |||
360 | } | |||
361 | ||||
362 | bool InlineSpiller::isSibling(Register Reg) { | |||
363 | return Reg.isVirtual() && VRM.getOriginal(Reg) == Original; | |||
364 | } | |||
365 | ||||
366 | /// It is beneficial to spill to earlier place in the same BB in case | |||
367 | /// as follows: | |||
368 | /// There is an alternative def earlier in the same MBB. | |||
369 | /// Hoist the spill as far as possible in SpillMBB. This can ease | |||
370 | /// register pressure: | |||
371 | /// | |||
372 | /// x = def | |||
373 | /// y = use x | |||
374 | /// s = copy x | |||
375 | /// | |||
376 | /// Hoisting the spill of s to immediately after the def removes the | |||
377 | /// interference between x and y: | |||
378 | /// | |||
379 | /// x = def | |||
380 | /// spill x | |||
381 | /// y = use killed x | |||
382 | /// | |||
383 | /// This hoist only helps when the copy kills its source. | |||
384 | /// | |||
385 | bool InlineSpiller::hoistSpillInsideBB(LiveInterval &SpillLI, | |||
386 | MachineInstr &CopyMI) { | |||
387 | SlotIndex Idx = LIS.getInstructionIndex(CopyMI); | |||
388 | #ifndef NDEBUG1 | |||
389 | VNInfo *VNI = SpillLI.getVNInfoAt(Idx.getRegSlot()); | |||
390 | assert(VNI && VNI->def == Idx.getRegSlot() && "Not defined by copy")((void)0); | |||
391 | #endif | |||
392 | ||||
393 | Register SrcReg = CopyMI.getOperand(1).getReg(); | |||
394 | LiveInterval &SrcLI = LIS.getInterval(SrcReg); | |||
395 | VNInfo *SrcVNI = SrcLI.getVNInfoAt(Idx); | |||
396 | LiveQueryResult SrcQ = SrcLI.Query(Idx); | |||
397 | MachineBasicBlock *DefMBB = LIS.getMBBFromIndex(SrcVNI->def); | |||
398 | if (DefMBB != CopyMI.getParent() || !SrcQ.isKill()) | |||
399 | return false; | |||
400 | ||||
401 | // Conservatively extend the stack slot range to the range of the original | |||
402 | // value. We may be able to do better with stack slot coloring by being more | |||
403 | // careful here. | |||
404 | assert(StackInt && "No stack slot assigned yet.")((void)0); | |||
405 | LiveInterval &OrigLI = LIS.getInterval(Original); | |||
406 | VNInfo *OrigVNI = OrigLI.getVNInfoAt(Idx); | |||
407 | StackInt->MergeValueInAsValue(OrigLI, OrigVNI, StackInt->getValNumInfo(0)); | |||
408 | LLVM_DEBUG(dbgs() << "\tmerged orig valno " << OrigVNI->id << ": "do { } while (false) | |||
409 | << *StackInt << '\n')do { } while (false); | |||
410 | ||||
411 | // We are going to spill SrcVNI immediately after its def, so clear out | |||
412 | // any later spills of the same value. | |||
413 | eliminateRedundantSpills(SrcLI, SrcVNI); | |||
414 | ||||
415 | MachineBasicBlock *MBB = LIS.getMBBFromIndex(SrcVNI->def); | |||
416 | MachineBasicBlock::iterator MII; | |||
417 | if (SrcVNI->isPHIDef()) | |||
418 | MII = MBB->SkipPHIsLabelsAndDebug(MBB->begin()); | |||
419 | else { | |||
420 | MachineInstr *DefMI = LIS.getInstructionFromIndex(SrcVNI->def); | |||
421 | assert(DefMI && "Defining instruction disappeared")((void)0); | |||
422 | MII = DefMI; | |||
423 | ++MII; | |||
424 | } | |||
425 | MachineInstrSpan MIS(MII, MBB); | |||
426 | // Insert spill without kill flag immediately after def. | |||
427 | TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot, | |||
428 | MRI.getRegClass(SrcReg), &TRI); | |||
429 | LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII); | |||
430 | for (const MachineInstr &MI : make_range(MIS.begin(), MII)) | |||
431 | getVDefInterval(MI, LIS); | |||
432 | --MII; // Point to store instruction. | |||
433 | LLVM_DEBUG(dbgs() << "\thoisted: " << SrcVNI->def << '\t' << *MII)do { } while (false); | |||
434 | ||||
435 | // If there is only 1 store instruction is required for spill, add it | |||
436 | // to mergeable list. In X86 AMX, 2 intructions are required to store. | |||
437 | // We disable the merge for this case. | |||
438 | if (MIS.begin() == MII) | |||
439 | HSpiller.addToMergeableSpills(*MII, StackSlot, Original); | |||
440 | ++NumSpills; | |||
441 | return true; | |||
442 | } | |||
443 | ||||
444 | /// eliminateRedundantSpills - SLI:VNI is known to be on the stack. Remove any | |||
445 | /// redundant spills of this value in SLI.reg and sibling copies. | |||
446 | void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) { | |||
447 | assert(VNI && "Missing value")((void)0); | |||
448 | SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList; | |||
449 | WorkList.push_back(std::make_pair(&SLI, VNI)); | |||
450 | assert(StackInt && "No stack slot assigned yet.")((void)0); | |||
451 | ||||
452 | do { | |||
453 | LiveInterval *LI; | |||
454 | std::tie(LI, VNI) = WorkList.pop_back_val(); | |||
455 | Register Reg = LI->reg(); | |||
456 | LLVM_DEBUG(dbgs() << "Checking redundant spills for " << VNI->id << '@'do { } while (false) | |||
457 | << VNI->def << " in " << *LI << '\n')do { } while (false); | |||
458 | ||||
459 | // Regs to spill are taken care of. | |||
460 | if (isRegToSpill(Reg)) | |||
461 | continue; | |||
462 | ||||
463 | // Add all of VNI's live range to StackInt. | |||
464 | StackInt->MergeValueInAsValue(*LI, VNI, StackInt->getValNumInfo(0)); | |||
465 | LLVM_DEBUG(dbgs() << "Merged to stack int: " << *StackInt << '\n')do { } while (false); | |||
466 | ||||
467 | // Find all spills and copies of VNI. | |||
468 | for (MachineRegisterInfo::use_instr_nodbg_iterator | |||
469 | UI = MRI.use_instr_nodbg_begin(Reg), E = MRI.use_instr_nodbg_end(); | |||
470 | UI != E; ) { | |||
471 | MachineInstr &MI = *UI++; | |||
472 | if (!MI.isCopy() && !MI.mayStore()) | |||
473 | continue; | |||
474 | SlotIndex Idx = LIS.getInstructionIndex(MI); | |||
475 | if (LI->getVNInfoAt(Idx) != VNI) | |||
476 | continue; | |||
477 | ||||
478 | // Follow sibling copies down the dominator tree. | |||
479 | if (Register DstReg = isFullCopyOf(MI, Reg)) { | |||
480 | if (isSibling(DstReg)) { | |||
481 | LiveInterval &DstLI = LIS.getInterval(DstReg); | |||
482 | VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot()); | |||
483 | assert(DstVNI && "Missing defined value")((void)0); | |||
484 | assert(DstVNI->def == Idx.getRegSlot() && "Wrong copy def slot")((void)0); | |||
485 | WorkList.push_back(std::make_pair(&DstLI, DstVNI)); | |||
486 | } | |||
487 | continue; | |||
488 | } | |||
489 | ||||
490 | // Erase spills. | |||
491 | int FI; | |||
492 | if (Reg == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot) { | |||
| ||||
493 | LLVM_DEBUG(dbgs() << "Redundant spill " << Idx << '\t' << MI)do { } while (false); | |||
494 | // eliminateDeadDefs won't normally remove stores, so switch opcode. | |||
495 | MI.setDesc(TII.get(TargetOpcode::KILL)); | |||
496 | DeadDefs.push_back(&MI); | |||
497 | ++NumSpillsRemoved; | |||
498 | if (HSpiller.rmFromMergeableSpills(MI, StackSlot)) | |||
499 | --NumSpills; | |||
500 | } | |||
501 | } | |||
502 | } while (!WorkList.empty()); | |||
503 | } | |||
504 | ||||
505 | //===----------------------------------------------------------------------===// | |||
506 | // Rematerialization | |||
507 | //===----------------------------------------------------------------------===// | |||
508 | ||||
509 | /// markValueUsed - Remember that VNI failed to rematerialize, so its defining | |||
510 | /// instruction cannot be eliminated. See through snippet copies | |||
511 | void InlineSpiller::markValueUsed(LiveInterval *LI, VNInfo *VNI) { | |||
512 | SmallVector<std::pair<LiveInterval*, VNInfo*>, 8> WorkList; | |||
513 | WorkList.push_back(std::make_pair(LI, VNI)); | |||
514 | do { | |||
515 | std::tie(LI, VNI) = WorkList.pop_back_val(); | |||
516 | if (!UsedValues.insert(VNI).second) | |||
517 | continue; | |||
518 | ||||
519 | if (VNI->isPHIDef()) { | |||
520 | MachineBasicBlock *MBB = LIS.getMBBFromIndex(VNI->def); | |||
521 | for (MachineBasicBlock *P : MBB->predecessors()) { | |||
522 | VNInfo *PVNI = LI->getVNInfoBefore(LIS.getMBBEndIdx(P)); | |||
523 | if (PVNI) | |||
524 | WorkList.push_back(std::make_pair(LI, PVNI)); | |||
525 | } | |||
526 | continue; | |||
527 | } | |||
528 | ||||
529 | // Follow snippet copies. | |||
530 | MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); | |||
531 | if (!SnippetCopies.count(MI)) | |||
532 | continue; | |||
533 | LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg()); | |||
534 | assert(isRegToSpill(SnipLI.reg()) && "Unexpected register in copy")((void)0); | |||
535 | VNInfo *SnipVNI = SnipLI.getVNInfoAt(VNI->def.getRegSlot(true)); | |||
536 | assert(SnipVNI && "Snippet undefined before copy")((void)0); | |||
537 | WorkList.push_back(std::make_pair(&SnipLI, SnipVNI)); | |||
538 | } while (!WorkList.empty()); | |||
539 | } | |||
540 | ||||
541 | bool InlineSpiller::canGuaranteeAssignmentAfterRemat(Register VReg, | |||
542 | MachineInstr &MI) { | |||
543 | if (!RestrictStatepointRemat) | |||
544 | return true; | |||
545 | // Here's a quick explanation of the problem we're trying to handle here: | |||
546 | // * There are some pseudo instructions with more vreg uses than there are | |||
547 | // physical registers on the machine. | |||
548 | // * This is normally handled by spilling the vreg, and folding the reload | |||
549 | // into the user instruction. (Thus decreasing the number of used vregs | |||
550 | // until the remainder can be assigned to physregs.) | |||
551 | // * However, since we may try to spill vregs in any order, we can end up | |||
552 | // trying to spill each operand to the instruction, and then rematting it | |||
553 | // instead. When that happens, the new live intervals (for the remats) are | |||
554 | // expected to be trivially assignable (i.e. RS_Done). However, since we | |||
555 | // may have more remats than physregs, we're guaranteed to fail to assign | |||
556 | // one. | |||
557 | // At the moment, we only handle this for STATEPOINTs since they're the only | |||
558 | // pseudo op where we've seen this. If we start seeing other instructions | |||
559 | // with the same problem, we need to revisit this. | |||
560 | if (MI.getOpcode() != TargetOpcode::STATEPOINT) | |||
561 | return true; | |||
562 | // For STATEPOINTs we allow re-materialization for fixed arguments only hoping | |||
563 | // that number of physical registers is enough to cover all fixed arguments. | |||
564 | // If it is not true we need to revisit it. | |||
565 | for (unsigned Idx = StatepointOpers(&MI).getVarIdx(), | |||
566 | EndIdx = MI.getNumOperands(); | |||
567 | Idx < EndIdx; ++Idx) { | |||
568 | MachineOperand &MO = MI.getOperand(Idx); | |||
569 | if (MO.isReg() && MO.getReg() == VReg) | |||
570 | return false; | |||
571 | } | |||
572 | return true; | |||
573 | } | |||
574 | ||||
575 | /// reMaterializeFor - Attempt to rematerialize before MI instead of reloading. | |||
576 | bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, MachineInstr &MI) { | |||
577 | // Analyze instruction | |||
578 | SmallVector<std::pair<MachineInstr *, unsigned>, 8> Ops; | |||
579 | VirtRegInfo RI = AnalyzeVirtRegInBundle(MI, VirtReg.reg(), &Ops); | |||
580 | ||||
581 | if (!RI.Reads) | |||
582 | return false; | |||
583 | ||||
584 | SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); | |||
585 | VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); | |||
586 | ||||
587 | if (!ParentVNI) { | |||
588 | LLVM_DEBUG(dbgs() << "\tadding <undef> flags: ")do { } while (false); | |||
589 | for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { | |||
590 | MachineOperand &MO = MI.getOperand(i); | |||
591 | if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg()) | |||
592 | MO.setIsUndef(); | |||
593 | } | |||
594 | LLVM_DEBUG(dbgs() << UseIdx << '\t' << MI)do { } while (false); | |||
595 | return true; | |||
596 | } | |||
597 | ||||
598 | if (SnippetCopies.count(&MI)) | |||
599 | return false; | |||
600 | ||||
601 | LiveInterval &OrigLI = LIS.getInterval(Original); | |||
602 | VNInfo *OrigVNI = OrigLI.getVNInfoAt(UseIdx); | |||
603 | LiveRangeEdit::Remat RM(ParentVNI); | |||
604 | RM.OrigMI = LIS.getInstructionFromIndex(OrigVNI->def); | |||
605 | ||||
606 | if (!Edit->canRematerializeAt(RM, OrigVNI, UseIdx, false)) { | |||
607 | markValueUsed(&VirtReg, ParentVNI); | |||
608 | LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI)do { } while (false); | |||
609 | return false; | |||
610 | } | |||
611 | ||||
612 | // If the instruction also writes VirtReg.reg, it had better not require the | |||
613 | // same register for uses and defs. | |||
614 | if (RI.Tied) { | |||
615 | markValueUsed(&VirtReg, ParentVNI); | |||
616 | LLVM_DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << MI)do { } while (false); | |||
617 | return false; | |||
618 | } | |||
619 | ||||
620 | // Before rematerializing into a register for a single instruction, try to | |||
621 | // fold a load into the instruction. That avoids allocating a new register. | |||
622 | if (RM.OrigMI->canFoldAsLoad() && | |||
623 | foldMemoryOperand(Ops, RM.OrigMI)) { | |||
624 | Edit->markRematerialized(RM.ParentVNI); | |||
625 | ++NumFoldedLoads; | |||
626 | return true; | |||
627 | } | |||
628 | ||||
629 | // If we can't guarantee that we'll be able to actually assign the new vreg, | |||
630 | // we can't remat. | |||
631 | if (!canGuaranteeAssignmentAfterRemat(VirtReg.reg(), MI)) { | |||
632 | markValueUsed(&VirtReg, ParentVNI); | |||
633 | LLVM_DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << MI)do { } while (false); | |||
634 | return false; | |||
635 | } | |||
636 | ||||
637 | // Allocate a new register for the remat. | |||
638 | Register NewVReg = Edit->createFrom(Original); | |||
639 | ||||
640 | // Finally we can rematerialize OrigMI before MI. | |||
641 | SlotIndex DefIdx = | |||
642 | Edit->rematerializeAt(*MI.getParent(), MI, NewVReg, RM, TRI); | |||
643 | ||||
644 | // We take the DebugLoc from MI, since OrigMI may be attributed to a | |||
645 | // different source location. | |||
646 | auto *NewMI = LIS.getInstructionFromIndex(DefIdx); | |||
647 | NewMI->setDebugLoc(MI.getDebugLoc()); | |||
648 | ||||
649 | (void)DefIdx; | |||
650 | LLVM_DEBUG(dbgs() << "\tremat: " << DefIdx << '\t'do { } while (false) | |||
651 | << *LIS.getInstructionFromIndex(DefIdx))do { } while (false); | |||
652 | ||||
653 | // Replace operands | |||
654 | for (const auto &OpPair : Ops) { | |||
655 | MachineOperand &MO = OpPair.first->getOperand(OpPair.second); | |||
656 | if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg()) { | |||
657 | MO.setReg(NewVReg); | |||
658 | MO.setIsKill(); | |||
659 | } | |||
660 | } | |||
661 | LLVM_DEBUG(dbgs() << "\t " << UseIdx << '\t' << MI << '\n')do { } while (false); | |||
662 | ||||
663 | ++NumRemats; | |||
664 | return true; | |||
665 | } | |||
666 | ||||
667 | /// reMaterializeAll - Try to rematerialize as many uses as possible, | |||
668 | /// and trim the live ranges after. | |||
669 | void InlineSpiller::reMaterializeAll() { | |||
670 | if (!Edit->anyRematerializable(AA)) | |||
671 | return; | |||
672 | ||||
673 | UsedValues.clear(); | |||
674 | ||||
675 | // Try to remat before all uses of snippets. | |||
676 | bool anyRemat = false; | |||
677 | for (Register Reg : RegsToSpill) { | |||
678 | LiveInterval &LI = LIS.getInterval(Reg); | |||
679 | for (MachineRegisterInfo::reg_bundle_iterator | |||
680 | RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end(); | |||
681 | RegI != E; ) { | |||
682 | MachineInstr &MI = *RegI++; | |||
683 | ||||
684 | // Debug values are not allowed to affect codegen. | |||
685 | if (MI.isDebugValue()) | |||
686 | continue; | |||
687 | ||||
688 | assert(!MI.isDebugInstr() && "Did not expect to find a use in debug "((void)0) | |||
689 | "instruction that isn't a DBG_VALUE")((void)0); | |||
690 | ||||
691 | anyRemat |= reMaterializeFor(LI, MI); | |||
692 | } | |||
693 | } | |||
694 | if (!anyRemat) | |||
695 | return; | |||
696 | ||||
697 | // Remove any values that were completely rematted. | |||
698 | for (Register Reg : RegsToSpill) { | |||
699 | LiveInterval &LI = LIS.getInterval(Reg); | |||
700 | for (LiveInterval::vni_iterator I = LI.vni_begin(), E = LI.vni_end(); | |||
701 | I != E; ++I) { | |||
702 | VNInfo *VNI = *I; | |||
703 | if (VNI->isUnused() || VNI->isPHIDef() || UsedValues.count(VNI)) | |||
704 | continue; | |||
705 | MachineInstr *MI = LIS.getInstructionFromIndex(VNI->def); | |||
706 | MI->addRegisterDead(Reg, &TRI); | |||
707 | if (!MI->allDefsAreDead()) | |||
708 | continue; | |||
709 | LLVM_DEBUG(dbgs() << "All defs dead: " << *MI)do { } while (false); | |||
710 | DeadDefs.push_back(MI); | |||
711 | } | |||
712 | } | |||
713 | ||||
714 | // Eliminate dead code after remat. Note that some snippet copies may be | |||
715 | // deleted here. | |||
716 | if (DeadDefs.empty()) | |||
717 | return; | |||
718 | LLVM_DEBUG(dbgs() << "Remat created " << DeadDefs.size() << " dead defs.\n")do { } while (false); | |||
719 | Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA); | |||
720 | ||||
721 | // LiveRangeEdit::eliminateDeadDef is used to remove dead define instructions | |||
722 | // after rematerialization. To remove a VNI for a vreg from its LiveInterval, | |||
723 | // LiveIntervals::removeVRegDefAt is used. However, after non-PHI VNIs are all | |||
724 | // removed, PHI VNI are still left in the LiveInterval. | |||
725 | // So to get rid of unused reg, we need to check whether it has non-dbg | |||
726 | // reference instead of whether it has non-empty interval. | |||
727 | unsigned ResultPos = 0; | |||
728 | for (Register Reg : RegsToSpill) { | |||
729 | if (MRI.reg_nodbg_empty(Reg)) { | |||
730 | Edit->eraseVirtReg(Reg); | |||
731 | continue; | |||
732 | } | |||
733 | ||||
734 | assert(LIS.hasInterval(Reg) &&((void)0) | |||
735 | (!LIS.getInterval(Reg).empty() || !MRI.reg_nodbg_empty(Reg)) &&((void)0) | |||
736 | "Empty and not used live-range?!")((void)0); | |||
737 | ||||
738 | RegsToSpill[ResultPos++] = Reg; | |||
739 | } | |||
740 | RegsToSpill.erase(RegsToSpill.begin() + ResultPos, RegsToSpill.end()); | |||
741 | LLVM_DEBUG(dbgs() << RegsToSpill.size()do { } while (false) | |||
742 | << " registers to spill after remat.\n")do { } while (false); | |||
743 | } | |||
744 | ||||
745 | //===----------------------------------------------------------------------===// | |||
746 | // Spilling | |||
747 | //===----------------------------------------------------------------------===// | |||
748 | ||||
749 | /// If MI is a load or store of StackSlot, it can be removed. | |||
750 | bool InlineSpiller::coalesceStackAccess(MachineInstr *MI, Register Reg) { | |||
751 | int FI = 0; | |||
752 | Register InstrReg = TII.isLoadFromStackSlot(*MI, FI); | |||
753 | bool IsLoad = InstrReg; | |||
754 | if (!IsLoad) | |||
755 | InstrReg = TII.isStoreToStackSlot(*MI, FI); | |||
756 | ||||
757 | // We have a stack access. Is it the right register and slot? | |||
758 | if (InstrReg != Reg || FI != StackSlot) | |||
759 | return false; | |||
760 | ||||
761 | if (!IsLoad) | |||
762 | HSpiller.rmFromMergeableSpills(*MI, StackSlot); | |||
763 | ||||
764 | LLVM_DEBUG(dbgs() << "Coalescing stack access: " << *MI)do { } while (false); | |||
765 | LIS.RemoveMachineInstrFromMaps(*MI); | |||
766 | MI->eraseFromParent(); | |||
767 | ||||
768 | if (IsLoad) { | |||
769 | ++NumReloadsRemoved; | |||
770 | --NumReloads; | |||
771 | } else { | |||
772 | ++NumSpillsRemoved; | |||
773 | --NumSpills; | |||
774 | } | |||
775 | ||||
776 | return true; | |||
777 | } | |||
778 | ||||
779 | #if !defined(NDEBUG1) || defined(LLVM_ENABLE_DUMP) | |||
780 | LLVM_DUMP_METHOD__attribute__((noinline)) | |||
781 | // Dump the range of instructions from B to E with their slot indexes. | |||
782 | static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B, | |||
783 | MachineBasicBlock::iterator E, | |||
784 | LiveIntervals const &LIS, | |||
785 | const char *const header, | |||
786 | Register VReg = Register()) { | |||
787 | char NextLine = '\n'; | |||
788 | char SlotIndent = '\t'; | |||
789 | ||||
790 | if (std::next(B) == E) { | |||
791 | NextLine = ' '; | |||
792 | SlotIndent = ' '; | |||
793 | } | |||
794 | ||||
795 | dbgs() << '\t' << header << ": " << NextLine; | |||
796 | ||||
797 | for (MachineBasicBlock::iterator I = B; I != E; ++I) { | |||
798 | SlotIndex Idx = LIS.getInstructionIndex(*I).getRegSlot(); | |||
799 | ||||
800 | // If a register was passed in and this instruction has it as a | |||
801 | // destination that is marked as an early clobber, print the | |||
802 | // early-clobber slot index. | |||
803 | if (VReg) { | |||
804 | MachineOperand *MO = I->findRegisterDefOperand(VReg); | |||
805 | if (MO && MO->isEarlyClobber()) | |||
806 | Idx = Idx.getRegSlot(true); | |||
807 | } | |||
808 | ||||
809 | dbgs() << SlotIndent << Idx << '\t' << *I; | |||
810 | } | |||
811 | } | |||
812 | #endif | |||
813 | ||||
814 | /// foldMemoryOperand - Try folding stack slot references in Ops into their | |||
815 | /// instructions. | |||
816 | /// | |||
817 | /// @param Ops Operand indices from AnalyzeVirtRegInBundle(). | |||
818 | /// @param LoadMI Load instruction to use instead of stack slot when non-null. | |||
819 | /// @return True on success. | |||
820 | bool InlineSpiller:: | |||
821 | foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops, | |||
822 | MachineInstr *LoadMI) { | |||
823 | if (Ops.empty()) | |||
824 | return false; | |||
825 | // Don't attempt folding in bundles. | |||
826 | MachineInstr *MI = Ops.front().first; | |||
827 | if (Ops.back().first != MI || MI->isBundled()) | |||
828 | return false; | |||
829 | ||||
830 | bool WasCopy = MI->isCopy(); | |||
831 | Register ImpReg; | |||
832 | ||||
833 | // TII::foldMemoryOperand will do what we need here for statepoint | |||
834 | // (fold load into use and remove corresponding def). We will replace | |||
835 | // uses of removed def with loads (spillAroundUses). | |||
836 | // For that to work we need to untie def and use to pass it through | |||
837 | // foldMemoryOperand and signal foldPatchpoint that it is allowed to | |||
838 | // fold them. | |||
839 | bool UntieRegs = MI->getOpcode() == TargetOpcode::STATEPOINT; | |||
840 | ||||
841 | // Spill subregs if the target allows it. | |||
842 | // We always want to spill subregs for stackmap/patchpoint pseudos. | |||
843 | bool SpillSubRegs = TII.isSubregFoldable() || | |||
844 | MI->getOpcode() == TargetOpcode::STATEPOINT || | |||
845 | MI->getOpcode() == TargetOpcode::PATCHPOINT || | |||
846 | MI->getOpcode() == TargetOpcode::STACKMAP; | |||
847 | ||||
848 | // TargetInstrInfo::foldMemoryOperand only expects explicit, non-tied | |||
849 | // operands. | |||
850 | SmallVector<unsigned, 8> FoldOps; | |||
851 | for (const auto &OpPair : Ops) { | |||
852 | unsigned Idx = OpPair.second; | |||
853 | assert(MI == OpPair.first && "Instruction conflict during operand folding")((void)0); | |||
854 | MachineOperand &MO = MI->getOperand(Idx); | |||
855 | if (MO.isImplicit()) { | |||
856 | ImpReg = MO.getReg(); | |||
857 | continue; | |||
858 | } | |||
859 | ||||
860 | if (!SpillSubRegs && MO.getSubReg()) | |||
861 | return false; | |||
862 | // We cannot fold a load instruction into a def. | |||
863 | if (LoadMI && MO.isDef()) | |||
864 | return false; | |||
865 | // Tied use operands should not be passed to foldMemoryOperand. | |||
866 | if (UntieRegs || !MI->isRegTiedToDefOperand(Idx)) | |||
867 | FoldOps.push_back(Idx); | |||
868 | } | |||
869 | ||||
870 | // If we only have implicit uses, we won't be able to fold that. | |||
871 | // Moreover, TargetInstrInfo::foldMemoryOperand will assert if we try! | |||
872 | if (FoldOps.empty()) | |||
873 | return false; | |||
874 | ||||
875 | MachineInstrSpan MIS(MI, MI->getParent()); | |||
876 | ||||
877 | SmallVector<std::pair<unsigned, unsigned> > TiedOps; | |||
878 | if (UntieRegs) | |||
879 | for (unsigned Idx : FoldOps) { | |||
880 | MachineOperand &MO = MI->getOperand(Idx); | |||
881 | if (!MO.isTied()) | |||
882 | continue; | |||
883 | unsigned Tied = MI->findTiedOperandIdx(Idx); | |||
884 | if (MO.isUse()) | |||
885 | TiedOps.emplace_back(Tied, Idx); | |||
886 | else { | |||
887 | assert(MO.isDef() && "Tied to not use and def?")((void)0); | |||
888 | TiedOps.emplace_back(Idx, Tied); | |||
889 | } | |||
890 | MI->untieRegOperand(Idx); | |||
891 | } | |||
892 | ||||
893 | MachineInstr *FoldMI = | |||
894 | LoadMI ? TII.foldMemoryOperand(*MI, FoldOps, *LoadMI, &LIS) | |||
895 | : TII.foldMemoryOperand(*MI, FoldOps, StackSlot, &LIS, &VRM); | |||
896 | if (!FoldMI) { | |||
897 | // Re-tie operands. | |||
898 | for (auto Tied : TiedOps) | |||
899 | MI->tieOperands(Tied.first, Tied.second); | |||
900 | return false; | |||
901 | } | |||
902 | ||||
903 | // Remove LIS for any dead defs in the original MI not in FoldMI. | |||
904 | for (MIBundleOperands MO(*MI); MO.isValid(); ++MO) { | |||
905 | if (!MO->isReg()) | |||
906 | continue; | |||
907 | Register Reg = MO->getReg(); | |||
908 | if (!Reg || Register::isVirtualRegister(Reg) || MRI.isReserved(Reg)) { | |||
909 | continue; | |||
910 | } | |||
911 | // Skip non-Defs, including undef uses and internal reads. | |||
912 | if (MO->isUse()) | |||
913 | continue; | |||
914 | PhysRegInfo RI = AnalyzePhysRegInBundle(*FoldMI, Reg, &TRI); | |||
915 | if (RI.FullyDefined) | |||
916 | continue; | |||
917 | // FoldMI does not define this physreg. Remove the LI segment. | |||
918 | assert(MO->isDead() && "Cannot fold physreg def")((void)0); | |||
919 | SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot(); | |||
920 | LIS.removePhysRegDefAt(Reg.asMCReg(), Idx); | |||
921 | } | |||
922 | ||||
923 | int FI; | |||
924 | if (TII.isStoreToStackSlot(*MI, FI) && | |||
925 | HSpiller.rmFromMergeableSpills(*MI, FI)) | |||
926 | --NumSpills; | |||
927 | LIS.ReplaceMachineInstrInMaps(*MI, *FoldMI); | |||
928 | // Update the call site info. | |||
929 | if (MI->isCandidateForCallSiteEntry()) | |||
930 | MI->getMF()->moveCallSiteInfo(MI, FoldMI); | |||
931 | MI->eraseFromParent(); | |||
932 | ||||
933 | // Insert any new instructions other than FoldMI into the LIS maps. | |||
934 | assert(!MIS.empty() && "Unexpected empty span of instructions!")((void)0); | |||
935 | for (MachineInstr &MI : MIS) | |||
936 | if (&MI != FoldMI) | |||
937 | LIS.InsertMachineInstrInMaps(MI); | |||
938 | ||||
939 | // TII.foldMemoryOperand may have left some implicit operands on the | |||
940 | // instruction. Strip them. | |||
941 | if (ImpReg) | |||
942 | for (unsigned i = FoldMI->getNumOperands(); i; --i) { | |||
943 | MachineOperand &MO = FoldMI->getOperand(i - 1); | |||
944 | if (!MO.isReg() || !MO.isImplicit()) | |||
945 | break; | |||
946 | if (MO.getReg() == ImpReg) | |||
947 | FoldMI->RemoveOperand(i - 1); | |||
948 | } | |||
949 | ||||
950 | LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MIS.end(), LIS,do { } while (false) | |||
951 | "folded"))do { } while (false); | |||
952 | ||||
953 | if (!WasCopy) | |||
954 | ++NumFolded; | |||
955 | else if (Ops.front().second == 0) { | |||
956 | ++NumSpills; | |||
957 | // If there is only 1 store instruction is required for spill, add it | |||
958 | // to mergeable list. In X86 AMX, 2 intructions are required to store. | |||
959 | // We disable the merge for this case. | |||
960 | if (std::distance(MIS.begin(), MIS.end()) <= 1) | |||
961 | HSpiller.addToMergeableSpills(*FoldMI, StackSlot, Original); | |||
962 | } else | |||
963 | ++NumReloads; | |||
964 | return true; | |||
965 | } | |||
966 | ||||
967 | void InlineSpiller::insertReload(Register NewVReg, | |||
968 | SlotIndex Idx, | |||
969 | MachineBasicBlock::iterator MI) { | |||
970 | MachineBasicBlock &MBB = *MI->getParent(); | |||
971 | ||||
972 | MachineInstrSpan MIS(MI, &MBB); | |||
973 | TII.loadRegFromStackSlot(MBB, MI, NewVReg, StackSlot, | |||
974 | MRI.getRegClass(NewVReg), &TRI); | |||
975 | ||||
976 | LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MI); | |||
977 | ||||
978 | LLVM_DEBUG(dumpMachineInstrRangeWithSlotIndex(MIS.begin(), MI, LIS, "reload",do { } while (false) | |||
979 | NewVReg))do { } while (false); | |||
980 | ++NumReloads; | |||
981 | } | |||
982 | ||||
983 | /// Check if \p Def fully defines a VReg with an undefined value. | |||
984 | /// If that's the case, that means the value of VReg is actually | |||
985 | /// not relevant. | |||
986 | static bool isRealSpill(const MachineInstr &Def) { | |||
987 | if (!Def.isImplicitDef()) | |||
988 | return true; | |||
989 | assert(Def.getNumOperands() == 1 &&((void)0) | |||
990 | "Implicit def with more than one definition")((void)0); | |||
991 | // We can say that the VReg defined by Def is undef, only if it is | |||
992 | // fully defined by Def. Otherwise, some of the lanes may not be | |||
993 | // undef and the value of the VReg matters. | |||
994 | return Def.getOperand(0).getSubReg(); | |||
995 | } | |||
996 | ||||
997 | /// insertSpill - Insert a spill of NewVReg after MI. | |||
998 | void InlineSpiller::insertSpill(Register NewVReg, bool isKill, | |||
999 | MachineBasicBlock::iterator MI) { | |||
1000 | // Spill are not terminators, so inserting spills after terminators will | |||
1001 | // violate invariants in MachineVerifier. | |||
1002 | assert(!MI->isTerminator() && "Inserting a spill after a terminator")((void)0); | |||
1003 | MachineBasicBlock &MBB = *MI->getParent(); | |||
1004 | ||||
1005 | MachineInstrSpan MIS(MI, &MBB); | |||
1006 | MachineBasicBlock::iterator SpillBefore = std::next(MI); | |||
1007 | bool IsRealSpill = isRealSpill(*MI); | |||
1008 | ||||
1009 | if (IsRealSpill) | |||
1010 | TII.storeRegToStackSlot(MBB, SpillBefore, NewVReg, isKill, StackSlot, | |||
1011 | MRI.getRegClass(NewVReg), &TRI); | |||
1012 | else | |||
1013 | // Don't spill undef value. | |||
1014 | // Anything works for undef, in particular keeping the memory | |||
1015 | // uninitialized is a viable option and it saves code size and | |||
1016 | // run time. | |||
1017 | BuildMI(MBB, SpillBefore, MI->getDebugLoc(), TII.get(TargetOpcode::KILL)) | |||
1018 | .addReg(NewVReg, getKillRegState(isKill)); | |||
1019 | ||||
1020 | MachineBasicBlock::iterator Spill = std::next(MI); | |||
1021 | LIS.InsertMachineInstrRangeInMaps(Spill, MIS.end()); | |||
1022 | for (const MachineInstr &MI : make_range(Spill, MIS.end())) | |||
1023 | getVDefInterval(MI, LIS); | |||
1024 | ||||
1025 | LLVM_DEBUG(do { } while (false) | |||
1026 | dumpMachineInstrRangeWithSlotIndex(Spill, MIS.end(), LIS, "spill"))do { } while (false); | |||
1027 | ++NumSpills; | |||
1028 | // If there is only 1 store instruction is required for spill, add it | |||
1029 | // to mergeable list. In X86 AMX, 2 intructions are required to store. | |||
1030 | // We disable the merge for this case. | |||
1031 | if (IsRealSpill && std::distance(Spill, MIS.end()) <= 1) | |||
1032 | HSpiller.addToMergeableSpills(*Spill, StackSlot, Original); | |||
1033 | } | |||
1034 | ||||
1035 | /// spillAroundUses - insert spill code around each use of Reg. | |||
1036 | void InlineSpiller::spillAroundUses(Register Reg) { | |||
1037 | LLVM_DEBUG(dbgs() << "spillAroundUses " << printReg(Reg) << '\n')do { } while (false); | |||
1038 | LiveInterval &OldLI = LIS.getInterval(Reg); | |||
1039 | ||||
1040 | // Iterate over instructions using Reg. | |||
1041 | for (MachineRegisterInfo::reg_bundle_iterator | |||
1042 | RegI = MRI.reg_bundle_begin(Reg), E = MRI.reg_bundle_end(); | |||
1043 | RegI != E; ) { | |||
1044 | MachineInstr *MI = &*(RegI++); | |||
1045 | ||||
1046 | // Debug values are not allowed to affect codegen. | |||
1047 | if (MI->isDebugValue()) { | |||
1048 | // Modify DBG_VALUE now that the value is in a spill slot. | |||
1049 | MachineBasicBlock *MBB = MI->getParent(); | |||
1050 | LLVM_DEBUG(dbgs() << "Modifying debug info due to spill:\t" << *MI)do { } while (false); | |||
1051 | buildDbgValueForSpill(*MBB, MI, *MI, StackSlot, Reg); | |||
1052 | MBB->erase(MI); | |||
1053 | continue; | |||
1054 | } | |||
1055 | ||||
1056 | assert(!MI->isDebugInstr() && "Did not expect to find a use in debug "((void)0) | |||
1057 | "instruction that isn't a DBG_VALUE")((void)0); | |||
1058 | ||||
1059 | // Ignore copies to/from snippets. We'll delete them. | |||
1060 | if (SnippetCopies.count(MI)) | |||
1061 | continue; | |||
1062 | ||||
1063 | // Stack slot accesses may coalesce away. | |||
1064 | if (coalesceStackAccess(MI, Reg)) | |||
1065 | continue; | |||
1066 | ||||
1067 | // Analyze instruction. | |||
1068 | SmallVector<std::pair<MachineInstr*, unsigned>, 8> Ops; | |||
1069 | VirtRegInfo RI = AnalyzeVirtRegInBundle(*MI, Reg, &Ops); | |||
1070 | ||||
1071 | // Find the slot index where this instruction reads and writes OldLI. | |||
1072 | // This is usually the def slot, except for tied early clobbers. | |||
1073 | SlotIndex Idx = LIS.getInstructionIndex(*MI).getRegSlot(); | |||
1074 | if (VNInfo *VNI = OldLI.getVNInfoAt(Idx.getRegSlot(true))) | |||
1075 | if (SlotIndex::isSameInstr(Idx, VNI->def)) | |||
1076 | Idx = VNI->def; | |||
1077 | ||||
1078 | // Check for a sibling copy. | |||
1079 | Register SibReg = isFullCopyOf(*MI, Reg); | |||
1080 | if (SibReg && isSibling(SibReg)) { | |||
1081 | // This may actually be a copy between snippets. | |||
1082 | if (isRegToSpill(SibReg)) { | |||
1083 | LLVM_DEBUG(dbgs() << "Found new snippet copy: " << *MI)do { } while (false); | |||
1084 | SnippetCopies.insert(MI); | |||
1085 | continue; | |||
1086 | } | |||
1087 | if (RI.Writes) { | |||
1088 | if (hoistSpillInsideBB(OldLI, *MI)) { | |||
1089 | // This COPY is now dead, the value is already in the stack slot. | |||
1090 | MI->getOperand(0).setIsDead(); | |||
1091 | DeadDefs.push_back(MI); | |||
1092 | continue; | |||
1093 | } | |||
1094 | } else { | |||
1095 | // This is a reload for a sib-reg copy. Drop spills downstream. | |||
1096 | LiveInterval &SibLI = LIS.getInterval(SibReg); | |||
1097 | eliminateRedundantSpills(SibLI, SibLI.getVNInfoAt(Idx)); | |||
1098 | // The COPY will fold to a reload below. | |||
1099 | } | |||
1100 | } | |||
1101 | ||||
1102 | // Attempt to fold memory ops. | |||
1103 | if (foldMemoryOperand(Ops)) | |||
1104 | continue; | |||
1105 | ||||
1106 | // Create a new virtual register for spill/fill. | |||
1107 | // FIXME: Infer regclass from instruction alone. | |||
1108 | Register NewVReg = Edit->createFrom(Reg); | |||
1109 | ||||
1110 | if (RI.Reads) | |||
1111 | insertReload(NewVReg, Idx, MI); | |||
1112 | ||||
1113 | // Rewrite instruction operands. | |||
1114 | bool hasLiveDef = false; | |||
1115 | for (const auto &OpPair : Ops) { | |||
1116 | MachineOperand &MO = OpPair.first->getOperand(OpPair.second); | |||
1117 | MO.setReg(NewVReg); | |||
1118 | if (MO.isUse()) { | |||
1119 | if (!OpPair.first->isRegTiedToDefOperand(OpPair.second)) | |||
1120 | MO.setIsKill(); | |||
1121 | } else { | |||
1122 | if (!MO.isDead()) | |||
1123 | hasLiveDef = true; | |||
1124 | } | |||
1125 | } | |||
1126 | LLVM_DEBUG(dbgs() << "\trewrite: " << Idx << '\t' << *MI << '\n')do { } while (false); | |||
1127 | ||||
1128 | // FIXME: Use a second vreg if instruction has no tied ops. | |||
1129 | if (RI.Writes) | |||
1130 | if (hasLiveDef) | |||
1131 | insertSpill(NewVReg, true, MI); | |||
1132 | } | |||
1133 | } | |||
1134 | ||||
1135 | /// spillAll - Spill all registers remaining after rematerialization. | |||
1136 | void InlineSpiller::spillAll() { | |||
1137 | // Update LiveStacks now that we are committed to spilling. | |||
1138 | if (StackSlot == VirtRegMap::NO_STACK_SLOT) { | |||
1139 | StackSlot = VRM.assignVirt2StackSlot(Original); | |||
1140 | StackInt = &LSS.getOrCreateInterval(StackSlot, MRI.getRegClass(Original)); | |||
1141 | StackInt->getNextValue(SlotIndex(), LSS.getVNInfoAllocator()); | |||
1142 | } else | |||
1143 | StackInt = &LSS.getInterval(StackSlot); | |||
1144 | ||||
1145 | if (Original != Edit->getReg()) | |||
1146 | VRM.assignVirt2StackSlot(Edit->getReg(), StackSlot); | |||
1147 | ||||
1148 | assert(StackInt->getNumValNums() == 1 && "Bad stack interval values")((void)0); | |||
1149 | for (Register Reg : RegsToSpill) | |||
1150 | StackInt->MergeSegmentsInAsValue(LIS.getInterval(Reg), | |||
1151 | StackInt->getValNumInfo(0)); | |||
1152 | LLVM_DEBUG(dbgs() << "Merged spilled regs: " << *StackInt << '\n')do { } while (false); | |||
1153 | ||||
1154 | // Spill around uses of all RegsToSpill. | |||
1155 | for (Register Reg : RegsToSpill) | |||
1156 | spillAroundUses(Reg); | |||
1157 | ||||
1158 | // Hoisted spills may cause dead code. | |||
1159 | if (!DeadDefs.empty()) { | |||
1160 | LLVM_DEBUG(dbgs() << "Eliminating " << DeadDefs.size() << " dead defs\n")do { } while (false); | |||
1161 | Edit->eliminateDeadDefs(DeadDefs, RegsToSpill, AA); | |||
1162 | } | |||
1163 | ||||
1164 | // Finally delete the SnippetCopies. | |||
1165 | for (Register Reg : RegsToSpill) { | |||
1166 | for (MachineRegisterInfo::reg_instr_iterator | |||
1167 | RI = MRI.reg_instr_begin(Reg), E = MRI.reg_instr_end(); | |||
1168 | RI != E; ) { | |||
1169 | MachineInstr &MI = *(RI++); | |||
1170 | assert(SnippetCopies.count(&MI) && "Remaining use wasn't a snippet copy")((void)0); | |||
1171 | // FIXME: Do this with a LiveRangeEdit callback. | |||
1172 | LIS.RemoveMachineInstrFromMaps(MI); | |||
1173 | MI.eraseFromParent(); | |||
1174 | } | |||
1175 | } | |||
1176 | ||||
1177 | // Delete all spilled registers. | |||
1178 | for (Register Reg : RegsToSpill) | |||
1179 | Edit->eraseVirtReg(Reg); | |||
1180 | } | |||
1181 | ||||
1182 | void InlineSpiller::spill(LiveRangeEdit &edit) { | |||
1183 | ++NumSpilledRanges; | |||
1184 | Edit = &edit; | |||
1185 | assert(!Register::isStackSlot(edit.getReg()) &&((void)0) | |||
1186 | "Trying to spill a stack slot.")((void)0); | |||
1187 | // Share a stack slot among all descendants of Original. | |||
1188 | Original = VRM.getOriginal(edit.getReg()); | |||
1189 | StackSlot = VRM.getStackSlot(Original); | |||
1190 | StackInt = nullptr; | |||
1191 | ||||
1192 | LLVM_DEBUG(dbgs() << "Inline spilling "do { } while (false) | |||
| ||||
1193 | << TRI.getRegClassName(MRI.getRegClass(edit.getReg()))do { } while (false) | |||
1194 | << ':' << edit.getParent() << "\nFrom original "do { } while (false) | |||
1195 | << printReg(Original) << '\n')do { } while (false); | |||
1196 | assert(edit.getParent().isSpillable() &&((void)0) | |||
1197 | "Attempting to spill already spilled value.")((void)0); | |||
1198 | assert(DeadDefs.empty() && "Previous spill didn't remove dead defs")((void)0); | |||
1199 | ||||
1200 | collectRegsToSpill(); | |||
1201 | reMaterializeAll(); | |||
1202 | ||||
1203 | // Remat may handle everything. | |||
1204 | if (!RegsToSpill.empty()) | |||
1205 | spillAll(); | |||
1206 | ||||
1207 | Edit->calculateRegClassAndHint(MF, VRAI); | |||
1208 | } | |||
1209 | ||||
1210 | /// Optimizations after all the reg selections and spills are done. | |||
1211 | void InlineSpiller::postOptimization() { HSpiller.hoistAllSpills(); } | |||
1212 | ||||
1213 | /// When a spill is inserted, add the spill to MergeableSpills map. | |||
1214 | void HoistSpillHelper::addToMergeableSpills(MachineInstr &Spill, int StackSlot, | |||
1215 | unsigned Original) { | |||
1216 | BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator(); | |||
1217 | LiveInterval &OrigLI = LIS.getInterval(Original); | |||
1218 | // save a copy of LiveInterval in StackSlotToOrigLI because the original | |||
1219 | // LiveInterval may be cleared after all its references are spilled. | |||
1220 | if (StackSlotToOrigLI.find(StackSlot) == StackSlotToOrigLI.end()) { | |||
1221 | auto LI = std::make_unique<LiveInterval>(OrigLI.reg(), OrigLI.weight()); | |||
1222 | LI->assign(OrigLI, Allocator); | |||
1223 | StackSlotToOrigLI[StackSlot] = std::move(LI); | |||
1224 | } | |||
1225 | SlotIndex Idx = LIS.getInstructionIndex(Spill); | |||
1226 | VNInfo *OrigVNI = StackSlotToOrigLI[StackSlot]->getVNInfoAt(Idx.getRegSlot()); | |||
1227 | std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI); | |||
1228 | MergeableSpills[MIdx].insert(&Spill); | |||
1229 | } | |||
1230 | ||||
1231 | /// When a spill is removed, remove the spill from MergeableSpills map. | |||
1232 | /// Return true if the spill is removed successfully. | |||
1233 | bool HoistSpillHelper::rmFromMergeableSpills(MachineInstr &Spill, | |||
1234 | int StackSlot) { | |||
1235 | auto It = StackSlotToOrigLI.find(StackSlot); | |||
1236 | if (It == StackSlotToOrigLI.end()) | |||
1237 | return false; | |||
1238 | SlotIndex Idx = LIS.getInstructionIndex(Spill); | |||
1239 | VNInfo *OrigVNI = It->second->getVNInfoAt(Idx.getRegSlot()); | |||
1240 | std::pair<int, VNInfo *> MIdx = std::make_pair(StackSlot, OrigVNI); | |||
1241 | return MergeableSpills[MIdx].erase(&Spill); | |||
1242 | } | |||
1243 | ||||
1244 | /// Check BB to see if it is a possible target BB to place a hoisted spill, | |||
1245 | /// i.e., there should be a living sibling of OrigReg at the insert point. | |||
1246 | bool HoistSpillHelper::isSpillCandBB(LiveInterval &OrigLI, VNInfo &OrigVNI, | |||
1247 | MachineBasicBlock &BB, Register &LiveReg) { | |||
1248 | SlotIndex Idx = IPA.getLastInsertPoint(OrigLI, BB); | |||
1249 | // The original def could be after the last insert point in the root block, | |||
1250 | // we can't hoist to here. | |||
1251 | if (Idx < OrigVNI.def) { | |||
1252 | // TODO: We could be better here. If LI is not alive in landing pad | |||
1253 | // we could hoist spill after LIP. | |||
1254 | LLVM_DEBUG(dbgs() << "can't spill in root block - def after LIP\n")do { } while (false); | |||
1255 | return false; | |||
1256 | } | |||
1257 | Register OrigReg = OrigLI.reg(); | |||
1258 | SmallSetVector<Register, 16> &Siblings = Virt2SiblingsMap[OrigReg]; | |||
1259 | assert(OrigLI.getVNInfoAt(Idx) == &OrigVNI && "Unexpected VNI")((void)0); | |||
1260 | ||||
1261 | for (const Register &SibReg : Siblings) { | |||
1262 | LiveInterval &LI = LIS.getInterval(SibReg); | |||
1263 | VNInfo *VNI = LI.getVNInfoAt(Idx); | |||
1264 | if (VNI) { | |||
1265 | LiveReg = SibReg; | |||
1266 | return true; | |||
1267 | } | |||
1268 | } | |||
1269 | return false; | |||
1270 | } | |||
1271 | ||||
1272 | /// Remove redundant spills in the same BB. Save those redundant spills in | |||
1273 | /// SpillsToRm, and save the spill to keep and its BB in SpillBBToSpill map. | |||
1274 | void HoistSpillHelper::rmRedundantSpills( | |||
1275 | SmallPtrSet<MachineInstr *, 16> &Spills, | |||
1276 | SmallVectorImpl<MachineInstr *> &SpillsToRm, | |||
1277 | DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) { | |||
1278 | // For each spill saw, check SpillBBToSpill[] and see if its BB already has | |||
1279 | // another spill inside. If a BB contains more than one spill, only keep the | |||
1280 | // earlier spill with smaller SlotIndex. | |||
1281 | for (const auto CurrentSpill : Spills) { | |||
1282 | MachineBasicBlock *Block = CurrentSpill->getParent(); | |||
1283 | MachineDomTreeNode *Node = MDT.getBase().getNode(Block); | |||
1284 | MachineInstr *PrevSpill = SpillBBToSpill[Node]; | |||
1285 | if (PrevSpill) { | |||
1286 | SlotIndex PIdx = LIS.getInstructionIndex(*PrevSpill); | |||
1287 | SlotIndex CIdx = LIS.getInstructionIndex(*CurrentSpill); | |||
1288 | MachineInstr *SpillToRm = (CIdx > PIdx) ? CurrentSpill : PrevSpill; | |||
1289 | MachineInstr *SpillToKeep = (CIdx > PIdx) ? PrevSpill : CurrentSpill; | |||
1290 | SpillsToRm.push_back(SpillToRm); | |||
1291 | SpillBBToSpill[MDT.getBase().getNode(Block)] = SpillToKeep; | |||
1292 | } else { | |||
1293 | SpillBBToSpill[MDT.getBase().getNode(Block)] = CurrentSpill; | |||
1294 | } | |||
1295 | } | |||
1296 | for (const auto SpillToRm : SpillsToRm) | |||
1297 | Spills.erase(SpillToRm); | |||
1298 | } | |||
1299 | ||||
1300 | /// Starting from \p Root find a top-down traversal order of the dominator | |||
1301 | /// tree to visit all basic blocks containing the elements of \p Spills. | |||
1302 | /// Redundant spills will be found and put into \p SpillsToRm at the same | |||
1303 | /// time. \p SpillBBToSpill will be populated as part of the process and | |||
1304 | /// maps a basic block to the first store occurring in the basic block. | |||
1305 | /// \post SpillsToRm.union(Spills\@post) == Spills\@pre | |||
1306 | void HoistSpillHelper::getVisitOrders( | |||
1307 | MachineBasicBlock *Root, SmallPtrSet<MachineInstr *, 16> &Spills, | |||
1308 | SmallVectorImpl<MachineDomTreeNode *> &Orders, | |||
1309 | SmallVectorImpl<MachineInstr *> &SpillsToRm, | |||
1310 | DenseMap<MachineDomTreeNode *, unsigned> &SpillsToKeep, | |||
1311 | DenseMap<MachineDomTreeNode *, MachineInstr *> &SpillBBToSpill) { | |||
1312 | // The set contains all the possible BB nodes to which we may hoist | |||
1313 | // original spills. | |||
1314 | SmallPtrSet<MachineDomTreeNode *, 8> WorkSet; | |||
1315 | // Save the BB nodes on the path from the first BB node containing | |||
1316 | // non-redundant spill to the Root node. | |||
1317 | SmallPtrSet<MachineDomTreeNode *, 8> NodesOnPath; | |||
1318 | // All the spills to be hoisted must originate from a single def instruction | |||
1319 | // to the OrigReg. It means the def instruction should dominate all the spills | |||
1320 | // to be hoisted. We choose the BB where the def instruction is located as | |||
1321 | // the Root. | |||
1322 | MachineDomTreeNode *RootIDomNode = MDT[Root]->getIDom(); | |||
1323 | // For every node on the dominator tree with spill, walk up on the dominator | |||
1324 | // tree towards the Root node until it is reached. If there is other node | |||
1325 | // containing spill in the middle of the path, the previous spill saw will | |||
1326 | // be redundant and the node containing it will be removed. All the nodes on | |||
1327 | // the path starting from the first node with non-redundant spill to the Root | |||
1328 | // node will be added to the WorkSet, which will contain all the possible | |||
1329 | // locations where spills may be hoisted to after the loop below is done. | |||
1330 | for (const auto Spill : Spills) { | |||
1331 | MachineBasicBlock *Block = Spill->getParent(); | |||
1332 | MachineDomTreeNode *Node = MDT[Block]; | |||
1333 | MachineInstr *SpillToRm = nullptr; | |||
1334 | while (Node != RootIDomNode) { | |||
1335 | // If Node dominates Block, and it already contains a spill, the spill in | |||
1336 | // Block will be redundant. | |||
1337 | if (Node != MDT[Block] && SpillBBToSpill[Node]) { | |||
1338 | SpillToRm = SpillBBToSpill[MDT[Block]]; | |||
1339 | break; | |||
1340 | /// If we see the Node already in WorkSet, the path from the Node to | |||
1341 | /// the Root node must already be traversed by another spill. | |||
1342 | /// Then no need to repeat. | |||
1343 | } else if (WorkSet.count(Node)) { | |||
1344 | break; | |||
1345 | } else { | |||
1346 | NodesOnPath.insert(Node); | |||
1347 | } | |||
1348 | Node = Node->getIDom(); | |||
1349 | } | |||
1350 | if (SpillToRm) { | |||
1351 | SpillsToRm.push_back(SpillToRm); | |||
1352 | } else { | |||
1353 | // Add a BB containing the original spills to SpillsToKeep -- i.e., | |||
1354 | // set the initial status before hoisting start. The value of BBs | |||
1355 | // containing original spills is set to 0, in order to descriminate | |||
1356 | // with BBs containing hoisted spills which will be inserted to | |||
1357 | // SpillsToKeep later during hoisting. | |||
1358 | SpillsToKeep[MDT[Block]] = 0; | |||
1359 | WorkSet.insert(NodesOnPath.begin(), NodesOnPath.end()); | |||
1360 | } | |||
1361 | NodesOnPath.clear(); | |||
1362 | } | |||
1363 | ||||
1364 | // Sort the nodes in WorkSet in top-down order and save the nodes | |||
1365 | // in Orders. Orders will be used for hoisting in runHoistSpills. | |||
1366 | unsigned idx = 0; | |||
1367 | Orders.push_back(MDT.getBase().getNode(Root)); | |||
1368 | do { | |||
1369 | MachineDomTreeNode *Node = Orders[idx++]; | |||
1370 | for (MachineDomTreeNode *Child : Node->children()) { | |||
1371 | if (WorkSet.count(Child)) | |||
1372 | Orders.push_back(Child); | |||
1373 | } | |||
1374 | } while (idx != Orders.size()); | |||
1375 | assert(Orders.size() == WorkSet.size() &&((void)0) | |||
1376 | "Orders have different size with WorkSet")((void)0); | |||
1377 | ||||
1378 | #ifndef NDEBUG1 | |||
1379 | LLVM_DEBUG(dbgs() << "Orders size is " << Orders.size() << "\n")do { } while (false); | |||
1380 | SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin(); | |||
1381 | for (; RIt != Orders.rend(); RIt++) | |||
1382 | LLVM_DEBUG(dbgs() << "BB" << (*RIt)->getBlock()->getNumber() << ",")do { } while (false); | |||
1383 | LLVM_DEBUG(dbgs() << "\n")do { } while (false); | |||
1384 | #endif | |||
1385 | } | |||
1386 | ||||
1387 | /// Try to hoist spills according to BB hotness. The spills to removed will | |||
1388 | /// be saved in \p SpillsToRm. The spills to be inserted will be saved in | |||
1389 | /// \p SpillsToIns. | |||
1390 | void HoistSpillHelper::runHoistSpills( | |||
1391 | LiveInterval &OrigLI, VNInfo &OrigVNI, | |||
1392 | SmallPtrSet<MachineInstr *, 16> &Spills, | |||
1393 | SmallVectorImpl<MachineInstr *> &SpillsToRm, | |||
1394 | DenseMap<MachineBasicBlock *, unsigned> &SpillsToIns) { | |||
1395 | // Visit order of dominator tree nodes. | |||
1396 | SmallVector<MachineDomTreeNode *, 32> Orders; | |||
1397 | // SpillsToKeep contains all the nodes where spills are to be inserted | |||
1398 | // during hoisting. If the spill to be inserted is an original spill | |||
1399 | // (not a hoisted one), the value of the map entry is 0. If the spill | |||
1400 | // is a hoisted spill, the value of the map entry is the VReg to be used | |||
1401 | // as the source of the spill. | |||
1402 | DenseMap<MachineDomTreeNode *, unsigned> SpillsToKeep; | |||
1403 | // Map from BB to the first spill inside of it. | |||
1404 | DenseMap<MachineDomTreeNode *, MachineInstr *> SpillBBToSpill; | |||
1405 | ||||
1406 | rmRedundantSpills(Spills, SpillsToRm, SpillBBToSpill); | |||
1407 | ||||
1408 | MachineBasicBlock *Root = LIS.getMBBFromIndex(OrigVNI.def); | |||
1409 | getVisitOrders(Root, Spills, Orders, SpillsToRm, SpillsToKeep, | |||
1410 | SpillBBToSpill); | |||
1411 | ||||
1412 | // SpillsInSubTreeMap keeps the map from a dom tree node to a pair of | |||
1413 | // nodes set and the cost of all the spills inside those nodes. | |||
1414 | // The nodes set are the locations where spills are to be inserted | |||
1415 | // in the subtree of current node. | |||
1416 | using NodesCostPair = | |||
1417 | std::pair<SmallPtrSet<MachineDomTreeNode *, 16>, BlockFrequency>; | |||
1418 | DenseMap<MachineDomTreeNode *, NodesCostPair> SpillsInSubTreeMap; | |||
1419 | ||||
1420 | // Iterate Orders set in reverse order, which will be a bottom-up order | |||
1421 | // in the dominator tree. Once we visit a dom tree node, we know its | |||
1422 | // children have already been visited and the spill locations in the | |||
1423 | // subtrees of all the children have been determined. | |||
1424 | SmallVector<MachineDomTreeNode *, 32>::reverse_iterator RIt = Orders.rbegin(); | |||
1425 | for (; RIt != Orders.rend(); RIt++) { | |||
1426 | MachineBasicBlock *Block = (*RIt)->getBlock(); | |||
1427 | ||||
1428 | // If Block contains an original spill, simply continue. | |||
1429 | if (SpillsToKeep.find(*RIt) != SpillsToKeep.end() && !SpillsToKeep[*RIt]) { | |||
1430 | SpillsInSubTreeMap[*RIt].first.insert(*RIt); | |||
1431 | // SpillsInSubTreeMap[*RIt].second contains the cost of spill. | |||
1432 | SpillsInSubTreeMap[*RIt].second = MBFI.getBlockFreq(Block); | |||
1433 | continue; | |||
1434 | } | |||
1435 | ||||
1436 | // Collect spills in subtree of current node (*RIt) to | |||
1437 | // SpillsInSubTreeMap[*RIt].first. | |||
1438 | for (MachineDomTreeNode *Child : (*RIt)->children()) { | |||
1439 | if (SpillsInSubTreeMap.find(Child) == SpillsInSubTreeMap.end()) | |||
1440 | continue; | |||
1441 | // The stmt "SpillsInSubTree = SpillsInSubTreeMap[*RIt].first" below | |||
1442 | // should be placed before getting the begin and end iterators of | |||
1443 | // SpillsInSubTreeMap[Child].first, or else the iterators may be | |||
1444 | // invalidated when SpillsInSubTreeMap[*RIt] is seen the first time | |||
1445 | // and the map grows and then the original buckets in the map are moved. | |||
1446 | SmallPtrSet<MachineDomTreeNode *, 16> &SpillsInSubTree = | |||
1447 | SpillsInSubTreeMap[*RIt].first; | |||
1448 | BlockFrequency &SubTreeCost = SpillsInSubTreeMap[*RIt].second; | |||
1449 | SubTreeCost += SpillsInSubTreeMap[Child].second; | |||
1450 | auto BI = SpillsInSubTreeMap[Child].first.begin(); | |||
1451 | auto EI = SpillsInSubTreeMap[Child].first.end(); | |||
1452 | SpillsInSubTree.insert(BI, EI); | |||
1453 | SpillsInSubTreeMap.erase(Child); | |||
1454 | } | |||
1455 | ||||
1456 | SmallPtrSet<MachineDomTreeNode *, 16> &SpillsInSubTree = | |||
1457 | SpillsInSubTreeMap[*RIt].first; | |||
1458 | BlockFrequency &SubTreeCost = SpillsInSubTreeMap[*RIt].second; | |||
1459 | // No spills in subtree, simply continue. | |||
1460 | if (SpillsInSubTree.empty()) | |||
1461 | continue; | |||
1462 | ||||
1463 | // Check whether Block is a possible candidate to insert spill. | |||
1464 | Register LiveReg; | |||
1465 | if (!isSpillCandBB(OrigLI, OrigVNI, *Block, LiveReg)) | |||
1466 | continue; | |||
1467 | ||||
1468 | // If there are multiple spills that could be merged, bias a little | |||
1469 | // to hoist the spill. | |||
1470 | BranchProbability MarginProb = (SpillsInSubTree.size() > 1) | |||
1471 | ? BranchProbability(9, 10) | |||
1472 | : BranchProbability(1, 1); | |||
1473 | if (SubTreeCost > MBFI.getBlockFreq(Block) * MarginProb) { | |||
1474 | // Hoist: Move spills to current Block. | |||
1475 | for (const auto SpillBB : SpillsInSubTree) { | |||
1476 | // When SpillBB is a BB contains original spill, insert the spill | |||
1477 | // to SpillsToRm. | |||
1478 | if (SpillsToKeep.find(SpillBB) != SpillsToKeep.end() && | |||
1479 | !SpillsToKeep[SpillBB]) { | |||
1480 | MachineInstr *SpillToRm = SpillBBToSpill[SpillBB]; | |||
1481 | SpillsToRm.push_back(SpillToRm); | |||
1482 | } | |||
1483 | // SpillBB will not contain spill anymore, remove it from SpillsToKeep. | |||
1484 | SpillsToKeep.erase(SpillBB); | |||
1485 | } | |||
1486 | // Current Block is the BB containing the new hoisted spill. Add it to | |||
1487 | // SpillsToKeep. LiveReg is the source of the new spill. | |||
1488 | SpillsToKeep[*RIt] = LiveReg; | |||
1489 | LLVM_DEBUG({do { } while (false) | |||
1490 | dbgs() << "spills in BB: ";do { } while (false) | |||
1491 | for (const auto Rspill : SpillsInSubTree)do { } while (false) | |||
1492 | dbgs() << Rspill->getBlock()->getNumber() << " ";do { } while (false) | |||
1493 | dbgs() << "were promoted to BB" << (*RIt)->getBlock()->getNumber()do { } while (false) | |||
1494 | << "\n";do { } while (false) | |||
1495 | })do { } while (false); | |||
1496 | SpillsInSubTree.clear(); | |||
1497 | SpillsInSubTree.insert(*RIt); | |||
1498 | SubTreeCost = MBFI.getBlockFreq(Block); | |||
1499 | } | |||
1500 | } | |||
1501 | // For spills in SpillsToKeep with LiveReg set (i.e., not original spill), | |||
1502 | // save them to SpillsToIns. | |||
1503 | for (const auto &Ent : SpillsToKeep) { | |||
1504 | if (Ent.second) | |||
1505 | SpillsToIns[Ent.first->getBlock()] = Ent.second; | |||
1506 | } | |||
1507 | } | |||
1508 | ||||
1509 | /// For spills with equal values, remove redundant spills and hoist those left | |||
1510 | /// to less hot spots. | |||
1511 | /// | |||
1512 | /// Spills with equal values will be collected into the same set in | |||
1513 | /// MergeableSpills when spill is inserted. These equal spills are originated | |||
1514 | /// from the same defining instruction and are dominated by the instruction. | |||
1515 | /// Before hoisting all the equal spills, redundant spills inside in the same | |||
1516 | /// BB are first marked to be deleted. Then starting from the spills left, walk | |||
1517 | /// up on the dominator tree towards the Root node where the define instruction | |||
1518 | /// is located, mark the dominated spills to be deleted along the way and | |||
1519 | /// collect the BB nodes on the path from non-dominated spills to the define | |||
1520 | /// instruction into a WorkSet. The nodes in WorkSet are the candidate places | |||
1521 | /// where we are considering to hoist the spills. We iterate the WorkSet in | |||
1522 | /// bottom-up order, and for each node, we will decide whether to hoist spills | |||
1523 | /// inside its subtree to that node. In this way, we can get benefit locally | |||
1524 | /// even if hoisting all the equal spills to one cold place is impossible. | |||
1525 | void HoistSpillHelper::hoistAllSpills() { | |||
1526 | SmallVector<Register, 4> NewVRegs; | |||
1527 | LiveRangeEdit Edit(nullptr, NewVRegs, MF, LIS, &VRM, this); | |||
1528 | ||||
1529 | for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) { | |||
1530 | Register Reg = Register::index2VirtReg(i); | |||
1531 | Register Original = VRM.getPreSplitReg(Reg); | |||
1532 | if (!MRI.def_empty(Reg)) | |||
1533 | Virt2SiblingsMap[Original].insert(Reg); | |||
1534 | } | |||
1535 | ||||
1536 | // Each entry in MergeableSpills contains a spill set with equal values. | |||
1537 | for (auto &Ent : MergeableSpills) { | |||
1538 | int Slot = Ent.first.first; | |||
1539 | LiveInterval &OrigLI = *StackSlotToOrigLI[Slot]; | |||
1540 | VNInfo *OrigVNI = Ent.first.second; | |||
1541 | SmallPtrSet<MachineInstr *, 16> &EqValSpills = Ent.second; | |||
1542 | if (Ent.second.empty()) | |||
1543 | continue; | |||
1544 | ||||
1545 | LLVM_DEBUG({do { } while (false) | |||
1546 | dbgs() << "\nFor Slot" << Slot << " and VN" << OrigVNI->id << ":\n"do { } while (false) | |||
1547 | << "Equal spills in BB: ";do { } while (false) | |||
1548 | for (const auto spill : EqValSpills)do { } while (false) | |||
1549 | dbgs() << spill->getParent()->getNumber() << " ";do { } while (false) | |||
1550 | dbgs() << "\n";do { } while (false) | |||
1551 | })do { } while (false); | |||
1552 | ||||
1553 | // SpillsToRm is the spill set to be removed from EqValSpills. | |||
1554 | SmallVector<MachineInstr *, 16> SpillsToRm; | |||
1555 | // SpillsToIns is the spill set to be newly inserted after hoisting. | |||
1556 | DenseMap<MachineBasicBlock *, unsigned> SpillsToIns; | |||
1557 | ||||
1558 | runHoistSpills(OrigLI, *OrigVNI, EqValSpills, SpillsToRm, SpillsToIns); | |||
1559 | ||||
1560 | LLVM_DEBUG({do { } while (false) | |||
1561 | dbgs() << "Finally inserted spills in BB: ";do { } while (false) | |||
1562 | for (const auto &Ispill : SpillsToIns)do { } while (false) | |||
1563 | dbgs() << Ispill.first->getNumber() << " ";do { } while (false) | |||
1564 | dbgs() << "\nFinally removed spills in BB: ";do { } while (false) | |||
1565 | for (const auto Rspill : SpillsToRm)do { } while (false) | |||
1566 | dbgs() << Rspill->getParent()->getNumber() << " ";do { } while (false) | |||
1567 | dbgs() << "\n";do { } while (false) | |||
1568 | })do { } while (false); | |||
1569 | ||||
1570 | // Stack live range update. | |||
1571 | LiveInterval &StackIntvl = LSS.getInterval(Slot); | |||
1572 | if (!SpillsToIns.empty() || !SpillsToRm.empty()) | |||
1573 | StackIntvl.MergeValueInAsValue(OrigLI, OrigVNI, | |||
1574 | StackIntvl.getValNumInfo(0)); | |||
1575 | ||||
1576 | // Insert hoisted spills. | |||
1577 | for (auto const &Insert : SpillsToIns) { | |||
1578 | MachineBasicBlock *BB = Insert.first; | |||
1579 | Register LiveReg = Insert.second; | |||
1580 | MachineBasicBlock::iterator MII = IPA.getLastInsertPointIter(OrigLI, *BB); | |||
1581 | MachineInstrSpan MIS(MII, BB); | |||
1582 | TII.storeRegToStackSlot(*BB, MII, LiveReg, false, Slot, | |||
1583 | MRI.getRegClass(LiveReg), &TRI); | |||
1584 | LIS.InsertMachineInstrRangeInMaps(MIS.begin(), MII); | |||
1585 | for (const MachineInstr &MI : make_range(MIS.begin(), MII)) | |||
1586 | getVDefInterval(MI, LIS); | |||
1587 | ++NumSpills; | |||
1588 | } | |||
1589 | ||||
1590 | // Remove redundant spills or change them to dead instructions. | |||
1591 | NumSpills -= SpillsToRm.size(); | |||
1592 | for (auto const RMEnt : SpillsToRm) { | |||
1593 | RMEnt->setDesc(TII.get(TargetOpcode::KILL)); | |||
1594 | for (unsigned i = RMEnt->getNumOperands(); i; --i) { | |||
1595 | MachineOperand &MO = RMEnt->getOperand(i - 1); | |||
1596 | if (MO.isReg() && MO.isImplicit() && MO.isDef() && !MO.isDead()) | |||
1597 | RMEnt->RemoveOperand(i - 1); | |||
1598 | } | |||
1599 | } | |||
1600 | Edit.eliminateDeadDefs(SpillsToRm, None, AA); | |||
1601 | } | |||
1602 | } | |||
1603 | ||||
1604 | /// For VirtReg clone, the \p New register should have the same physreg or | |||
1605 | /// stackslot as the \p old register. | |||
1606 | void HoistSpillHelper::LRE_DidCloneVirtReg(Register New, Register Old) { | |||
1607 | if (VRM.hasPhys(Old)) | |||
1608 | VRM.assignVirt2Phys(New, VRM.getPhys(Old)); | |||
1609 | else if (VRM.getStackSlot(Old) != VirtRegMap::NO_STACK_SLOT) | |||
1610 | VRM.assignVirt2StackSlot(New, VRM.getStackSlot(Old)); | |||
1611 | else | |||
1612 | llvm_unreachable("VReg should be assigned either physreg or stackslot")__builtin_unreachable(); | |||
1613 | if (VRM.hasShape(Old)) | |||
1614 | VRM.assignVirt2Shape(New, VRM.getShape(Old)); | |||
1615 | } |
1 | //===- llvm/ADT/STLExtras.h - Useful STL related functions ------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file contains some templates that are useful if you are working with the |
10 | // STL at all. |
11 | // |
12 | // No library is required when using these functions. |
13 | // |
14 | //===----------------------------------------------------------------------===// |
15 | |
16 | #ifndef LLVM_ADT_STLEXTRAS_H |
17 | #define LLVM_ADT_STLEXTRAS_H |
18 | |
19 | #include "llvm/ADT/Optional.h" |
20 | #include "llvm/ADT/STLForwardCompat.h" |
21 | #include "llvm/ADT/iterator.h" |
22 | #include "llvm/ADT/iterator_range.h" |
23 | #include "llvm/Config/abi-breaking.h" |
24 | #include "llvm/Support/ErrorHandling.h" |
25 | #include <algorithm> |
26 | #include <cassert> |
27 | #include <cstddef> |
28 | #include <cstdint> |
29 | #include <cstdlib> |
30 | #include <functional> |
31 | #include <initializer_list> |
32 | #include <iterator> |
33 | #include <limits> |
34 | #include <memory> |
35 | #include <tuple> |
36 | #include <type_traits> |
37 | #include <utility> |
38 | |
39 | #ifdef EXPENSIVE_CHECKS |
40 | #include <random> // for std::mt19937 |
41 | #endif |
42 | |
43 | namespace llvm { |
44 | |
45 | // Only used by compiler if both template types are the same. Useful when |
46 | // using SFINAE to test for the existence of member functions. |
47 | template <typename T, T> struct SameType; |
48 | |
49 | namespace detail { |
50 | |
51 | template <typename RangeT> |
52 | using IterOfRange = decltype(std::begin(std::declval<RangeT &>())); |
53 | |
54 | template <typename RangeT> |
55 | using ValueOfRange = typename std::remove_reference<decltype( |
56 | *std::begin(std::declval<RangeT &>()))>::type; |
57 | |
58 | } // end namespace detail |
59 | |
60 | //===----------------------------------------------------------------------===// |
61 | // Extra additions to <type_traits> |
62 | //===----------------------------------------------------------------------===// |
63 | |
64 | template <typename T> struct make_const_ptr { |
65 | using type = |
66 | typename std::add_pointer<typename std::add_const<T>::type>::type; |
67 | }; |
68 | |
69 | template <typename T> struct make_const_ref { |
70 | using type = typename std::add_lvalue_reference< |
71 | typename std::add_const<T>::type>::type; |
72 | }; |
73 | |
74 | namespace detail { |
75 | template <typename...> using void_t = void; |
76 | template <class, template <class...> class Op, class... Args> struct detector { |
77 | using value_t = std::false_type; |
78 | }; |
79 | template <template <class...> class Op, class... Args> |
80 | struct detector<void_t<Op<Args...>>, Op, Args...> { |
81 | using value_t = std::true_type; |
82 | }; |
83 | } // end namespace detail |
84 | |
85 | /// Detects if a given trait holds for some set of arguments 'Args'. |
86 | /// For example, the given trait could be used to detect if a given type |
87 | /// has a copy assignment operator: |
88 | /// template<class T> |
89 | /// using has_copy_assign_t = decltype(std::declval<T&>() |
90 | /// = std::declval<const T&>()); |
91 | /// bool fooHasCopyAssign = is_detected<has_copy_assign_t, FooClass>::value; |
92 | template <template <class...> class Op, class... Args> |
93 | using is_detected = typename detail::detector<void, Op, Args...>::value_t; |
94 | |
95 | namespace detail { |
96 | template <typename Callable, typename... Args> |
97 | using is_invocable = |
98 | decltype(std::declval<Callable &>()(std::declval<Args>()...)); |
99 | } // namespace detail |
100 | |
101 | /// Check if a Callable type can be invoked with the given set of arg types. |
102 | template <typename Callable, typename... Args> |
103 | using is_invocable = is_detected<detail::is_invocable, Callable, Args...>; |
104 | |
105 | /// This class provides various trait information about a callable object. |
106 | /// * To access the number of arguments: Traits::num_args |
107 | /// * To access the type of an argument: Traits::arg_t<Index> |
108 | /// * To access the type of the result: Traits::result_t |
109 | template <typename T, bool isClass = std::is_class<T>::value> |
110 | struct function_traits : public function_traits<decltype(&T::operator())> {}; |
111 | |
112 | /// Overload for class function types. |
113 | template <typename ClassType, typename ReturnType, typename... Args> |
114 | struct function_traits<ReturnType (ClassType::*)(Args...) const, false> { |
115 | /// The number of arguments to this function. |
116 | enum { num_args = sizeof...(Args) }; |
117 | |
118 | /// The result type of this function. |
119 | using result_t = ReturnType; |
120 | |
121 | /// The type of an argument to this function. |
122 | template <size_t Index> |
123 | using arg_t = typename std::tuple_element<Index, std::tuple<Args...>>::type; |
124 | }; |
125 | /// Overload for class function types. |
126 | template <typename ClassType, typename ReturnType, typename... Args> |
127 | struct function_traits<ReturnType (ClassType::*)(Args...), false> |
128 | : function_traits<ReturnType (ClassType::*)(Args...) const> {}; |
129 | /// Overload for non-class function types. |
130 | template <typename ReturnType, typename... Args> |
131 | struct function_traits<ReturnType (*)(Args...), false> { |
132 | /// The number of arguments to this function. |
133 | enum { num_args = sizeof...(Args) }; |
134 | |
135 | /// The result type of this function. |
136 | using result_t = ReturnType; |
137 | |
138 | /// The type of an argument to this function. |
139 | template <size_t i> |
140 | using arg_t = typename std::tuple_element<i, std::tuple<Args...>>::type; |
141 | }; |
142 | /// Overload for non-class function type references. |
143 | template <typename ReturnType, typename... Args> |
144 | struct function_traits<ReturnType (&)(Args...), false> |
145 | : public function_traits<ReturnType (*)(Args...)> {}; |
146 | |
147 | //===----------------------------------------------------------------------===// |
148 | // Extra additions to <functional> |
149 | //===----------------------------------------------------------------------===// |
150 | |
151 | template <class Ty> struct identity { |
152 | using argument_type = Ty; |
153 | |
154 | Ty &operator()(Ty &self) const { |
155 | return self; |
156 | } |
157 | const Ty &operator()(const Ty &self) const { |
158 | return self; |
159 | } |
160 | }; |
161 | |
162 | /// An efficient, type-erasing, non-owning reference to a callable. This is |
163 | /// intended for use as the type of a function parameter that is not used |
164 | /// after the function in question returns. |
165 | /// |
166 | /// This class does not own the callable, so it is not in general safe to store |
167 | /// a function_ref. |
168 | template<typename Fn> class function_ref; |
169 | |
170 | template<typename Ret, typename ...Params> |
171 | class function_ref<Ret(Params...)> { |
172 | Ret (*callback)(intptr_t callable, Params ...params) = nullptr; |
173 | intptr_t callable; |
174 | |
175 | template<typename Callable> |
176 | static Ret callback_fn(intptr_t callable, Params ...params) { |
177 | return (*reinterpret_cast<Callable*>(callable))( |
178 | std::forward<Params>(params)...); |
179 | } |
180 | |
181 | public: |
182 | function_ref() = default; |
183 | function_ref(std::nullptr_t) {} |
184 | |
185 | template <typename Callable> |
186 | function_ref( |
187 | Callable &&callable, |
188 | // This is not the copy-constructor. |
189 | std::enable_if_t<!std::is_same<remove_cvref_t<Callable>, |
190 | function_ref>::value> * = nullptr, |
191 | // Functor must be callable and return a suitable type. |
192 | std::enable_if_t<std::is_void<Ret>::value || |
193 | std::is_convertible<decltype(std::declval<Callable>()( |
194 | std::declval<Params>()...)), |
195 | Ret>::value> * = nullptr) |
196 | : callback(callback_fn<typename std::remove_reference<Callable>::type>), |
197 | callable(reinterpret_cast<intptr_t>(&callable)) {} |
198 | |
199 | Ret operator()(Params ...params) const { |
200 | return callback(callable, std::forward<Params>(params)...); |
201 | } |
202 | |
203 | explicit operator bool() const { return callback; } |
204 | }; |
205 | |
206 | //===----------------------------------------------------------------------===// |
207 | // Extra additions to <iterator> |
208 | //===----------------------------------------------------------------------===// |
209 | |
210 | namespace adl_detail { |
211 | |
212 | using std::begin; |
213 | |
214 | template <typename ContainerTy> |
215 | decltype(auto) adl_begin(ContainerTy &&container) { |
216 | return begin(std::forward<ContainerTy>(container)); |
217 | } |
218 | |
219 | using std::end; |
220 | |
221 | template <typename ContainerTy> |
222 | decltype(auto) adl_end(ContainerTy &&container) { |
223 | return end(std::forward<ContainerTy>(container)); |
224 | } |
225 | |
226 | using std::swap; |
227 | |
228 | template <typename T> |
229 | void adl_swap(T &&lhs, T &&rhs) noexcept(noexcept(swap(std::declval<T>(), |
230 | std::declval<T>()))) { |
231 | swap(std::forward<T>(lhs), std::forward<T>(rhs)); |
232 | } |
233 | |
234 | } // end namespace adl_detail |
235 | |
236 | template <typename ContainerTy> |
237 | decltype(auto) adl_begin(ContainerTy &&container) { |
238 | return adl_detail::adl_begin(std::forward<ContainerTy>(container)); |
239 | } |
240 | |
241 | template <typename ContainerTy> |
242 | decltype(auto) adl_end(ContainerTy &&container) { |
243 | return adl_detail::adl_end(std::forward<ContainerTy>(container)); |
244 | } |
245 | |
246 | template <typename T> |
247 | void adl_swap(T &&lhs, T &&rhs) noexcept( |
248 | noexcept(adl_detail::adl_swap(std::declval<T>(), std::declval<T>()))) { |
249 | adl_detail::adl_swap(std::forward<T>(lhs), std::forward<T>(rhs)); |
250 | } |
251 | |
252 | /// Test whether \p RangeOrContainer is empty. Similar to C++17 std::empty. |
253 | template <typename T> |
254 | constexpr bool empty(const T &RangeOrContainer) { |
255 | return adl_begin(RangeOrContainer) == adl_end(RangeOrContainer); |
256 | } |
257 | |
258 | /// Returns true if the given container only contains a single element. |
259 | template <typename ContainerTy> bool hasSingleElement(ContainerTy &&C) { |
260 | auto B = std::begin(C), E = std::end(C); |
261 | return B != E && std::next(B) == E; |
262 | } |
263 | |
264 | /// Return a range covering \p RangeOrContainer with the first N elements |
265 | /// excluded. |
266 | template <typename T> auto drop_begin(T &&RangeOrContainer, size_t N = 1) { |
267 | return make_range(std::next(adl_begin(RangeOrContainer), N), |
268 | adl_end(RangeOrContainer)); |
269 | } |
270 | |
271 | // mapped_iterator - This is a simple iterator adapter that causes a function to |
272 | // be applied whenever operator* is invoked on the iterator. |
273 | |
274 | template <typename ItTy, typename FuncTy, |
275 | typename FuncReturnTy = |
276 | decltype(std::declval<FuncTy>()(*std::declval<ItTy>()))> |
277 | class mapped_iterator |
278 | : public iterator_adaptor_base< |
279 | mapped_iterator<ItTy, FuncTy>, ItTy, |
280 | typename std::iterator_traits<ItTy>::iterator_category, |
281 | typename std::remove_reference<FuncReturnTy>::type> { |
282 | public: |
283 | mapped_iterator(ItTy U, FuncTy F) |
284 | : mapped_iterator::iterator_adaptor_base(std::move(U)), F(std::move(F)) {} |
285 | |
286 | ItTy getCurrent() { return this->I; } |
287 | |
288 | FuncReturnTy operator*() const { return F(*this->I); } |
289 | |
290 | private: |
291 | FuncTy F; |
292 | }; |
293 | |
294 | // map_iterator - Provide a convenient way to create mapped_iterators, just like |
295 | // make_pair is useful for creating pairs... |
296 | template <class ItTy, class FuncTy> |
297 | inline mapped_iterator<ItTy, FuncTy> map_iterator(ItTy I, FuncTy F) { |
298 | return mapped_iterator<ItTy, FuncTy>(std::move(I), std::move(F)); |
299 | } |
300 | |
301 | template <class ContainerTy, class FuncTy> |
302 | auto map_range(ContainerTy &&C, FuncTy F) { |
303 | return make_range(map_iterator(C.begin(), F), map_iterator(C.end(), F)); |
304 | } |
305 | |
306 | /// Helper to determine if type T has a member called rbegin(). |
307 | template <typename Ty> class has_rbegin_impl { |
308 | using yes = char[1]; |
309 | using no = char[2]; |
310 | |
311 | template <typename Inner> |
312 | static yes& test(Inner *I, decltype(I->rbegin()) * = nullptr); |
313 | |
314 | template <typename> |
315 | static no& test(...); |
316 | |
317 | public: |
318 | static const bool value = sizeof(test<Ty>(nullptr)) == sizeof(yes); |
319 | }; |
320 | |
321 | /// Metafunction to determine if T& or T has a member called rbegin(). |
322 | template <typename Ty> |
323 | struct has_rbegin : has_rbegin_impl<typename std::remove_reference<Ty>::type> { |
324 | }; |
325 | |
326 | // Returns an iterator_range over the given container which iterates in reverse. |
327 | // Note that the container must have rbegin()/rend() methods for this to work. |
328 | template <typename ContainerTy> |
329 | auto reverse(ContainerTy &&C, |
330 | std::enable_if_t<has_rbegin<ContainerTy>::value> * = nullptr) { |
331 | return make_range(C.rbegin(), C.rend()); |
332 | } |
333 | |
334 | // Returns a std::reverse_iterator wrapped around the given iterator. |
335 | template <typename IteratorTy> |
336 | std::reverse_iterator<IteratorTy> make_reverse_iterator(IteratorTy It) { |
337 | return std::reverse_iterator<IteratorTy>(It); |
338 | } |
339 | |
340 | // Returns an iterator_range over the given container which iterates in reverse. |
341 | // Note that the container must have begin()/end() methods which return |
342 | // bidirectional iterators for this to work. |
343 | template <typename ContainerTy> |
344 | auto reverse(ContainerTy &&C, |
345 | std::enable_if_t<!has_rbegin<ContainerTy>::value> * = nullptr) { |
346 | return make_range(llvm::make_reverse_iterator(std::end(C)), |
347 | llvm::make_reverse_iterator(std::begin(C))); |
348 | } |
349 | |
350 | /// An iterator adaptor that filters the elements of given inner iterators. |
351 | /// |
352 | /// The predicate parameter should be a callable object that accepts the wrapped |
353 | /// iterator's reference type and returns a bool. When incrementing or |
354 | /// decrementing the iterator, it will call the predicate on each element and |
355 | /// skip any where it returns false. |
356 | /// |
357 | /// \code |
358 | /// int A[] = { 1, 2, 3, 4 }; |
359 | /// auto R = make_filter_range(A, [](int N) { return N % 2 == 1; }); |
360 | /// // R contains { 1, 3 }. |
361 | /// \endcode |
362 | /// |
363 | /// Note: filter_iterator_base implements support for forward iteration. |
364 | /// filter_iterator_impl exists to provide support for bidirectional iteration, |
365 | /// conditional on whether the wrapped iterator supports it. |
366 | template <typename WrappedIteratorT, typename PredicateT, typename IterTag> |
367 | class filter_iterator_base |
368 | : public iterator_adaptor_base< |
369 | filter_iterator_base<WrappedIteratorT, PredicateT, IterTag>, |
370 | WrappedIteratorT, |
371 | typename std::common_type< |
372 | IterTag, typename std::iterator_traits< |
373 | WrappedIteratorT>::iterator_category>::type> { |
374 | using BaseT = iterator_adaptor_base< |
375 | filter_iterator_base<WrappedIteratorT, PredicateT, IterTag>, |
376 | WrappedIteratorT, |
377 | typename std::common_type< |
378 | IterTag, typename std::iterator_traits< |
379 | WrappedIteratorT>::iterator_category>::type>; |
380 | |
381 | protected: |
382 | WrappedIteratorT End; |
383 | PredicateT Pred; |
384 | |
385 | void findNextValid() { |
386 | while (this->I != End && !Pred(*this->I)) |
387 | BaseT::operator++(); |
388 | } |
389 | |
390 | // Construct the iterator. The begin iterator needs to know where the end |
391 | // is, so that it can properly stop when it gets there. The end iterator only |
392 | // needs the predicate to support bidirectional iteration. |
393 | filter_iterator_base(WrappedIteratorT Begin, WrappedIteratorT End, |
394 | PredicateT Pred) |
395 | : BaseT(Begin), End(End), Pred(Pred) { |
396 | findNextValid(); |
397 | } |
398 | |
399 | public: |
400 | using BaseT::operator++; |
401 | |
402 | filter_iterator_base &operator++() { |
403 | BaseT::operator++(); |
404 | findNextValid(); |
405 | return *this; |
406 | } |
407 | }; |
408 | |
409 | /// Specialization of filter_iterator_base for forward iteration only. |
410 | template <typename WrappedIteratorT, typename PredicateT, |
411 | typename IterTag = std::forward_iterator_tag> |
412 | class filter_iterator_impl |
413 | : public filter_iterator_base<WrappedIteratorT, PredicateT, IterTag> { |
414 | using BaseT = filter_iterator_base<WrappedIteratorT, PredicateT, IterTag>; |
415 | |
416 | public: |
417 | filter_iterator_impl(WrappedIteratorT Begin, WrappedIteratorT End, |
418 | PredicateT Pred) |
419 | : BaseT(Begin, End, Pred) {} |
420 | }; |
421 | |
422 | /// Specialization of filter_iterator_base for bidirectional iteration. |
423 | template <typename WrappedIteratorT, typename PredicateT> |
424 | class filter_iterator_impl<WrappedIteratorT, PredicateT, |
425 | std::bidirectional_iterator_tag> |
426 | : public filter_iterator_base<WrappedIteratorT, PredicateT, |
427 | std::bidirectional_iterator_tag> { |
428 | using BaseT = filter_iterator_base<WrappedIteratorT, PredicateT, |
429 | std::bidirectional_iterator_tag>; |
430 | void findPrevValid() { |
431 | while (!this->Pred(*this->I)) |
432 | BaseT::operator--(); |
433 | } |
434 | |
435 | public: |
436 | using BaseT::operator--; |
437 | |
438 | filter_iterator_impl(WrappedIteratorT Begin, WrappedIteratorT End, |
439 | PredicateT Pred) |
440 | : BaseT(Begin, End, Pred) {} |
441 | |
442 | filter_iterator_impl &operator--() { |
443 | BaseT::operator--(); |
444 | findPrevValid(); |
445 | return *this; |
446 | } |
447 | }; |
448 | |
449 | namespace detail { |
450 | |
451 | template <bool is_bidirectional> struct fwd_or_bidi_tag_impl { |
452 | using type = std::forward_iterator_tag; |
453 | }; |
454 | |
455 | template <> struct fwd_or_bidi_tag_impl<true> { |
456 | using type = std::bidirectional_iterator_tag; |
457 | }; |
458 | |
459 | /// Helper which sets its type member to forward_iterator_tag if the category |
460 | /// of \p IterT does not derive from bidirectional_iterator_tag, and to |
461 | /// bidirectional_iterator_tag otherwise. |
462 | template <typename IterT> struct fwd_or_bidi_tag { |
463 | using type = typename fwd_or_bidi_tag_impl<std::is_base_of< |
464 | std::bidirectional_iterator_tag, |
465 | typename std::iterator_traits<IterT>::iterator_category>::value>::type; |
466 | }; |
467 | |
468 | } // namespace detail |
469 | |
470 | /// Defines filter_iterator to a suitable specialization of |
471 | /// filter_iterator_impl, based on the underlying iterator's category. |
472 | template <typename WrappedIteratorT, typename PredicateT> |
473 | using filter_iterator = filter_iterator_impl< |
474 | WrappedIteratorT, PredicateT, |
475 | typename detail::fwd_or_bidi_tag<WrappedIteratorT>::type>; |
476 | |
477 | /// Convenience function that takes a range of elements and a predicate, |
478 | /// and return a new filter_iterator range. |
479 | /// |
480 | /// FIXME: Currently if RangeT && is a rvalue reference to a temporary, the |
481 | /// lifetime of that temporary is not kept by the returned range object, and the |
482 | /// temporary is going to be dropped on the floor after the make_iterator_range |
483 | /// full expression that contains this function call. |
484 | template <typename RangeT, typename PredicateT> |
485 | iterator_range<filter_iterator<detail::IterOfRange<RangeT>, PredicateT>> |
486 | make_filter_range(RangeT &&Range, PredicateT Pred) { |
487 | using FilterIteratorT = |
488 | filter_iterator<detail::IterOfRange<RangeT>, PredicateT>; |
489 | return make_range( |
490 | FilterIteratorT(std::begin(std::forward<RangeT>(Range)), |
491 | std::end(std::forward<RangeT>(Range)), Pred), |
492 | FilterIteratorT(std::end(std::forward<RangeT>(Range)), |
493 | std::end(std::forward<RangeT>(Range)), Pred)); |
494 | } |
495 | |
496 | /// A pseudo-iterator adaptor that is designed to implement "early increment" |
497 | /// style loops. |
498 | /// |
499 | /// This is *not a normal iterator* and should almost never be used directly. It |
500 | /// is intended primarily to be used with range based for loops and some range |
501 | /// algorithms. |
502 | /// |
503 | /// The iterator isn't quite an `OutputIterator` or an `InputIterator` but |
504 | /// somewhere between them. The constraints of these iterators are: |
505 | /// |
506 | /// - On construction or after being incremented, it is comparable and |
507 | /// dereferencable. It is *not* incrementable. |
508 | /// - After being dereferenced, it is neither comparable nor dereferencable, it |
509 | /// is only incrementable. |
510 | /// |
511 | /// This means you can only dereference the iterator once, and you can only |
512 | /// increment it once between dereferences. |
513 | template <typename WrappedIteratorT> |
514 | class early_inc_iterator_impl |
515 | : public iterator_adaptor_base<early_inc_iterator_impl<WrappedIteratorT>, |
516 | WrappedIteratorT, std::input_iterator_tag> { |
517 | using BaseT = |
518 | iterator_adaptor_base<early_inc_iterator_impl<WrappedIteratorT>, |
519 | WrappedIteratorT, std::input_iterator_tag>; |
520 | |
521 | using PointerT = typename std::iterator_traits<WrappedIteratorT>::pointer; |
522 | |
523 | protected: |
524 | #if LLVM_ENABLE_ABI_BREAKING_CHECKS0 |
525 | bool IsEarlyIncremented = false; |
526 | #endif |
527 | |
528 | public: |
529 | early_inc_iterator_impl(WrappedIteratorT I) : BaseT(I) {} |
530 | |
531 | using BaseT::operator*; |
532 | decltype(*std::declval<WrappedIteratorT>()) operator*() { |
533 | #if LLVM_ENABLE_ABI_BREAKING_CHECKS0 |
534 | assert(!IsEarlyIncremented && "Cannot dereference twice!")((void)0); |
535 | IsEarlyIncremented = true; |
536 | #endif |
537 | return *(this->I)++; |
538 | } |
539 | |
540 | using BaseT::operator++; |
541 | early_inc_iterator_impl &operator++() { |
542 | #if LLVM_ENABLE_ABI_BREAKING_CHECKS0 |
543 | assert(IsEarlyIncremented && "Cannot increment before dereferencing!")((void)0); |
544 | IsEarlyIncremented = false; |
545 | #endif |
546 | return *this; |
547 | } |
548 | |
549 | friend bool operator==(const early_inc_iterator_impl &LHS, |
550 | const early_inc_iterator_impl &RHS) { |
551 | #if LLVM_ENABLE_ABI_BREAKING_CHECKS0 |
552 | assert(!LHS.IsEarlyIncremented && "Cannot compare after dereferencing!")((void)0); |
553 | #endif |
554 | return (const BaseT &)LHS == (const BaseT &)RHS; |
555 | } |
556 | }; |
557 | |
558 | /// Make a range that does early increment to allow mutation of the underlying |
559 | /// range without disrupting iteration. |
560 | /// |
561 | /// The underlying iterator will be incremented immediately after it is |
562 | /// dereferenced, allowing deletion of the current node or insertion of nodes to |
563 | /// not disrupt iteration provided they do not invalidate the *next* iterator -- |
564 | /// the current iterator can be invalidated. |
565 | /// |
566 | /// This requires a very exact pattern of use that is only really suitable to |
567 | /// range based for loops and other range algorithms that explicitly guarantee |
568 | /// to dereference exactly once each element, and to increment exactly once each |
569 | /// element. |
570 | template <typename RangeT> |
571 | iterator_range<early_inc_iterator_impl<detail::IterOfRange<RangeT>>> |
572 | make_early_inc_range(RangeT &&Range) { |
573 | using EarlyIncIteratorT = |
574 | early_inc_iterator_impl<detail::IterOfRange<RangeT>>; |
575 | return make_range(EarlyIncIteratorT(std::begin(std::forward<RangeT>(Range))), |
576 | EarlyIncIteratorT(std::end(std::forward<RangeT>(Range)))); |
577 | } |
578 | |
579 | // forward declarations required by zip_shortest/zip_first/zip_longest |
580 | template <typename R, typename UnaryPredicate> |
581 | bool all_of(R &&range, UnaryPredicate P); |
582 | template <typename R, typename UnaryPredicate> |
583 | bool any_of(R &&range, UnaryPredicate P); |
584 | |
585 | namespace detail { |
586 | |
587 | using std::declval; |
588 | |
589 | // We have to alias this since inlining the actual type at the usage site |
590 | // in the parameter list of iterator_facade_base<> below ICEs MSVC 2017. |
591 | template<typename... Iters> struct ZipTupleType { |
592 | using type = std::tuple<decltype(*declval<Iters>())...>; |
593 | }; |
594 | |
595 | template <typename ZipType, typename... Iters> |
596 | using zip_traits = iterator_facade_base< |
597 | ZipType, typename std::common_type<std::bidirectional_iterator_tag, |
598 | typename std::iterator_traits< |
599 | Iters>::iterator_category...>::type, |
600 | // ^ TODO: Implement random access methods. |
601 | typename ZipTupleType<Iters...>::type, |
602 | typename std::iterator_traits<typename std::tuple_element< |
603 | 0, std::tuple<Iters...>>::type>::difference_type, |
604 | // ^ FIXME: This follows boost::make_zip_iterator's assumption that all |
605 | // inner iterators have the same difference_type. It would fail if, for |
606 | // instance, the second field's difference_type were non-numeric while the |
607 | // first is. |
608 | typename ZipTupleType<Iters...>::type *, |
609 | typename ZipTupleType<Iters...>::type>; |
610 | |
611 | template <typename ZipType, typename... Iters> |
612 | struct zip_common : public zip_traits<ZipType, Iters...> { |
613 | using Base = zip_traits<ZipType, Iters...>; |
614 | using value_type = typename Base::value_type; |
615 | |
616 | std::tuple<Iters...> iterators; |
617 | |
618 | protected: |
619 | template <size_t... Ns> value_type deref(std::index_sequence<Ns...>) const { |
620 | return value_type(*std::get<Ns>(iterators)...); |
621 | } |
622 | |
623 | template <size_t... Ns> |
624 | decltype(iterators) tup_inc(std::index_sequence<Ns...>) const { |
625 | return std::tuple<Iters...>(std::next(std::get<Ns>(iterators))...); |
626 | } |
627 | |
628 | template <size_t... Ns> |
629 | decltype(iterators) tup_dec(std::index_sequence<Ns...>) const { |
630 | return std::tuple<Iters...>(std::prev(std::get<Ns>(iterators))...); |
631 | } |
632 | |
633 | public: |
634 | zip_common(Iters &&... ts) : iterators(std::forward<Iters>(ts)...) {} |
635 | |
636 | value_type operator*() { return deref(std::index_sequence_for<Iters...>{}); } |
637 | |
638 | const value_type operator*() const { |
639 | return deref(std::index_sequence_for<Iters...>{}); |
640 | } |
641 | |
642 | ZipType &operator++() { |
643 | iterators = tup_inc(std::index_sequence_for<Iters...>{}); |
644 | return *reinterpret_cast<ZipType *>(this); |
645 | } |
646 | |
647 | ZipType &operator--() { |
648 | static_assert(Base::IsBidirectional, |
649 | "All inner iterators must be at least bidirectional."); |
650 | iterators = tup_dec(std::index_sequence_for<Iters...>{}); |
651 | return *reinterpret_cast<ZipType *>(this); |
652 | } |
653 | }; |
654 | |
655 | template <typename... Iters> |
656 | struct zip_first : public zip_common<zip_first<Iters...>, Iters...> { |
657 | using Base = zip_common<zip_first<Iters...>, Iters...>; |
658 | |
659 | bool operator==(const zip_first<Iters...> &other) const { |
660 | return std::get<0>(this->iterators) == std::get<0>(other.iterators); |
661 | } |
662 | |
663 | zip_first(Iters &&... ts) : Base(std::forward<Iters>(ts)...) {} |
664 | }; |
665 | |
666 | template <typename... Iters> |
667 | class zip_shortest : public zip_common<zip_shortest<Iters...>, Iters...> { |
668 | template <size_t... Ns> |
669 | bool test(const zip_shortest<Iters...> &other, |
670 | std::index_sequence<Ns...>) const { |
671 | return all_of(std::initializer_list<bool>{std::get<Ns>(this->iterators) != |
672 | std::get<Ns>(other.iterators)...}, |
673 | identity<bool>{}); |
674 | } |
675 | |
676 | public: |
677 | using Base = zip_common<zip_shortest<Iters...>, Iters...>; |
678 | |
679 | zip_shortest(Iters &&... ts) : Base(std::forward<Iters>(ts)...) {} |
680 | |
681 | bool operator==(const zip_shortest<Iters...> &other) const { |
682 | return !test(other, std::index_sequence_for<Iters...>{}); |
683 | } |
684 | }; |
685 | |
686 | template <template <typename...> class ItType, typename... Args> class zippy { |
687 | public: |
688 | using iterator = ItType<decltype(std::begin(std::declval<Args>()))...>; |
689 | using iterator_category = typename iterator::iterator_category; |
690 | using value_type = typename iterator::value_type; |
691 | using difference_type = typename iterator::difference_type; |
692 | using pointer = typename iterator::pointer; |
693 | using reference = typename iterator::reference; |
694 | |
695 | private: |
696 | std::tuple<Args...> ts; |
697 | |
698 | template <size_t... Ns> |
699 | iterator begin_impl(std::index_sequence<Ns...>) const { |
700 | return iterator(std::begin(std::get<Ns>(ts))...); |
701 | } |
702 | template <size_t... Ns> iterator end_impl(std::index_sequence<Ns...>) const { |
703 | return iterator(std::end(std::get<Ns>(ts))...); |
704 | } |
705 | |
706 | public: |
707 | zippy(Args &&... ts_) : ts(std::forward<Args>(ts_)...) {} |
708 | |
709 | iterator begin() const { |
710 | return begin_impl(std::index_sequence_for<Args...>{}); |
711 | } |
712 | iterator end() const { return end_impl(std::index_sequence_for<Args...>{}); } |
713 | }; |
714 | |
715 | } // end namespace detail |
716 | |
717 | /// zip iterator for two or more iteratable types. |
718 | template <typename T, typename U, typename... Args> |
719 | detail::zippy<detail::zip_shortest, T, U, Args...> zip(T &&t, U &&u, |
720 | Args &&... args) { |
721 | return detail::zippy<detail::zip_shortest, T, U, Args...>( |
722 | std::forward<T>(t), std::forward<U>(u), std::forward<Args>(args)...); |
723 | } |
724 | |
725 | /// zip iterator that, for the sake of efficiency, assumes the first iteratee to |
726 | /// be the shortest. |
727 | template <typename T, typename U, typename... Args> |
728 | detail::zippy<detail::zip_first, T, U, Args...> zip_first(T &&t, U &&u, |
729 | Args &&... args) { |
730 | return detail::zippy<detail::zip_first, T, U, Args...>( |
731 | std::forward<T>(t), std::forward<U>(u), std::forward<Args>(args)...); |
732 | } |
733 | |
734 | namespace detail { |
735 | template <typename Iter> |
736 | Iter next_or_end(const Iter &I, const Iter &End) { |
737 | if (I == End) |
738 | return End; |
739 | return std::next(I); |
740 | } |
741 | |
742 | template <typename Iter> |
743 | auto deref_or_none(const Iter &I, const Iter &End) -> llvm::Optional< |
744 | std::remove_const_t<std::remove_reference_t<decltype(*I)>>> { |
745 | if (I == End) |
746 | return None; |
747 | return *I; |
748 | } |
749 | |
750 | template <typename Iter> struct ZipLongestItemType { |
751 | using type = |
752 | llvm::Optional<typename std::remove_const<typename std::remove_reference< |
753 | decltype(*std::declval<Iter>())>::type>::type>; |
754 | }; |
755 | |
756 | template <typename... Iters> struct ZipLongestTupleType { |
757 | using type = std::tuple<typename ZipLongestItemType<Iters>::type...>; |
758 | }; |
759 | |
760 | template <typename... Iters> |
761 | class zip_longest_iterator |
762 | : public iterator_facade_base< |
763 | zip_longest_iterator<Iters...>, |
764 | typename std::common_type< |
765 | std::forward_iterator_tag, |
766 | typename std::iterator_traits<Iters>::iterator_category...>::type, |
767 | typename ZipLongestTupleType<Iters...>::type, |
768 | typename std::iterator_traits<typename std::tuple_element< |
769 | 0, std::tuple<Iters...>>::type>::difference_type, |
770 | typename ZipLongestTupleType<Iters...>::type *, |
771 | typename ZipLongestTupleType<Iters...>::type> { |
772 | public: |
773 | using value_type = typename ZipLongestTupleType<Iters...>::type; |
774 | |
775 | private: |
776 | std::tuple<Iters...> iterators; |
777 | std::tuple<Iters...> end_iterators; |
778 | |
779 | template <size_t... Ns> |
780 | bool test(const zip_longest_iterator<Iters...> &other, |
781 | std::index_sequence<Ns...>) const { |
782 | return llvm::any_of( |
783 | std::initializer_list<bool>{std::get<Ns>(this->iterators) != |
784 | std::get<Ns>(other.iterators)...}, |
785 | identity<bool>{}); |
786 | } |
787 | |
788 | template <size_t... Ns> value_type deref(std::index_sequence<Ns...>) const { |
789 | return value_type( |
790 | deref_or_none(std::get<Ns>(iterators), std::get<Ns>(end_iterators))...); |
791 | } |
792 | |
793 | template <size_t... Ns> |
794 | decltype(iterators) tup_inc(std::index_sequence<Ns...>) const { |
795 | return std::tuple<Iters...>( |
796 | next_or_end(std::get<Ns>(iterators), std::get<Ns>(end_iterators))...); |
797 | } |
798 | |
799 | public: |
800 | zip_longest_iterator(std::pair<Iters &&, Iters &&>... ts) |
801 | : iterators(std::forward<Iters>(ts.first)...), |
802 | end_iterators(std::forward<Iters>(ts.second)...) {} |
803 | |
804 | value_type operator*() { return deref(std::index_sequence_for<Iters...>{}); } |
805 | |
806 | value_type operator*() const { |
807 | return deref(std::index_sequence_for<Iters...>{}); |
808 | } |
809 | |
810 | zip_longest_iterator<Iters...> &operator++() { |
811 | iterators = tup_inc(std::index_sequence_for<Iters...>{}); |
812 | return *this; |
813 | } |
814 | |
815 | bool operator==(const zip_longest_iterator<Iters...> &other) const { |
816 | return !test(other, std::index_sequence_for<Iters...>{}); |
817 | } |
818 | }; |
819 | |
820 | template <typename... Args> class zip_longest_range { |
821 | public: |
822 | using iterator = |
823 | zip_longest_iterator<decltype(adl_begin(std::declval<Args>()))...>; |
824 | using iterator_category = typename iterator::iterator_category; |
825 | using value_type = typename iterator::value_type; |
826 | using difference_type = typename iterator::difference_type; |
827 | using pointer = typename iterator::pointer; |
828 | using reference = typename iterator::reference; |
829 | |
830 | private: |
831 | std::tuple<Args...> ts; |
832 | |
833 | template <size_t... Ns> |
834 | iterator begin_impl(std::index_sequence<Ns...>) const { |
835 | return iterator(std::make_pair(adl_begin(std::get<Ns>(ts)), |
836 | adl_end(std::get<Ns>(ts)))...); |
837 | } |
838 | |
839 | template <size_t... Ns> iterator end_impl(std::index_sequence<Ns...>) const { |
840 | return iterator(std::make_pair(adl_end(std::get<Ns>(ts)), |
841 | adl_end(std::get<Ns>(ts)))...); |
842 | } |
843 | |
844 | public: |
845 | zip_longest_range(Args &&... ts_) : ts(std::forward<Args>(ts_)...) {} |
846 | |
847 | iterator begin() const { |
848 | return begin_impl(std::index_sequence_for<Args...>{}); |
849 | } |
850 | iterator end() const { return end_impl(std::index_sequence_for<Args...>{}); } |
851 | }; |
852 | } // namespace detail |
853 | |
854 | /// Iterate over two or more iterators at the same time. Iteration continues |
855 | /// until all iterators reach the end. The llvm::Optional only contains a value |
856 | /// if the iterator has not reached the end. |
857 | template <typename T, typename U, typename... Args> |
858 | detail::zip_longest_range<T, U, Args...> zip_longest(T &&t, U &&u, |
859 | Args &&... args) { |
860 | return detail::zip_longest_range<T, U, Args...>( |
861 | std::forward<T>(t), std::forward<U>(u), std::forward<Args>(args)...); |
862 | } |
863 | |
864 | /// Iterator wrapper that concatenates sequences together. |
865 | /// |
866 | /// This can concatenate different iterators, even with different types, into |
867 | /// a single iterator provided the value types of all the concatenated |
868 | /// iterators expose `reference` and `pointer` types that can be converted to |
869 | /// `ValueT &` and `ValueT *` respectively. It doesn't support more |
870 | /// interesting/customized pointer or reference types. |
871 | /// |
872 | /// Currently this only supports forward or higher iterator categories as |
873 | /// inputs and always exposes a forward iterator interface. |
874 | template <typename ValueT, typename... IterTs> |
875 | class concat_iterator |
876 | : public iterator_facade_base<concat_iterator<ValueT, IterTs...>, |
877 | std::forward_iterator_tag, ValueT> { |
878 | using BaseT = typename concat_iterator::iterator_facade_base; |
879 | |
880 | /// We store both the current and end iterators for each concatenated |
881 | /// sequence in a tuple of pairs. |
882 | /// |
883 | /// Note that something like iterator_range seems nice at first here, but the |
884 | /// range properties are of little benefit and end up getting in the way |
885 | /// because we need to do mutation on the current iterators. |
886 | std::tuple<IterTs...> Begins; |
887 | std::tuple<IterTs...> Ends; |
888 | |
889 | /// Attempts to increment a specific iterator. |
890 | /// |
891 | /// Returns true if it was able to increment the iterator. Returns false if |
892 | /// the iterator is already at the end iterator. |
893 | template <size_t Index> bool incrementHelper() { |
894 | auto &Begin = std::get<Index>(Begins); |
895 | auto &End = std::get<Index>(Ends); |
896 | if (Begin == End) |
897 | return false; |
898 | |
899 | ++Begin; |
900 | return true; |
901 | } |
902 | |
903 | /// Increments the first non-end iterator. |
904 | /// |
905 | /// It is an error to call this with all iterators at the end. |
906 | template <size_t... Ns> void increment(std::index_sequence<Ns...>) { |
907 | // Build a sequence of functions to increment each iterator if possible. |
908 | bool (concat_iterator::*IncrementHelperFns[])() = { |
909 | &concat_iterator::incrementHelper<Ns>...}; |
910 | |
911 | // Loop over them, and stop as soon as we succeed at incrementing one. |
912 | for (auto &IncrementHelperFn : IncrementHelperFns) |
913 | if ((this->*IncrementHelperFn)()) |
914 | return; |
915 | |
916 | llvm_unreachable("Attempted to increment an end concat iterator!")__builtin_unreachable(); |
917 | } |
918 | |
919 | /// Returns null if the specified iterator is at the end. Otherwise, |
920 | /// dereferences the iterator and returns the address of the resulting |
921 | /// reference. |
922 | template <size_t Index> ValueT *getHelper() const { |
923 | auto &Begin = std::get<Index>(Begins); |
924 | auto &End = std::get<Index>(Ends); |
925 | if (Begin == End) |
926 | return nullptr; |
927 | |
928 | return &*Begin; |
929 | } |
930 | |
931 | /// Finds the first non-end iterator, dereferences, and returns the resulting |
932 | /// reference. |
933 | /// |
934 | /// It is an error to call this with all iterators at the end. |
935 | template <size_t... Ns> ValueT &get(std::index_sequence<Ns...>) const { |
936 | // Build a sequence of functions to get from iterator if possible. |
937 | ValueT *(concat_iterator::*GetHelperFns[])() const = { |
938 | &concat_iterator::getHelper<Ns>...}; |
939 | |
940 | // Loop over them, and return the first result we find. |
941 | for (auto &GetHelperFn : GetHelperFns) |
942 | if (ValueT *P = (this->*GetHelperFn)()) |
943 | return *P; |
944 | |
945 | llvm_unreachable("Attempted to get a pointer from an end concat iterator!")__builtin_unreachable(); |
946 | } |
947 | |
948 | public: |
949 | /// Constructs an iterator from a sequence of ranges. |
950 | /// |
951 | /// We need the full range to know how to switch between each of the |
952 | /// iterators. |
953 | template <typename... RangeTs> |
954 | explicit concat_iterator(RangeTs &&... Ranges) |
955 | : Begins(std::begin(Ranges)...), Ends(std::end(Ranges)...) {} |
956 | |
957 | using BaseT::operator++; |
958 | |
959 | concat_iterator &operator++() { |
960 | increment(std::index_sequence_for<IterTs...>()); |
961 | return *this; |
962 | } |
963 | |
964 | ValueT &operator*() const { |
965 | return get(std::index_sequence_for<IterTs...>()); |
966 | } |
967 | |
968 | bool operator==(const concat_iterator &RHS) const { |
969 | return Begins == RHS.Begins && Ends == RHS.Ends; |
970 | } |
971 | }; |
972 | |
973 | namespace detail { |
974 | |
975 | /// Helper to store a sequence of ranges being concatenated and access them. |
976 | /// |
977 | /// This is designed to facilitate providing actual storage when temporaries |
978 | /// are passed into the constructor such that we can use it as part of range |
979 | /// based for loops. |
980 | template <typename ValueT, typename... RangeTs> class concat_range { |
981 | public: |
982 | using iterator = |
983 | concat_iterator<ValueT, |
984 | decltype(std::begin(std::declval<RangeTs &>()))...>; |
985 | |
986 | private: |
987 | std::tuple<RangeTs...> Ranges; |
988 | |
989 | template <size_t... Ns> iterator begin_impl(std::index_sequence<Ns...>) { |
990 | return iterator(std::get<Ns>(Ranges)...); |
991 | } |
992 | template <size_t... Ns> iterator end_impl(std::index_sequence<Ns...>) { |
993 | return iterator(make_range(std::end(std::get<Ns>(Ranges)), |
994 | std::end(std::get<Ns>(Ranges)))...); |
995 | } |
996 | |
997 | public: |
998 | concat_range(RangeTs &&... Ranges) |
999 | : Ranges(std::forward<RangeTs>(Ranges)...) {} |
1000 | |
1001 | iterator begin() { return begin_impl(std::index_sequence_for<RangeTs...>{}); } |
1002 | iterator end() { return end_impl(std::index_sequence_for<RangeTs...>{}); } |
1003 | }; |
1004 | |
1005 | } // end namespace detail |
1006 | |
1007 | /// Concatenated range across two or more ranges. |
1008 | /// |
1009 | /// The desired value type must be explicitly specified. |
1010 | template <typename ValueT, typename... RangeTs> |
1011 | detail::concat_range<ValueT, RangeTs...> concat(RangeTs &&... Ranges) { |
1012 | static_assert(sizeof...(RangeTs) > 1, |
1013 | "Need more than one range to concatenate!"); |
1014 | return detail::concat_range<ValueT, RangeTs...>( |
1015 | std::forward<RangeTs>(Ranges)...); |
1016 | } |
1017 | |
1018 | /// A utility class used to implement an iterator that contains some base object |
1019 | /// and an index. The iterator moves the index but keeps the base constant. |
1020 | template <typename DerivedT, typename BaseT, typename T, |
1021 | typename PointerT = T *, typename ReferenceT = T &> |
1022 | class indexed_accessor_iterator |
1023 | : public llvm::iterator_facade_base<DerivedT, |
1024 | std::random_access_iterator_tag, T, |
1025 | std::ptrdiff_t, PointerT, ReferenceT> { |
1026 | public: |
1027 | ptrdiff_t operator-(const indexed_accessor_iterator &rhs) const { |
1028 | assert(base == rhs.base && "incompatible iterators")((void)0); |
1029 | return index - rhs.index; |
1030 | } |
1031 | bool operator==(const indexed_accessor_iterator &rhs) const { |
1032 | return base == rhs.base && index == rhs.index; |
1033 | } |
1034 | bool operator<(const indexed_accessor_iterator &rhs) const { |
1035 | assert(base == rhs.base && "incompatible iterators")((void)0); |
1036 | return index < rhs.index; |
1037 | } |
1038 | |
1039 | DerivedT &operator+=(ptrdiff_t offset) { |
1040 | this->index += offset; |
1041 | return static_cast<DerivedT &>(*this); |
1042 | } |
1043 | DerivedT &operator-=(ptrdiff_t offset) { |
1044 | this->index -= offset; |
1045 | return static_cast<DerivedT &>(*this); |
1046 | } |
1047 | |
1048 | /// Returns the current index of the iterator. |
1049 | ptrdiff_t getIndex() const { return index; } |
1050 | |
1051 | /// Returns the current base of the iterator. |
1052 | const BaseT &getBase() const { return base; } |
1053 | |
1054 | protected: |
1055 | indexed_accessor_iterator(BaseT base, ptrdiff_t index) |
1056 | : base(base), index(index) {} |
1057 | BaseT base; |
1058 | ptrdiff_t index; |
1059 | }; |
1060 | |
1061 | namespace detail { |
1062 | /// The class represents the base of a range of indexed_accessor_iterators. It |
1063 | /// provides support for many different range functionalities, e.g. |
1064 | /// drop_front/slice/etc.. Derived range classes must implement the following |
1065 | /// static methods: |
1066 | /// * ReferenceT dereference_iterator(const BaseT &base, ptrdiff_t index) |
1067 | /// - Dereference an iterator pointing to the base object at the given |
1068 | /// index. |
1069 | /// * BaseT offset_base(const BaseT &base, ptrdiff_t index) |
1070 | /// - Return a new base that is offset from the provide base by 'index' |
1071 | /// elements. |
1072 | template <typename DerivedT, typename BaseT, typename T, |
1073 | typename PointerT = T *, typename ReferenceT = T &> |
1074 | class indexed_accessor_range_base { |
1075 | public: |
1076 | using RangeBaseT = |
1077 | indexed_accessor_range_base<DerivedT, BaseT, T, PointerT, ReferenceT>; |
1078 | |
1079 | /// An iterator element of this range. |
1080 | class iterator : public indexed_accessor_iterator<iterator, BaseT, T, |
1081 | PointerT, ReferenceT> { |
1082 | public: |
1083 | // Index into this iterator, invoking a static method on the derived type. |
1084 | ReferenceT operator*() const { |
1085 | return DerivedT::dereference_iterator(this->getBase(), this->getIndex()); |
1086 | } |
1087 | |
1088 | private: |
1089 | iterator(BaseT owner, ptrdiff_t curIndex) |
1090 | : indexed_accessor_iterator<iterator, BaseT, T, PointerT, ReferenceT>( |
1091 | owner, curIndex) {} |
1092 | |
1093 | /// Allow access to the constructor. |
1094 | friend indexed_accessor_range_base<DerivedT, BaseT, T, PointerT, |
1095 | ReferenceT>; |
1096 | }; |
1097 | |
1098 | indexed_accessor_range_base(iterator begin, iterator end) |
1099 | : base(offset_base(begin.getBase(), begin.getIndex())), |
1100 | count(end.getIndex() - begin.getIndex()) {} |
1101 | indexed_accessor_range_base(const iterator_range<iterator> &range) |
1102 | : indexed_accessor_range_base(range.begin(), range.end()) {} |
1103 | indexed_accessor_range_base(BaseT base, ptrdiff_t count) |
1104 | : base(base), count(count) {} |
1105 | |
1106 | iterator begin() const { return iterator(base, 0); } |
1107 | iterator end() const { return iterator(base, count); } |
1108 | ReferenceT operator[](size_t Index) const { |
1109 | assert(Index < size() && "invalid index for value range")((void)0); |
1110 | return DerivedT::dereference_iterator(base, static_cast<ptrdiff_t>(Index)); |
1111 | } |
1112 | ReferenceT front() const { |
1113 | assert(!empty() && "expected non-empty range")((void)0); |
1114 | return (*this)[0]; |
1115 | } |
1116 | ReferenceT back() const { |
1117 | assert(!empty() && "expected non-empty range")((void)0); |
1118 | return (*this)[size() - 1]; |
1119 | } |
1120 | |
1121 | /// Compare this range with another. |
1122 | template <typename OtherT> bool operator==(const OtherT &other) const { |
1123 | return size() == |
1124 | static_cast<size_t>(std::distance(other.begin(), other.end())) && |
1125 | std::equal(begin(), end(), other.begin()); |
1126 | } |
1127 | template <typename OtherT> bool operator!=(const OtherT &other) const { |
1128 | return !(*this == other); |
1129 | } |
1130 | |
1131 | /// Return the size of this range. |
1132 | size_t size() const { return count; } |
1133 | |
1134 | /// Return if the range is empty. |
1135 | bool empty() const { return size() == 0; } |
1136 | |
1137 | /// Drop the first N elements, and keep M elements. |
1138 | DerivedT slice(size_t n, size_t m) const { |
1139 | assert(n + m <= size() && "invalid size specifiers")((void)0); |
1140 | return DerivedT(offset_base(base, n), m); |
1141 | } |
1142 | |
1143 | /// Drop the first n elements. |
1144 | DerivedT drop_front(size_t n = 1) const { |
1145 | assert(size() >= n && "Dropping more elements than exist")((void)0); |
1146 | return slice(n, size() - n); |
1147 | } |
1148 | /// Drop the last n elements. |
1149 | DerivedT drop_back(size_t n = 1) const { |
1150 | assert(size() >= n && "Dropping more elements than exist")((void)0); |
1151 | return DerivedT(base, size() - n); |
1152 | } |
1153 | |
1154 | /// Take the first n elements. |
1155 | DerivedT take_front(size_t n = 1) const { |
1156 | return n < size() ? drop_back(size() - n) |
1157 | : static_cast<const DerivedT &>(*this); |
1158 | } |
1159 | |
1160 | /// Take the last n elements. |
1161 | DerivedT take_back(size_t n = 1) const { |
1162 | return n < size() ? drop_front(size() - n) |
1163 | : static_cast<const DerivedT &>(*this); |
1164 | } |
1165 | |
1166 | /// Allow conversion to any type accepting an iterator_range. |
1167 | template <typename RangeT, typename = std::enable_if_t<std::is_constructible< |
1168 | RangeT, iterator_range<iterator>>::value>> |
1169 | operator RangeT() const { |
1170 | return RangeT(iterator_range<iterator>(*this)); |
1171 | } |
1172 | |
1173 | /// Returns the base of this range. |
1174 | const BaseT &getBase() const { return base; } |
1175 | |
1176 | private: |
1177 | /// Offset the given base by the given amount. |
1178 | static BaseT offset_base(const BaseT &base, size_t n) { |
1179 | return n == 0 ? base : DerivedT::offset_base(base, n); |
1180 | } |
1181 | |
1182 | protected: |
1183 | indexed_accessor_range_base(const indexed_accessor_range_base &) = default; |
1184 | indexed_accessor_range_base(indexed_accessor_range_base &&) = default; |
1185 | indexed_accessor_range_base & |
1186 | operator=(const indexed_accessor_range_base &) = default; |
1187 | |
1188 | /// The base that owns the provided range of values. |
1189 | BaseT base; |
1190 | /// The size from the owning range. |
1191 | ptrdiff_t count; |
1192 | }; |
1193 | } // end namespace detail |
1194 | |
1195 | /// This class provides an implementation of a range of |
1196 | /// indexed_accessor_iterators where the base is not indexable. Ranges with |
1197 | /// bases that are offsetable should derive from indexed_accessor_range_base |
1198 | /// instead. Derived range classes are expected to implement the following |
1199 | /// static method: |
1200 | /// * ReferenceT dereference(const BaseT &base, ptrdiff_t index) |
1201 | /// - Dereference an iterator pointing to a parent base at the given index. |
1202 | template <typename DerivedT, typename BaseT, typename T, |
1203 | typename PointerT = T *, typename ReferenceT = T &> |
1204 | class indexed_accessor_range |
1205 | : public detail::indexed_accessor_range_base< |
1206 | DerivedT, std::pair<BaseT, ptrdiff_t>, T, PointerT, ReferenceT> { |
1207 | public: |
1208 | indexed_accessor_range(BaseT base, ptrdiff_t startIndex, ptrdiff_t count) |
1209 | : detail::indexed_accessor_range_base< |
1210 | DerivedT, std::pair<BaseT, ptrdiff_t>, T, PointerT, ReferenceT>( |
1211 | std::make_pair(base, startIndex), count) {} |
1212 | using detail::indexed_accessor_range_base< |
1213 | DerivedT, std::pair<BaseT, ptrdiff_t>, T, PointerT, |
1214 | ReferenceT>::indexed_accessor_range_base; |
1215 | |
1216 | /// Returns the current base of the range. |
1217 | const BaseT &getBase() const { return this->base.first; } |
1218 | |
1219 | /// Returns the current start index of the range. |
1220 | ptrdiff_t getStartIndex() const { return this->base.second; } |
1221 | |
1222 | /// See `detail::indexed_accessor_range_base` for details. |
1223 | static std::pair<BaseT, ptrdiff_t> |
1224 | offset_base(const std::pair<BaseT, ptrdiff_t> &base, ptrdiff_t index) { |
1225 | // We encode the internal base as a pair of the derived base and a start |
1226 | // index into the derived base. |
1227 | return std::make_pair(base.first, base.second + index); |
1228 | } |
1229 | /// See `detail::indexed_accessor_range_base` for details. |
1230 | static ReferenceT |
1231 | dereference_iterator(const std::pair<BaseT, ptrdiff_t> &base, |
1232 | ptrdiff_t index) { |
1233 | return DerivedT::dereference(base.first, base.second + index); |
1234 | } |
1235 | }; |
1236 | |
1237 | /// Given a container of pairs, return a range over the first elements. |
1238 | template <typename ContainerTy> auto make_first_range(ContainerTy &&c) { |
1239 | return llvm::map_range( |
1240 | std::forward<ContainerTy>(c), |
1241 | [](decltype((*std::begin(c))) elt) -> decltype((elt.first)) { |
1242 | return elt.first; |
1243 | }); |
1244 | } |
1245 | |
1246 | /// Given a container of pairs, return a range over the second elements. |
1247 | template <typename ContainerTy> auto make_second_range(ContainerTy &&c) { |
1248 | return llvm::map_range( |
1249 | std::forward<ContainerTy>(c), |
1250 | [](decltype((*std::begin(c))) elt) -> decltype((elt.second)) { |
1251 | return elt.second; |
1252 | }); |
1253 | } |
1254 | |
1255 | //===----------------------------------------------------------------------===// |
1256 | // Extra additions to <utility> |
1257 | //===----------------------------------------------------------------------===// |
1258 | |
1259 | /// Function object to check whether the first component of a std::pair |
1260 | /// compares less than the first component of another std::pair. |
1261 | struct less_first { |
1262 | template <typename T> bool operator()(const T &lhs, const T &rhs) const { |
1263 | return lhs.first < rhs.first; |
1264 | } |
1265 | }; |
1266 | |
1267 | /// Function object to check whether the second component of a std::pair |
1268 | /// compares less than the second component of another std::pair. |
1269 | struct less_second { |
1270 | template <typename T> bool operator()(const T &lhs, const T &rhs) const { |
1271 | return lhs.second < rhs.second; |
1272 | } |
1273 | }; |
1274 | |
1275 | /// \brief Function object to apply a binary function to the first component of |
1276 | /// a std::pair. |
1277 | template<typename FuncTy> |
1278 | struct on_first { |
1279 | FuncTy func; |
1280 | |
1281 | template <typename T> |
1282 | decltype(auto) operator()(const T &lhs, const T &rhs) const { |
1283 | return func(lhs.first, rhs.first); |
1284 | } |
1285 | }; |
1286 | |
1287 | /// Utility type to build an inheritance chain that makes it easy to rank |
1288 | /// overload candidates. |
1289 | template <int N> struct rank : rank<N - 1> {}; |
1290 | template <> struct rank<0> {}; |
1291 | |
1292 | /// traits class for checking whether type T is one of any of the given |
1293 | /// types in the variadic list. |
1294 | template <typename T, typename... Ts> |
1295 | using is_one_of = disjunction<std::is_same<T, Ts>...>; |
1296 | |
1297 | /// traits class for checking whether type T is a base class for all |
1298 | /// the given types in the variadic list. |
1299 | template <typename T, typename... Ts> |
1300 | using are_base_of = conjunction<std::is_base_of<T, Ts>...>; |
1301 | |
1302 | namespace detail { |
1303 | template <typename... Ts> struct Visitor; |
1304 | |
1305 | template <typename HeadT, typename... TailTs> |
1306 | struct Visitor<HeadT, TailTs...> : remove_cvref_t<HeadT>, Visitor<TailTs...> { |
1307 | explicit constexpr Visitor(HeadT &&Head, TailTs &&...Tail) |
1308 | : remove_cvref_t<HeadT>(std::forward<HeadT>(Head)), |
1309 | Visitor<TailTs...>(std::forward<TailTs>(Tail)...) {} |
1310 | using remove_cvref_t<HeadT>::operator(); |
1311 | using Visitor<TailTs...>::operator(); |
1312 | }; |
1313 | |
1314 | template <typename HeadT> struct Visitor<HeadT> : remove_cvref_t<HeadT> { |
1315 | explicit constexpr Visitor(HeadT &&Head) |
1316 | : remove_cvref_t<HeadT>(std::forward<HeadT>(Head)) {} |
1317 | using remove_cvref_t<HeadT>::operator(); |
1318 | }; |
1319 | } // namespace detail |
1320 | |
1321 | /// Returns an opaquely-typed Callable object whose operator() overload set is |
1322 | /// the sum of the operator() overload sets of each CallableT in CallableTs. |
1323 | /// |
1324 | /// The type of the returned object derives from each CallableT in CallableTs. |
1325 | /// The returned object is constructed by invoking the appropriate copy or move |
1326 | /// constructor of each CallableT, as selected by overload resolution on the |
1327 | /// corresponding argument to makeVisitor. |
1328 | /// |
1329 | /// Example: |
1330 | /// |
1331 | /// \code |
1332 | /// auto visitor = makeVisitor([](auto) { return "unhandled type"; }, |
1333 | /// [](int i) { return "int"; }, |
1334 | /// [](std::string s) { return "str"; }); |
1335 | /// auto a = visitor(42); // `a` is now "int". |
1336 | /// auto b = visitor("foo"); // `b` is now "str". |
1337 | /// auto c = visitor(3.14f); // `c` is now "unhandled type". |
1338 | /// \endcode |
1339 | /// |
1340 | /// Example of making a visitor with a lambda which captures a move-only type: |
1341 | /// |
1342 | /// \code |
1343 | /// std::unique_ptr<FooHandler> FH = /* ... */; |
1344 | /// auto visitor = makeVisitor( |
1345 | /// [FH{std::move(FH)}](Foo F) { return FH->handle(F); }, |
1346 | /// [](int i) { return i; }, |
1347 | /// [](std::string s) { return atoi(s); }); |
1348 | /// \endcode |
1349 | template <typename... CallableTs> |
1350 | constexpr decltype(auto) makeVisitor(CallableTs &&...Callables) { |
1351 | return detail::Visitor<CallableTs...>(std::forward<CallableTs>(Callables)...); |
1352 | } |
1353 | |
1354 | //===----------------------------------------------------------------------===// |
1355 | // Extra additions for arrays |
1356 | //===----------------------------------------------------------------------===// |
1357 | |
1358 | // We have a copy here so that LLVM behaves the same when using different |
1359 | // standard libraries. |
1360 | template <class Iterator, class RNG> |
1361 | void shuffle(Iterator first, Iterator last, RNG &&g) { |
1362 | // It would be better to use a std::uniform_int_distribution, |
1363 | // but that would be stdlib dependent. |
1364 | typedef |
1365 | typename std::iterator_traits<Iterator>::difference_type difference_type; |
1366 | for (auto size = last - first; size > 1; ++first, (void)--size) { |
1367 | difference_type offset = g() % size; |
1368 | // Avoid self-assignment due to incorrect assertions in libstdc++ |
1369 | // containers (https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85828). |
1370 | if (offset != difference_type(0)) |
1371 | std::iter_swap(first, first + offset); |
1372 | } |
1373 | } |
1374 | |
1375 | /// Find the length of an array. |
1376 | template <class T, std::size_t N> |
1377 | constexpr inline size_t array_lengthof(T (&)[N]) { |
1378 | return N; |
1379 | } |
1380 | |
1381 | /// Adapt std::less<T> for array_pod_sort. |
1382 | template<typename T> |
1383 | inline int array_pod_sort_comparator(const void *P1, const void *P2) { |
1384 | if (std::less<T>()(*reinterpret_cast<const T*>(P1), |
1385 | *reinterpret_cast<const T*>(P2))) |
1386 | return -1; |
1387 | if (std::less<T>()(*reinterpret_cast<const T*>(P2), |
1388 | *reinterpret_cast<const T*>(P1))) |
1389 | return 1; |
1390 | return 0; |
1391 | } |
1392 | |
1393 | /// get_array_pod_sort_comparator - This is an internal helper function used to |
1394 | /// get type deduction of T right. |
1395 | template<typename T> |
1396 | inline int (*get_array_pod_sort_comparator(const T &)) |
1397 | (const void*, const void*) { |
1398 | return array_pod_sort_comparator<T>; |
1399 | } |
1400 | |
1401 | #ifdef EXPENSIVE_CHECKS |
1402 | namespace detail { |
1403 | |
1404 | inline unsigned presortShuffleEntropy() { |
1405 | static unsigned Result(std::random_device{}()); |
1406 | return Result; |
1407 | } |
1408 | |
1409 | template <class IteratorTy> |
1410 | inline void presortShuffle(IteratorTy Start, IteratorTy End) { |
1411 | std::mt19937 Generator(presortShuffleEntropy()); |
1412 | llvm::shuffle(Start, End, Generator); |
1413 | } |
1414 | |
1415 | } // end namespace detail |
1416 | #endif |
1417 | |
1418 | /// array_pod_sort - This sorts an array with the specified start and end |
1419 | /// extent. This is just like std::sort, except that it calls qsort instead of |
1420 | /// using an inlined template. qsort is slightly slower than std::sort, but |
1421 | /// most sorts are not performance critical in LLVM and std::sort has to be |
1422 | /// template instantiated for each type, leading to significant measured code |
1423 | /// bloat. This function should generally be used instead of std::sort where |
1424 | /// possible. |
1425 | /// |
1426 | /// This function assumes that you have simple POD-like types that can be |
1427 | /// compared with std::less and can be moved with memcpy. If this isn't true, |
1428 | /// you should use std::sort. |
1429 | /// |
1430 | /// NOTE: If qsort_r were portable, we could allow a custom comparator and |
1431 | /// default to std::less. |
1432 | template<class IteratorTy> |
1433 | inline void array_pod_sort(IteratorTy Start, IteratorTy End) { |
1434 | // Don't inefficiently call qsort with one element or trigger undefined |
1435 | // behavior with an empty sequence. |
1436 | auto NElts = End - Start; |
1437 | if (NElts <= 1) return; |
1438 | #ifdef EXPENSIVE_CHECKS |
1439 | detail::presortShuffle<IteratorTy>(Start, End); |
1440 | #endif |
1441 | qsort(&*Start, NElts, sizeof(*Start), get_array_pod_sort_comparator(*Start)); |
1442 | } |
1443 | |
1444 | template <class IteratorTy> |
1445 | inline void array_pod_sort( |
1446 | IteratorTy Start, IteratorTy End, |
1447 | int (*Compare)( |
1448 | const typename std::iterator_traits<IteratorTy>::value_type *, |
1449 | const typename std::iterator_traits<IteratorTy>::value_type *)) { |
1450 | // Don't inefficiently call qsort with one element or trigger undefined |
1451 | // behavior with an empty sequence. |
1452 | auto NElts = End - Start; |
1453 | if (NElts <= 1) return; |
1454 | #ifdef EXPENSIVE_CHECKS |
1455 | detail::presortShuffle<IteratorTy>(Start, End); |
1456 | #endif |
1457 | qsort(&*Start, NElts, sizeof(*Start), |
1458 | reinterpret_cast<int (*)(const void *, const void *)>(Compare)); |
1459 | } |
1460 | |
1461 | namespace detail { |
1462 | template <typename T> |
1463 | // We can use qsort if the iterator type is a pointer and the underlying value |
1464 | // is trivially copyable. |
1465 | using sort_trivially_copyable = conjunction< |
1466 | std::is_pointer<T>, |
1467 | std::is_trivially_copyable<typename std::iterator_traits<T>::value_type>>; |
1468 | } // namespace detail |
1469 | |
1470 | // Provide wrappers to std::sort which shuffle the elements before sorting |
1471 | // to help uncover non-deterministic behavior (PR35135). |
1472 | template <typename IteratorTy, |
1473 | std::enable_if_t<!detail::sort_trivially_copyable<IteratorTy>::value, |
1474 | int> = 0> |
1475 | inline void sort(IteratorTy Start, IteratorTy End) { |
1476 | #ifdef EXPENSIVE_CHECKS |
1477 | detail::presortShuffle<IteratorTy>(Start, End); |
1478 | #endif |
1479 | std::sort(Start, End); |
1480 | } |
1481 | |
1482 | // Forward trivially copyable types to array_pod_sort. This avoids a large |
1483 | // amount of code bloat for a minor performance hit. |
1484 | template <typename IteratorTy, |
1485 | std::enable_if_t<detail::sort_trivially_copyable<IteratorTy>::value, |
1486 | int> = 0> |
1487 | inline void sort(IteratorTy Start, IteratorTy End) { |
1488 | array_pod_sort(Start, End); |
1489 | } |
1490 | |
1491 | template <typename Container> inline void sort(Container &&C) { |
1492 | llvm::sort(adl_begin(C), adl_end(C)); |
1493 | } |
1494 | |
1495 | template <typename IteratorTy, typename Compare> |
1496 | inline void sort(IteratorTy Start, IteratorTy End, Compare Comp) { |
1497 | #ifdef EXPENSIVE_CHECKS |
1498 | detail::presortShuffle<IteratorTy>(Start, End); |
1499 | #endif |
1500 | std::sort(Start, End, Comp); |
1501 | } |
1502 | |
1503 | template <typename Container, typename Compare> |
1504 | inline void sort(Container &&C, Compare Comp) { |
1505 | llvm::sort(adl_begin(C), adl_end(C), Comp); |
1506 | } |
1507 | |
1508 | //===----------------------------------------------------------------------===// |
1509 | // Extra additions to <algorithm> |
1510 | //===----------------------------------------------------------------------===// |
1511 | |
1512 | /// Get the size of a range. This is a wrapper function around std::distance |
1513 | /// which is only enabled when the operation is O(1). |
1514 | template <typename R> |
1515 | auto size(R &&Range, |
1516 | std::enable_if_t< |
1517 | std::is_base_of<std::random_access_iterator_tag, |
1518 | typename std::iterator_traits<decltype( |
1519 | Range.begin())>::iterator_category>::value, |
1520 | void> * = nullptr) { |
1521 | return std::distance(Range.begin(), Range.end()); |
1522 | } |
1523 | |
1524 | /// Provide wrappers to std::for_each which take ranges instead of having to |
1525 | /// pass begin/end explicitly. |
1526 | template <typename R, typename UnaryFunction> |
1527 | UnaryFunction for_each(R &&Range, UnaryFunction F) { |
1528 | return std::for_each(adl_begin(Range), adl_end(Range), F); |
1529 | } |
1530 | |
1531 | /// Provide wrappers to std::all_of which take ranges instead of having to pass |
1532 | /// begin/end explicitly. |
1533 | template <typename R, typename UnaryPredicate> |
1534 | bool all_of(R &&Range, UnaryPredicate P) { |
1535 | return std::all_of(adl_begin(Range), adl_end(Range), P); |
1536 | } |
1537 | |
1538 | /// Provide wrappers to std::any_of which take ranges instead of having to pass |
1539 | /// begin/end explicitly. |
1540 | template <typename R, typename UnaryPredicate> |
1541 | bool any_of(R &&Range, UnaryPredicate P) { |
1542 | return std::any_of(adl_begin(Range), adl_end(Range), P); |
1543 | } |
1544 | |
1545 | /// Provide wrappers to std::none_of which take ranges instead of having to pass |
1546 | /// begin/end explicitly. |
1547 | template <typename R, typename UnaryPredicate> |
1548 | bool none_of(R &&Range, UnaryPredicate P) { |
1549 | return std::none_of(adl_begin(Range), adl_end(Range), P); |
1550 | } |
1551 | |
1552 | /// Provide wrappers to std::find which take ranges instead of having to pass |
1553 | /// begin/end explicitly. |
1554 | template <typename R, typename T> auto find(R &&Range, const T &Val) { |
1555 | return std::find(adl_begin(Range), adl_end(Range), Val); |
1556 | } |
1557 | |
1558 | /// Provide wrappers to std::find_if which take ranges instead of having to pass |
1559 | /// begin/end explicitly. |
1560 | template <typename R, typename UnaryPredicate> |
1561 | auto find_if(R &&Range, UnaryPredicate P) { |
1562 | return std::find_if(adl_begin(Range), adl_end(Range), P); |
1563 | } |
1564 | |
1565 | template <typename R, typename UnaryPredicate> |
1566 | auto find_if_not(R &&Range, UnaryPredicate P) { |
1567 | return std::find_if_not(adl_begin(Range), adl_end(Range), P); |
1568 | } |
1569 | |
1570 | /// Provide wrappers to std::remove_if which take ranges instead of having to |
1571 | /// pass begin/end explicitly. |
1572 | template <typename R, typename UnaryPredicate> |
1573 | auto remove_if(R &&Range, UnaryPredicate P) { |
1574 | return std::remove_if(adl_begin(Range), adl_end(Range), P); |
1575 | } |
1576 | |
1577 | /// Provide wrappers to std::copy_if which take ranges instead of having to |
1578 | /// pass begin/end explicitly. |
1579 | template <typename R, typename OutputIt, typename UnaryPredicate> |
1580 | OutputIt copy_if(R &&Range, OutputIt Out, UnaryPredicate P) { |
1581 | return std::copy_if(adl_begin(Range), adl_end(Range), Out, P); |
1582 | } |
1583 | |
1584 | template <typename R, typename OutputIt> |
1585 | OutputIt copy(R &&Range, OutputIt Out) { |
1586 | return std::copy(adl_begin(Range), adl_end(Range), Out); |
1587 | } |
1588 | |
1589 | /// Provide wrappers to std::move which take ranges instead of having to |
1590 | /// pass begin/end explicitly. |
1591 | template <typename R, typename OutputIt> |
1592 | OutputIt move(R &&Range, OutputIt Out) { |
1593 | return std::move(adl_begin(Range), adl_end(Range), Out); |
1594 | } |
1595 | |
1596 | /// Wrapper function around std::find to detect if an element exists |
1597 | /// in a container. |
1598 | template <typename R, typename E> |
1599 | bool is_contained(R &&Range, const E &Element) { |
1600 | return std::find(adl_begin(Range), adl_end(Range), Element) != adl_end(Range); |
1601 | } |
1602 | |
1603 | /// Wrapper function around std::is_sorted to check if elements in a range \p R |
1604 | /// are sorted with respect to a comparator \p C. |
1605 | template <typename R, typename Compare> bool is_sorted(R &&Range, Compare C) { |
1606 | return std::is_sorted(adl_begin(Range), adl_end(Range), C); |
1607 | } |
1608 | |
1609 | /// Wrapper function around std::is_sorted to check if elements in a range \p R |
1610 | /// are sorted in non-descending order. |
1611 | template <typename R> bool is_sorted(R &&Range) { |
1612 | return std::is_sorted(adl_begin(Range), adl_end(Range)); |
1613 | } |
1614 | |
1615 | /// Wrapper function around std::count to count the number of times an element |
1616 | /// \p Element occurs in the given range \p Range. |
1617 | template <typename R, typename E> auto count(R &&Range, const E &Element) { |
1618 | return std::count(adl_begin(Range), adl_end(Range), Element); |
1619 | } |
1620 | |
1621 | /// Wrapper function around std::count_if to count the number of times an |
1622 | /// element satisfying a given predicate occurs in a range. |
1623 | template <typename R, typename UnaryPredicate> |
1624 | auto count_if(R &&Range, UnaryPredicate P) { |
1625 | return std::count_if(adl_begin(Range), adl_end(Range), P); |
1626 | } |
1627 | |
1628 | /// Wrapper function around std::transform to apply a function to a range and |
1629 | /// store the result elsewhere. |
1630 | template <typename R, typename OutputIt, typename UnaryFunction> |
1631 | OutputIt transform(R &&Range, OutputIt d_first, UnaryFunction F) { |
1632 | return std::transform(adl_begin(Range), adl_end(Range), d_first, F); |
1633 | } |
1634 | |
1635 | /// Provide wrappers to std::partition which take ranges instead of having to |
1636 | /// pass begin/end explicitly. |
1637 | template <typename R, typename UnaryPredicate> |
1638 | auto partition(R &&Range, UnaryPredicate P) { |
1639 | return std::partition(adl_begin(Range), adl_end(Range), P); |
1640 | } |
1641 | |
1642 | /// Provide wrappers to std::lower_bound which take ranges instead of having to |
1643 | /// pass begin/end explicitly. |
1644 | template <typename R, typename T> auto lower_bound(R &&Range, T &&Value) { |
1645 | return std::lower_bound(adl_begin(Range), adl_end(Range), |
1646 | std::forward<T>(Value)); |
1647 | } |
1648 | |
1649 | template <typename R, typename T, typename Compare> |
1650 | auto lower_bound(R &&Range, T &&Value, Compare C) { |
1651 | return std::lower_bound(adl_begin(Range), adl_end(Range), |
1652 | std::forward<T>(Value), C); |
1653 | } |
1654 | |
1655 | /// Provide wrappers to std::upper_bound which take ranges instead of having to |
1656 | /// pass begin/end explicitly. |
1657 | template <typename R, typename T> auto upper_bound(R &&Range, T &&Value) { |
1658 | return std::upper_bound(adl_begin(Range), adl_end(Range), |
1659 | std::forward<T>(Value)); |
1660 | } |
1661 | |
1662 | template <typename R, typename T, typename Compare> |
1663 | auto upper_bound(R &&Range, T &&Value, Compare C) { |
1664 | return std::upper_bound(adl_begin(Range), adl_end(Range), |
1665 | std::forward<T>(Value), C); |
1666 | } |
1667 | |
1668 | template <typename R> |
1669 | void stable_sort(R &&Range) { |
1670 | std::stable_sort(adl_begin(Range), adl_end(Range)); |
1671 | } |
1672 | |
1673 | template <typename R, typename Compare> |
1674 | void stable_sort(R &&Range, Compare C) { |
1675 | std::stable_sort(adl_begin(Range), adl_end(Range), C); |
1676 | } |
1677 | |
1678 | /// Binary search for the first iterator in a range where a predicate is false. |
1679 | /// Requires that C is always true below some limit, and always false above it. |
1680 | template <typename R, typename Predicate, |
1681 | typename Val = decltype(*adl_begin(std::declval<R>()))> |
1682 | auto partition_point(R &&Range, Predicate P) { |
1683 | return std::partition_point(adl_begin(Range), adl_end(Range), P); |
1684 | } |
1685 | |
1686 | template<typename Range, typename Predicate> |
1687 | auto unique(Range &&R, Predicate P) { |
1688 | return std::unique(adl_begin(R), adl_end(R), P); |
1689 | } |
1690 | |
1691 | /// Wrapper function around std::equal to detect if pair-wise elements between |
1692 | /// two ranges are the same. |
1693 | template <typename L, typename R> bool equal(L &&LRange, R &&RRange) { |
1694 | return std::equal(adl_begin(LRange), adl_end(LRange), adl_begin(RRange), |
1695 | adl_end(RRange)); |
1696 | } |
1697 | |
1698 | /// Wrapper function around std::equal to detect if all elements |
1699 | /// in a container are same. |
1700 | template <typename R> |
1701 | bool is_splat(R &&Range) { |
1702 | size_t range_size = size(Range); |
1703 | return range_size != 0 && (range_size == 1 || |
1704 | std::equal(adl_begin(Range) + 1, adl_end(Range), adl_begin(Range))); |
1705 | } |
1706 | |
1707 | /// Provide a container algorithm similar to C++ Library Fundamentals v2's |
1708 | /// `erase_if` which is equivalent to: |
1709 | /// |
1710 | /// C.erase(remove_if(C, pred), C.end()); |
1711 | /// |
1712 | /// This version works for any container with an erase method call accepting |
1713 | /// two iterators. |
1714 | template <typename Container, typename UnaryPredicate> |
1715 | void erase_if(Container &C, UnaryPredicate P) { |
1716 | C.erase(remove_if(C, P), C.end()); |
1717 | } |
1718 | |
1719 | /// Wrapper function to remove a value from a container: |
1720 | /// |
1721 | /// C.erase(remove(C.begin(), C.end(), V), C.end()); |
1722 | template <typename Container, typename ValueType> |
1723 | void erase_value(Container &C, ValueType V) { |
1724 | C.erase(std::remove(C.begin(), C.end(), V), C.end()); |
1725 | } |
1726 | |
1727 | /// Wrapper function to append a range to a container. |
1728 | /// |
1729 | /// C.insert(C.end(), R.begin(), R.end()); |
1730 | template <typename Container, typename Range> |
1731 | inline void append_range(Container &C, Range &&R) { |
1732 | C.insert(C.end(), R.begin(), R.end()); |
1733 | } |
1734 | |
1735 | /// Given a sequence container Cont, replace the range [ContIt, ContEnd) with |
1736 | /// the range [ValIt, ValEnd) (which is not from the same container). |
1737 | template<typename Container, typename RandomAccessIterator> |
1738 | void replace(Container &Cont, typename Container::iterator ContIt, |
1739 | typename Container::iterator ContEnd, RandomAccessIterator ValIt, |
1740 | RandomAccessIterator ValEnd) { |
1741 | while (true) { |
1742 | if (ValIt == ValEnd) { |
1743 | Cont.erase(ContIt, ContEnd); |
1744 | return; |
1745 | } else if (ContIt == ContEnd) { |
1746 | Cont.insert(ContIt, ValIt, ValEnd); |
1747 | return; |
1748 | } |
1749 | *ContIt++ = *ValIt++; |
1750 | } |
1751 | } |
1752 | |
1753 | /// Given a sequence container Cont, replace the range [ContIt, ContEnd) with |
1754 | /// the range R. |
1755 | template<typename Container, typename Range = std::initializer_list< |
1756 | typename Container::value_type>> |
1757 | void replace(Container &Cont, typename Container::iterator ContIt, |
1758 | typename Container::iterator ContEnd, Range R) { |
1759 | replace(Cont, ContIt, ContEnd, R.begin(), R.end()); |
1760 | } |
1761 | |
1762 | /// An STL-style algorithm similar to std::for_each that applies a second |
1763 | /// functor between every pair of elements. |
1764 | /// |
1765 | /// This provides the control flow logic to, for example, print a |
1766 | /// comma-separated list: |
1767 | /// \code |
1768 | /// interleave(names.begin(), names.end(), |
1769 | /// [&](StringRef name) { os << name; }, |
1770 | /// [&] { os << ", "; }); |
1771 | /// \endcode |
1772 | template <typename ForwardIterator, typename UnaryFunctor, |
1773 | typename NullaryFunctor, |
1774 | typename = typename std::enable_if< |
1775 | !std::is_constructible<StringRef, UnaryFunctor>::value && |
1776 | !std::is_constructible<StringRef, NullaryFunctor>::value>::type> |
1777 | inline void interleave(ForwardIterator begin, ForwardIterator end, |
1778 | UnaryFunctor each_fn, NullaryFunctor between_fn) { |
1779 | if (begin == end) |
1780 | return; |
1781 | each_fn(*begin); |
1782 | ++begin; |
1783 | for (; begin != end; ++begin) { |
1784 | between_fn(); |
1785 | each_fn(*begin); |
1786 | } |
1787 | } |
1788 | |
1789 | template <typename Container, typename UnaryFunctor, typename NullaryFunctor, |
1790 | typename = typename std::enable_if< |
1791 | !std::is_constructible<StringRef, UnaryFunctor>::value && |
1792 | !std::is_constructible<StringRef, NullaryFunctor>::value>::type> |
1793 | inline void interleave(const Container &c, UnaryFunctor each_fn, |
1794 | NullaryFunctor between_fn) { |
1795 | interleave(c.begin(), c.end(), each_fn, between_fn); |
1796 | } |
1797 | |
1798 | /// Overload of interleave for the common case of string separator. |
1799 | template <typename Container, typename UnaryFunctor, typename StreamT, |
1800 | typename T = detail::ValueOfRange<Container>> |
1801 | inline void interleave(const Container &c, StreamT &os, UnaryFunctor each_fn, |
1802 | const StringRef &separator) { |
1803 | interleave(c.begin(), c.end(), each_fn, [&] { os << separator; }); |
1804 | } |
1805 | template <typename Container, typename StreamT, |
1806 | typename T = detail::ValueOfRange<Container>> |
1807 | inline void interleave(const Container &c, StreamT &os, |
1808 | const StringRef &separator) { |
1809 | interleave( |
1810 | c, os, [&](const T &a) { os << a; }, separator); |
1811 | } |
1812 | |
1813 | template <typename Container, typename UnaryFunctor, typename StreamT, |
1814 | typename T = detail::ValueOfRange<Container>> |
1815 | inline void interleaveComma(const Container &c, StreamT &os, |
1816 | UnaryFunctor each_fn) { |
1817 | interleave(c, os, each_fn, ", "); |
1818 | } |
1819 | template <typename Container, typename StreamT, |
1820 | typename T = detail::ValueOfRange<Container>> |
1821 | inline void interleaveComma(const Container &c, StreamT &os) { |
1822 | interleaveComma(c, os, [&](const T &a) { os << a; }); |
1823 | } |
1824 | |
1825 | //===----------------------------------------------------------------------===// |
1826 | // Extra additions to <memory> |
1827 | //===----------------------------------------------------------------------===// |
1828 | |
1829 | struct FreeDeleter { |
1830 | void operator()(void* v) { |
1831 | ::free(v); |
1832 | } |
1833 | }; |
1834 | |
1835 | template<typename First, typename Second> |
1836 | struct pair_hash { |
1837 | size_t operator()(const std::pair<First, Second> &P) const { |
1838 | return std::hash<First>()(P.first) * 31 + std::hash<Second>()(P.second); |
1839 | } |
1840 | }; |
1841 | |
1842 | /// Binary functor that adapts to any other binary functor after dereferencing |
1843 | /// operands. |
1844 | template <typename T> struct deref { |
1845 | T func; |
1846 | |
1847 | // Could be further improved to cope with non-derivable functors and |
1848 | // non-binary functors (should be a variadic template member function |
1849 | // operator()). |
1850 | template <typename A, typename B> auto operator()(A &lhs, B &rhs) const { |
1851 | assert(lhs)((void)0); |
1852 | assert(rhs)((void)0); |
1853 | return func(*lhs, *rhs); |
1854 | } |
1855 | }; |
1856 | |
1857 | namespace detail { |
1858 | |
1859 | template <typename R> class enumerator_iter; |
1860 | |
1861 | template <typename R> struct result_pair { |
1862 | using value_reference = |
1863 | typename std::iterator_traits<IterOfRange<R>>::reference; |
1864 | |
1865 | friend class enumerator_iter<R>; |
1866 | |
1867 | result_pair() = default; |
1868 | result_pair(std::size_t Index, IterOfRange<R> Iter) |
1869 | : Index(Index), Iter(Iter) {} |
1870 | |
1871 | result_pair(const result_pair<R> &Other) |
1872 | : Index(Other.Index), Iter(Other.Iter) {} |
1873 | result_pair &operator=(const result_pair &Other) { |
1874 | Index = Other.Index; |
1875 | Iter = Other.Iter; |
1876 | return *this; |
1877 | } |
1878 | |
1879 | std::size_t index() const { return Index; } |
1880 | const value_reference value() const { return *Iter; } |
1881 | value_reference value() { return *Iter; } |
1882 | |
1883 | private: |
1884 | std::size_t Index = std::numeric_limits<std::size_t>::max(); |
1885 | IterOfRange<R> Iter; |
1886 | }; |
1887 | |
1888 | template <typename R> |
1889 | class enumerator_iter |
1890 | : public iterator_facade_base< |
1891 | enumerator_iter<R>, std::forward_iterator_tag, result_pair<R>, |
1892 | typename std::iterator_traits<IterOfRange<R>>::difference_type, |
1893 | typename std::iterator_traits<IterOfRange<R>>::pointer, |
1894 | typename std::iterator_traits<IterOfRange<R>>::reference> { |
1895 | using result_type = result_pair<R>; |
1896 | |
1897 | public: |
1898 | explicit enumerator_iter(IterOfRange<R> EndIter) |
1899 | : Result(std::numeric_limits<size_t>::max(), EndIter) {} |
1900 | |
1901 | enumerator_iter(std::size_t Index, IterOfRange<R> Iter) |
1902 | : Result(Index, Iter) {} |
1903 | |
1904 | result_type &operator*() { return Result; } |
1905 | const result_type &operator*() const { return Result; } |
1906 | |
1907 | enumerator_iter &operator++() { |
1908 | assert(Result.Index != std::numeric_limits<size_t>::max())((void)0); |
1909 | ++Result.Iter; |
1910 | ++Result.Index; |
1911 | return *this; |
1912 | } |
1913 | |
1914 | bool operator==(const enumerator_iter &RHS) const { |
1915 | // Don't compare indices here, only iterators. It's possible for an end |
1916 | // iterator to have different indices depending on whether it was created |
1917 | // by calling std::end() versus incrementing a valid iterator. |
1918 | return Result.Iter == RHS.Result.Iter; |
1919 | } |
1920 | |
1921 | enumerator_iter(const enumerator_iter &Other) : Result(Other.Result) {} |
1922 | enumerator_iter &operator=(const enumerator_iter &Other) { |
1923 | Result = Other.Result; |
1924 | return *this; |
1925 | } |
1926 | |
1927 | private: |
1928 | result_type Result; |
1929 | }; |
1930 | |
1931 | template <typename R> class enumerator { |
1932 | public: |
1933 | explicit enumerator(R &&Range) : TheRange(std::forward<R>(Range)) {} |
1934 | |
1935 | enumerator_iter<R> begin() { |
1936 | return enumerator_iter<R>(0, std::begin(TheRange)); |
1937 | } |
1938 | |
1939 | enumerator_iter<R> end() { |
1940 | return enumerator_iter<R>(std::end(TheRange)); |
1941 | } |
1942 | |
1943 | private: |
1944 | R TheRange; |
1945 | }; |
1946 | |
1947 | } // end namespace detail |
1948 | |
1949 | /// Given an input range, returns a new range whose values are are pair (A,B) |
1950 | /// such that A is the 0-based index of the item in the sequence, and B is |
1951 | /// the value from the original sequence. Example: |
1952 | /// |
1953 | /// std::vector<char> Items = {'A', 'B', 'C', 'D'}; |
1954 | /// for (auto X : enumerate(Items)) { |
1955 | /// printf("Item %d - %c\n", X.index(), X.value()); |
1956 | /// } |
1957 | /// |
1958 | /// Output: |
1959 | /// Item 0 - A |
1960 | /// Item 1 - B |
1961 | /// Item 2 - C |
1962 | /// Item 3 - D |
1963 | /// |
1964 | template <typename R> detail::enumerator<R> enumerate(R &&TheRange) { |
1965 | return detail::enumerator<R>(std::forward<R>(TheRange)); |
1966 | } |
1967 | |
1968 | namespace detail { |
1969 | |
1970 | template <typename F, typename Tuple, std::size_t... I> |
1971 | decltype(auto) apply_tuple_impl(F &&f, Tuple &&t, std::index_sequence<I...>) { |
1972 | return std::forward<F>(f)(std::get<I>(std::forward<Tuple>(t))...); |
1973 | } |
1974 | |
1975 | } // end namespace detail |
1976 | |
1977 | /// Given an input tuple (a1, a2, ..., an), pass the arguments of the |
1978 | /// tuple variadically to f as if by calling f(a1, a2, ..., an) and |
1979 | /// return the result. |
1980 | template <typename F, typename Tuple> |
1981 | decltype(auto) apply_tuple(F &&f, Tuple &&t) { |
1982 | using Indices = std::make_index_sequence< |
1983 | std::tuple_size<typename std::decay<Tuple>::type>::value>; |
1984 | |
1985 | return detail::apply_tuple_impl(std::forward<F>(f), std::forward<Tuple>(t), |
1986 | Indices{}); |
1987 | } |
1988 | |
1989 | /// Return true if the sequence [Begin, End) has exactly N items. Runs in O(N) |
1990 | /// time. Not meant for use with random-access iterators. |
1991 | /// Can optionally take a predicate to filter lazily some items. |
1992 | template <typename IterTy, |
1993 | typename Pred = bool (*)(const decltype(*std::declval<IterTy>()) &)> |
1994 | bool hasNItems( |
1995 | IterTy &&Begin, IterTy &&End, unsigned N, |
1996 | Pred &&ShouldBeCounted = |
1997 | [](const decltype(*std::declval<IterTy>()) &) { return true; }, |
1998 | std::enable_if_t< |
1999 | !std::is_base_of<std::random_access_iterator_tag, |
2000 | typename std::iterator_traits<std::remove_reference_t< |
2001 | decltype(Begin)>>::iterator_category>::value, |
2002 | void> * = nullptr) { |
2003 | for (; N; ++Begin) { |
2004 | if (Begin == End) |
2005 | return false; // Too few. |
2006 | N -= ShouldBeCounted(*Begin); |
2007 | } |
2008 | for (; Begin != End; ++Begin) |
2009 | if (ShouldBeCounted(*Begin)) |
2010 | return false; // Too many. |
2011 | return true; |
2012 | } |
2013 | |
2014 | /// Return true if the sequence [Begin, End) has N or more items. Runs in O(N) |
2015 | /// time. Not meant for use with random-access iterators. |
2016 | /// Can optionally take a predicate to lazily filter some items. |
2017 | template <typename IterTy, |
2018 | typename Pred = bool (*)(const decltype(*std::declval<IterTy>()) &)> |
2019 | bool hasNItemsOrMore( |
2020 | IterTy &&Begin, IterTy &&End, unsigned N, |
2021 | Pred &&ShouldBeCounted = |
2022 | [](const decltype(*std::declval<IterTy>()) &) { return true; }, |
2023 | std::enable_if_t< |
2024 | !std::is_base_of<std::random_access_iterator_tag, |
2025 | typename std::iterator_traits<std::remove_reference_t< |
2026 | decltype(Begin)>>::iterator_category>::value, |
2027 | void> * = nullptr) { |
2028 | for (; N; ++Begin) { |
2029 | if (Begin == End) |
2030 | return false; // Too few. |
2031 | N -= ShouldBeCounted(*Begin); |
2032 | } |
2033 | return true; |
2034 | } |
2035 | |
2036 | /// Returns true if the sequence [Begin, End) has N or less items. Can |
2037 | /// optionally take a predicate to lazily filter some items. |
2038 | template <typename IterTy, |
2039 | typename Pred = bool (*)(const decltype(*std::declval<IterTy>()) &)> |
2040 | bool hasNItemsOrLess( |
2041 | IterTy &&Begin, IterTy &&End, unsigned N, |
2042 | Pred &&ShouldBeCounted = [](const decltype(*std::declval<IterTy>()) &) { |
2043 | return true; |
2044 | }) { |
2045 | assert(N != std::numeric_limits<unsigned>::max())((void)0); |
2046 | return !hasNItemsOrMore(Begin, End, N + 1, ShouldBeCounted); |
2047 | } |
2048 | |
2049 | /// Returns true if the given container has exactly N items |
2050 | template <typename ContainerTy> bool hasNItems(ContainerTy &&C, unsigned N) { |
2051 | return hasNItems(std::begin(C), std::end(C), N); |
2052 | } |
2053 | |
2054 | /// Returns true if the given container has N or more items |
2055 | template <typename ContainerTy> |
2056 | bool hasNItemsOrMore(ContainerTy &&C, unsigned N) { |
2057 | return hasNItemsOrMore(std::begin(C), std::end(C), N); |
2058 | } |
2059 | |
2060 | /// Returns true if the given container has N or less items |
2061 | template <typename ContainerTy> |
2062 | bool hasNItemsOrLess(ContainerTy &&C, unsigned N) { |
2063 | return hasNItemsOrLess(std::begin(C), std::end(C), N); |
2064 | } |
2065 | |
2066 | /// Returns a raw pointer that represents the same address as the argument. |
2067 | /// |
2068 | /// This implementation can be removed once we move to C++20 where it's defined |
2069 | /// as std::to_address(). |
2070 | /// |
2071 | /// The std::pointer_traits<>::to_address(p) variations of these overloads has |
2072 | /// not been implemented. |
2073 | template <class Ptr> auto to_address(const Ptr &P) { return P.operator->(); } |
2074 | template <class T> constexpr T *to_address(T *P) { return P; } |
2075 | |
2076 | } // end namespace llvm |
2077 | |
2078 | #endif // LLVM_ADT_STLEXTRAS_H |
1 | //===- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file contains the declaration of the MachineInstr class, which is the |
10 | // basic representation for all target dependent machine instructions used by |
11 | // the back end. |
12 | // |
13 | //===----------------------------------------------------------------------===// |
14 | |
15 | #ifndef LLVM_CODEGEN_MACHINEINSTR_H |
16 | #define LLVM_CODEGEN_MACHINEINSTR_H |
17 | |
18 | #include "llvm/ADT/DenseMapInfo.h" |
19 | #include "llvm/ADT/PointerSumType.h" |
20 | #include "llvm/ADT/SmallSet.h" |
21 | #include "llvm/ADT/ilist.h" |
22 | #include "llvm/ADT/ilist_node.h" |
23 | #include "llvm/ADT/iterator_range.h" |
24 | #include "llvm/CodeGen/MachineMemOperand.h" |
25 | #include "llvm/CodeGen/MachineOperand.h" |
26 | #include "llvm/CodeGen/TargetOpcodes.h" |
27 | #include "llvm/IR/DebugLoc.h" |
28 | #include "llvm/IR/InlineAsm.h" |
29 | #include "llvm/IR/PseudoProbe.h" |
30 | #include "llvm/MC/MCInstrDesc.h" |
31 | #include "llvm/MC/MCSymbol.h" |
32 | #include "llvm/Support/ArrayRecycler.h" |
33 | #include "llvm/Support/TrailingObjects.h" |
34 | #include <algorithm> |
35 | #include <cassert> |
36 | #include <cstdint> |
37 | #include <utility> |
38 | |
39 | namespace llvm { |
40 | |
41 | class AAResults; |
42 | template <typename T> class ArrayRef; |
43 | class DIExpression; |
44 | class DILocalVariable; |
45 | class MachineBasicBlock; |
46 | class MachineFunction; |
47 | class MachineRegisterInfo; |
48 | class ModuleSlotTracker; |
49 | class raw_ostream; |
50 | template <typename T> class SmallVectorImpl; |
51 | class SmallBitVector; |
52 | class StringRef; |
53 | class TargetInstrInfo; |
54 | class TargetRegisterClass; |
55 | class TargetRegisterInfo; |
56 | |
57 | //===----------------------------------------------------------------------===// |
58 | /// Representation of each machine instruction. |
59 | /// |
60 | /// This class isn't a POD type, but it must have a trivial destructor. When a |
61 | /// MachineFunction is deleted, all the contained MachineInstrs are deallocated |
62 | /// without having their destructor called. |
63 | /// |
64 | class MachineInstr |
65 | : public ilist_node_with_parent<MachineInstr, MachineBasicBlock, |
66 | ilist_sentinel_tracking<true>> { |
67 | public: |
68 | using mmo_iterator = ArrayRef<MachineMemOperand *>::iterator; |
69 | |
70 | /// Flags to specify different kinds of comments to output in |
71 | /// assembly code. These flags carry semantic information not |
72 | /// otherwise easily derivable from the IR text. |
73 | /// |
74 | enum CommentFlag { |
75 | ReloadReuse = 0x1, // higher bits are reserved for target dep comments. |
76 | NoSchedComment = 0x2, |
77 | TAsmComments = 0x4 // Target Asm comments should start from this value. |
78 | }; |
79 | |
80 | enum MIFlag { |
81 | NoFlags = 0, |
82 | FrameSetup = 1 << 0, // Instruction is used as a part of |
83 | // function frame setup code. |
84 | FrameDestroy = 1 << 1, // Instruction is used as a part of |
85 | // function frame destruction code. |
86 | BundledPred = 1 << 2, // Instruction has bundled predecessors. |
87 | BundledSucc = 1 << 3, // Instruction has bundled successors. |
88 | FmNoNans = 1 << 4, // Instruction does not support Fast |
89 | // math nan values. |
90 | FmNoInfs = 1 << 5, // Instruction does not support Fast |
91 | // math infinity values. |
92 | FmNsz = 1 << 6, // Instruction is not required to retain |
93 | // signed zero values. |
94 | FmArcp = 1 << 7, // Instruction supports Fast math |
95 | // reciprocal approximations. |
96 | FmContract = 1 << 8, // Instruction supports Fast math |
97 | // contraction operations like fma. |
98 | FmAfn = 1 << 9, // Instruction may map to Fast math |
99 | // instrinsic approximation. |
100 | FmReassoc = 1 << 10, // Instruction supports Fast math |
101 | // reassociation of operand order. |
102 | NoUWrap = 1 << 11, // Instruction supports binary operator |
103 | // no unsigned wrap. |
104 | NoSWrap = 1 << 12, // Instruction supports binary operator |
105 | // no signed wrap. |
106 | IsExact = 1 << 13, // Instruction supports division is |
107 | // known to be exact. |
108 | NoFPExcept = 1 << 14, // Instruction does not raise |
109 | // floatint-point exceptions. |
110 | NoMerge = 1 << 15, // Passes that drop source location info |
111 | // (e.g. branch folding) should skip |
112 | // this instruction. |
113 | }; |
114 | |
115 | private: |
116 | const MCInstrDesc *MCID; // Instruction descriptor. |
117 | MachineBasicBlock *Parent = nullptr; // Pointer to the owning basic block. |
118 | |
119 | // Operands are allocated by an ArrayRecycler. |
120 | MachineOperand *Operands = nullptr; // Pointer to the first operand. |
121 | unsigned NumOperands = 0; // Number of operands on instruction. |
122 | |
123 | uint16_t Flags = 0; // Various bits of additional |
124 | // information about machine |
125 | // instruction. |
126 | |
127 | uint8_t AsmPrinterFlags = 0; // Various bits of information used by |
128 | // the AsmPrinter to emit helpful |
129 | // comments. This is *not* semantic |
130 | // information. Do not use this for |
131 | // anything other than to convey comment |
132 | // information to AsmPrinter. |
133 | |
134 | // OperandCapacity has uint8_t size, so it should be next to AsmPrinterFlags |
135 | // to properly pack. |
136 | using OperandCapacity = ArrayRecycler<MachineOperand>::Capacity; |
137 | OperandCapacity CapOperands; // Capacity of the Operands array. |
138 | |
139 | /// Internal implementation detail class that provides out-of-line storage for |
140 | /// extra info used by the machine instruction when this info cannot be stored |
141 | /// in-line within the instruction itself. |
142 | /// |
143 | /// This has to be defined eagerly due to the implementation constraints of |
144 | /// `PointerSumType` where it is used. |
145 | class ExtraInfo final |
146 | : TrailingObjects<ExtraInfo, MachineMemOperand *, MCSymbol *, MDNode *> { |
147 | public: |
148 | static ExtraInfo *create(BumpPtrAllocator &Allocator, |
149 | ArrayRef<MachineMemOperand *> MMOs, |
150 | MCSymbol *PreInstrSymbol = nullptr, |
151 | MCSymbol *PostInstrSymbol = nullptr, |
152 | MDNode *HeapAllocMarker = nullptr) { |
153 | bool HasPreInstrSymbol = PreInstrSymbol != nullptr; |
154 | bool HasPostInstrSymbol = PostInstrSymbol != nullptr; |
155 | bool HasHeapAllocMarker = HeapAllocMarker != nullptr; |
156 | auto *Result = new (Allocator.Allocate( |
157 | totalSizeToAlloc<MachineMemOperand *, MCSymbol *, MDNode *>( |
158 | MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol, |
159 | HasHeapAllocMarker), |
160 | alignof(ExtraInfo))) |
161 | ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol, |
162 | HasHeapAllocMarker); |
163 | |
164 | // Copy the actual data into the trailing objects. |
165 | std::copy(MMOs.begin(), MMOs.end(), |
166 | Result->getTrailingObjects<MachineMemOperand *>()); |
167 | |
168 | if (HasPreInstrSymbol) |
169 | Result->getTrailingObjects<MCSymbol *>()[0] = PreInstrSymbol; |
170 | if (HasPostInstrSymbol) |
171 | Result->getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] = |
172 | PostInstrSymbol; |
173 | if (HasHeapAllocMarker) |
174 | Result->getTrailingObjects<MDNode *>()[0] = HeapAllocMarker; |
175 | |
176 | return Result; |
177 | } |
178 | |
179 | ArrayRef<MachineMemOperand *> getMMOs() const { |
180 | return makeArrayRef(getTrailingObjects<MachineMemOperand *>(), NumMMOs); |
181 | } |
182 | |
183 | MCSymbol *getPreInstrSymbol() const { |
184 | return HasPreInstrSymbol ? getTrailingObjects<MCSymbol *>()[0] : nullptr; |
185 | } |
186 | |
187 | MCSymbol *getPostInstrSymbol() const { |
188 | return HasPostInstrSymbol |
189 | ? getTrailingObjects<MCSymbol *>()[HasPreInstrSymbol] |
190 | : nullptr; |
191 | } |
192 | |
193 | MDNode *getHeapAllocMarker() const { |
194 | return HasHeapAllocMarker ? getTrailingObjects<MDNode *>()[0] : nullptr; |
195 | } |
196 | |
197 | private: |
198 | friend TrailingObjects; |
199 | |
200 | // Description of the extra info, used to interpret the actual optional |
201 | // data appended. |
202 | // |
203 | // Note that this is not terribly space optimized. This leaves a great deal |
204 | // of flexibility to fit more in here later. |
205 | const int NumMMOs; |
206 | const bool HasPreInstrSymbol; |
207 | const bool HasPostInstrSymbol; |
208 | const bool HasHeapAllocMarker; |
209 | |
210 | // Implement the `TrailingObjects` internal API. |
211 | size_t numTrailingObjects(OverloadToken<MachineMemOperand *>) const { |
212 | return NumMMOs; |
213 | } |
214 | size_t numTrailingObjects(OverloadToken<MCSymbol *>) const { |
215 | return HasPreInstrSymbol + HasPostInstrSymbol; |
216 | } |
217 | size_t numTrailingObjects(OverloadToken<MDNode *>) const { |
218 | return HasHeapAllocMarker; |
219 | } |
220 | |
221 | // Just a boring constructor to allow us to initialize the sizes. Always use |
222 | // the `create` routine above. |
223 | ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol, |
224 | bool HasHeapAllocMarker) |
225 | : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol), |
226 | HasPostInstrSymbol(HasPostInstrSymbol), |
227 | HasHeapAllocMarker(HasHeapAllocMarker) {} |
228 | }; |
229 | |
230 | /// Enumeration of the kinds of inline extra info available. It is important |
231 | /// that the `MachineMemOperand` inline kind has a tag value of zero to make |
232 | /// it accessible as an `ArrayRef`. |
233 | enum ExtraInfoInlineKinds { |
234 | EIIK_MMO = 0, |
235 | EIIK_PreInstrSymbol, |
236 | EIIK_PostInstrSymbol, |
237 | EIIK_OutOfLine |
238 | }; |
239 | |
240 | // We store extra information about the instruction here. The common case is |
241 | // expected to be nothing or a single pointer (typically a MMO or a symbol). |
242 | // We work to optimize this common case by storing it inline here rather than |
243 | // requiring a separate allocation, but we fall back to an allocation when |
244 | // multiple pointers are needed. |
245 | PointerSumType<ExtraInfoInlineKinds, |
246 | PointerSumTypeMember<EIIK_MMO, MachineMemOperand *>, |
247 | PointerSumTypeMember<EIIK_PreInstrSymbol, MCSymbol *>, |
248 | PointerSumTypeMember<EIIK_PostInstrSymbol, MCSymbol *>, |
249 | PointerSumTypeMember<EIIK_OutOfLine, ExtraInfo *>> |
250 | Info; |
251 | |
252 | DebugLoc debugLoc; // Source line information. |
253 | |
254 | /// Unique instruction number. Used by DBG_INSTR_REFs to refer to the values |
255 | /// defined by this instruction. |
256 | unsigned DebugInstrNum; |
257 | |
258 | // Intrusive list support |
259 | friend struct ilist_traits<MachineInstr>; |
260 | friend struct ilist_callback_traits<MachineBasicBlock>; |
261 | void setParent(MachineBasicBlock *P) { Parent = P; } |
262 | |
263 | /// This constructor creates a copy of the given |
264 | /// MachineInstr in the given MachineFunction. |
265 | MachineInstr(MachineFunction &, const MachineInstr &); |
266 | |
267 | /// This constructor create a MachineInstr and add the implicit operands. |
268 | /// It reserves space for number of operands specified by |
269 | /// MCInstrDesc. An explicit DebugLoc is supplied. |
270 | MachineInstr(MachineFunction &, const MCInstrDesc &tid, DebugLoc dl, |
271 | bool NoImp = false); |
272 | |
273 | // MachineInstrs are pool-allocated and owned by MachineFunction. |
274 | friend class MachineFunction; |
275 | |
276 | void |
277 | dumprImpl(const MachineRegisterInfo &MRI, unsigned Depth, unsigned MaxDepth, |
278 | SmallPtrSetImpl<const MachineInstr *> &AlreadySeenInstrs) const; |
279 | |
280 | public: |
281 | MachineInstr(const MachineInstr &) = delete; |
282 | MachineInstr &operator=(const MachineInstr &) = delete; |
283 | // Use MachineFunction::DeleteMachineInstr() instead. |
284 | ~MachineInstr() = delete; |
285 | |
286 | const MachineBasicBlock* getParent() const { return Parent; } |
287 | MachineBasicBlock* getParent() { return Parent; } |
288 | |
289 | /// Move the instruction before \p MovePos. |
290 | void moveBefore(MachineInstr *MovePos); |
291 | |
292 | /// Return the function that contains the basic block that this instruction |
293 | /// belongs to. |
294 | /// |
295 | /// Note: this is undefined behaviour if the instruction does not have a |
296 | /// parent. |
297 | const MachineFunction *getMF() const; |
298 | MachineFunction *getMF() { |
299 | return const_cast<MachineFunction *>( |
300 | static_cast<const MachineInstr *>(this)->getMF()); |
301 | } |
302 | |
303 | /// Return the asm printer flags bitvector. |
304 | uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; } |
305 | |
306 | /// Clear the AsmPrinter bitvector. |
307 | void clearAsmPrinterFlags() { AsmPrinterFlags = 0; } |
308 | |
309 | /// Return whether an AsmPrinter flag is set. |
310 | bool getAsmPrinterFlag(CommentFlag Flag) const { |
311 | return AsmPrinterFlags & Flag; |
312 | } |
313 | |
314 | /// Set a flag for the AsmPrinter. |
315 | void setAsmPrinterFlag(uint8_t Flag) { |
316 | AsmPrinterFlags |= Flag; |
317 | } |
318 | |
319 | /// Clear specific AsmPrinter flags. |
320 | void clearAsmPrinterFlag(CommentFlag Flag) { |
321 | AsmPrinterFlags &= ~Flag; |
322 | } |
323 | |
324 | /// Return the MI flags bitvector. |
325 | uint16_t getFlags() const { |
326 | return Flags; |
327 | } |
328 | |
329 | /// Return whether an MI flag is set. |
330 | bool getFlag(MIFlag Flag) const { |
331 | return Flags & Flag; |
332 | } |
333 | |
334 | /// Set a MI flag. |
335 | void setFlag(MIFlag Flag) { |
336 | Flags |= (uint16_t)Flag; |
337 | } |
338 | |
339 | void setFlags(unsigned flags) { |
340 | // Filter out the automatically maintained flags. |
341 | unsigned Mask = BundledPred | BundledSucc; |
342 | Flags = (Flags & Mask) | (flags & ~Mask); |
343 | } |
344 | |
345 | /// clearFlag - Clear a MI flag. |
346 | void clearFlag(MIFlag Flag) { |
347 | Flags &= ~((uint16_t)Flag); |
348 | } |
349 | |
350 | /// Return true if MI is in a bundle (but not the first MI in a bundle). |
351 | /// |
352 | /// A bundle looks like this before it's finalized: |
353 | /// ---------------- |
354 | /// | MI | |
355 | /// ---------------- |
356 | /// | |
357 | /// ---------------- |
358 | /// | MI * | |
359 | /// ---------------- |
360 | /// | |
361 | /// ---------------- |
362 | /// | MI * | |
363 | /// ---------------- |
364 | /// In this case, the first MI starts a bundle but is not inside a bundle, the |
365 | /// next 2 MIs are considered "inside" the bundle. |
366 | /// |
367 | /// After a bundle is finalized, it looks like this: |
368 | /// ---------------- |
369 | /// | Bundle | |
370 | /// ---------------- |
371 | /// | |
372 | /// ---------------- |
373 | /// | MI * | |
374 | /// ---------------- |
375 | /// | |
376 | /// ---------------- |
377 | /// | MI * | |
378 | /// ---------------- |
379 | /// | |
380 | /// ---------------- |
381 | /// | MI * | |
382 | /// ---------------- |
383 | /// The first instruction has the special opcode "BUNDLE". It's not "inside" |
384 | /// a bundle, but the next three MIs are. |
385 | bool isInsideBundle() const { |
386 | return getFlag(BundledPred); |
387 | } |
388 | |
389 | /// Return true if this instruction part of a bundle. This is true |
390 | /// if either itself or its following instruction is marked "InsideBundle". |
391 | bool isBundled() const { |
392 | return isBundledWithPred() || isBundledWithSucc(); |
393 | } |
394 | |
395 | /// Return true if this instruction is part of a bundle, and it is not the |
396 | /// first instruction in the bundle. |
397 | bool isBundledWithPred() const { return getFlag(BundledPred); } |
398 | |
399 | /// Return true if this instruction is part of a bundle, and it is not the |
400 | /// last instruction in the bundle. |
401 | bool isBundledWithSucc() const { return getFlag(BundledSucc); } |
402 | |
403 | /// Bundle this instruction with its predecessor. This can be an unbundled |
404 | /// instruction, or it can be the first instruction in a bundle. |
405 | void bundleWithPred(); |
406 | |
407 | /// Bundle this instruction with its successor. This can be an unbundled |
408 | /// instruction, or it can be the last instruction in a bundle. |
409 | void bundleWithSucc(); |
410 | |
411 | /// Break bundle above this instruction. |
412 | void unbundleFromPred(); |
413 | |
414 | /// Break bundle below this instruction. |
415 | void unbundleFromSucc(); |
416 | |
417 | /// Returns the debug location id of this MachineInstr. |
418 | const DebugLoc &getDebugLoc() const { return debugLoc; } |
419 | |
420 | /// Return the operand containing the offset to be used if this DBG_VALUE |
421 | /// instruction is indirect; will be an invalid register if this value is |
422 | /// not indirect, and an immediate with value 0 otherwise. |
423 | const MachineOperand &getDebugOffset() const { |
424 | assert(isNonListDebugValue() && "not a DBG_VALUE")((void)0); |
425 | return getOperand(1); |
426 | } |
427 | MachineOperand &getDebugOffset() { |
428 | assert(isNonListDebugValue() && "not a DBG_VALUE")((void)0); |
429 | return getOperand(1); |
430 | } |
431 | |
432 | /// Return the operand for the debug variable referenced by |
433 | /// this DBG_VALUE instruction. |
434 | const MachineOperand &getDebugVariableOp() const; |
435 | MachineOperand &getDebugVariableOp(); |
436 | |
437 | /// Return the debug variable referenced by |
438 | /// this DBG_VALUE instruction. |
439 | const DILocalVariable *getDebugVariable() const; |
440 | |
441 | /// Return the operand for the complex address expression referenced by |
442 | /// this DBG_VALUE instruction. |
443 | const MachineOperand &getDebugExpressionOp() const; |
444 | MachineOperand &getDebugExpressionOp(); |
445 | |
446 | /// Return the complex address expression referenced by |
447 | /// this DBG_VALUE instruction. |
448 | const DIExpression *getDebugExpression() const; |
449 | |
450 | /// Return the debug label referenced by |
451 | /// this DBG_LABEL instruction. |
452 | const DILabel *getDebugLabel() const; |
453 | |
454 | /// Fetch the instruction number of this MachineInstr. If it does not have |
455 | /// one already, a new and unique number will be assigned. |
456 | unsigned getDebugInstrNum(); |
457 | |
458 | /// Fetch instruction number of this MachineInstr -- but before it's inserted |
459 | /// into \p MF. Needed for transformations that create an instruction but |
460 | /// don't immediately insert them. |
461 | unsigned getDebugInstrNum(MachineFunction &MF); |
462 | |
463 | /// Examine the instruction number of this MachineInstr. May be zero if |
464 | /// it hasn't been assigned a number yet. |
465 | unsigned peekDebugInstrNum() const { return DebugInstrNum; } |
466 | |
467 | /// Set instruction number of this MachineInstr. Avoid using unless you're |
468 | /// deserializing this information. |
469 | void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; } |
470 | |
471 | /// Drop any variable location debugging information associated with this |
472 | /// instruction. Use when an instruction is modified in such a way that it no |
473 | /// longer defines the value it used to. Variable locations using that value |
474 | /// will be dropped. |
475 | void dropDebugNumber() { DebugInstrNum = 0; } |
476 | |
477 | /// Emit an error referring to the source location of this instruction. |
478 | /// This should only be used for inline assembly that is somehow |
479 | /// impossible to compile. Other errors should have been handled much |
480 | /// earlier. |
481 | /// |
482 | /// If this method returns, the caller should try to recover from the error. |
483 | void emitError(StringRef Msg) const; |
484 | |
485 | /// Returns the target instruction descriptor of this MachineInstr. |
486 | const MCInstrDesc &getDesc() const { return *MCID; } |
487 | |
488 | /// Returns the opcode of this MachineInstr. |
489 | unsigned getOpcode() const { return MCID->Opcode; } |
490 | |
491 | /// Retuns the total number of operands. |
492 | unsigned getNumOperands() const { return NumOperands; } |
493 | |
494 | /// Returns the total number of operands which are debug locations. |
495 | unsigned getNumDebugOperands() const { |
496 | return std::distance(debug_operands().begin(), debug_operands().end()); |
497 | } |
498 | |
499 | const MachineOperand& getOperand(unsigned i) const { |
500 | assert(i < getNumOperands() && "getOperand() out of range!")((void)0); |
501 | return Operands[i]; |
502 | } |
503 | MachineOperand& getOperand(unsigned i) { |
504 | assert(i < getNumOperands() && "getOperand() out of range!")((void)0); |
505 | return Operands[i]; |
506 | } |
507 | |
508 | MachineOperand &getDebugOperand(unsigned Index) { |
509 | assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!")((void)0); |
510 | return *(debug_operands().begin() + Index); |
511 | } |
512 | const MachineOperand &getDebugOperand(unsigned Index) const { |
513 | assert(Index < getNumDebugOperands() && "getDebugOperand() out of range!")((void)0); |
514 | return *(debug_operands().begin() + Index); |
515 | } |
516 | |
517 | SmallSet<Register, 4> getUsedDebugRegs() const { |
518 | assert(isDebugValue() && "not a DBG_VALUE*")((void)0); |
519 | SmallSet<Register, 4> UsedRegs; |
520 | for (auto MO : debug_operands()) |
521 | if (MO.isReg() && MO.getReg()) |
522 | UsedRegs.insert(MO.getReg()); |
523 | return UsedRegs; |
524 | } |
525 | |
526 | /// Returns whether this debug value has at least one debug operand with the |
527 | /// register \p Reg. |
528 | bool hasDebugOperandForReg(Register Reg) const { |
529 | return any_of(debug_operands(), [Reg](const MachineOperand &Op) { |
530 | return Op.isReg() && Op.getReg() == Reg; |
531 | }); |
532 | } |
533 | |
534 | /// Returns a range of all of the operands that correspond to a debug use of |
535 | /// \p Reg. |
536 | template <typename Operand, typename Instruction> |
537 | static iterator_range< |
538 | filter_iterator<Operand *, std::function<bool(Operand &Op)>>> |
539 | getDebugOperandsForReg(Instruction *MI, Register Reg) { |
540 | std::function<bool(Operand & Op)> OpUsesReg( |
541 | [Reg](Operand &Op) { return Op.isReg() && Op.getReg() == Reg; }); |
542 | return make_filter_range(MI->debug_operands(), OpUsesReg); |
543 | } |
544 | iterator_range<filter_iterator<const MachineOperand *, |
545 | std::function<bool(const MachineOperand &Op)>>> |
546 | getDebugOperandsForReg(Register Reg) const { |
547 | return MachineInstr::getDebugOperandsForReg<const MachineOperand, |
548 | const MachineInstr>(this, Reg); |
549 | } |
550 | iterator_range<filter_iterator<MachineOperand *, |
551 | std::function<bool(MachineOperand &Op)>>> |
552 | getDebugOperandsForReg(Register Reg) { |
553 | return MachineInstr::getDebugOperandsForReg<MachineOperand, MachineInstr>( |
554 | this, Reg); |
555 | } |
556 | |
557 | bool isDebugOperand(const MachineOperand *Op) const { |
558 | return Op >= adl_begin(debug_operands()) && Op <= adl_end(debug_operands()); |
559 | } |
560 | |
561 | unsigned getDebugOperandIndex(const MachineOperand *Op) const { |
562 | assert(isDebugOperand(Op) && "Expected a debug operand.")((void)0); |
563 | return std::distance(adl_begin(debug_operands()), Op); |
564 | } |
565 | |
566 | /// Returns the total number of definitions. |
567 | unsigned getNumDefs() const { |
568 | return getNumExplicitDefs() + MCID->getNumImplicitDefs(); |
569 | } |
570 | |
571 | /// Returns true if the instruction has implicit definition. |
572 | bool hasImplicitDef() const { |
573 | for (unsigned I = getNumExplicitOperands(), E = getNumOperands(); |
574 | I != E; ++I) { |
575 | const MachineOperand &MO = getOperand(I); |
576 | if (MO.isDef() && MO.isImplicit()) |
577 | return true; |
578 | } |
579 | return false; |
580 | } |
581 | |
582 | /// Returns the implicit operands number. |
583 | unsigned getNumImplicitOperands() const { |
584 | return getNumOperands() - getNumExplicitOperands(); |
585 | } |
586 | |
587 | /// Return true if operand \p OpIdx is a subregister index. |
588 | bool isOperandSubregIdx(unsigned OpIdx) const { |
589 | assert(getOperand(OpIdx).getType() == MachineOperand::MO_Immediate &&((void)0) |
590 | "Expected MO_Immediate operand type.")((void)0); |
591 | if (isExtractSubreg() && OpIdx == 2) |
592 | return true; |
593 | if (isInsertSubreg() && OpIdx == 3) |
594 | return true; |
595 | if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0) |
596 | return true; |
597 | if (isSubregToReg() && OpIdx == 3) |
598 | return true; |
599 | return false; |
600 | } |
601 | |
602 | /// Returns the number of non-implicit operands. |
603 | unsigned getNumExplicitOperands() const; |
604 | |
605 | /// Returns the number of non-implicit definitions. |
606 | unsigned getNumExplicitDefs() const; |
607 | |
608 | /// iterator/begin/end - Iterate over all operands of a machine instruction. |
609 | using mop_iterator = MachineOperand *; |
610 | using const_mop_iterator = const MachineOperand *; |
611 | |
612 | mop_iterator operands_begin() { return Operands; } |
613 | mop_iterator operands_end() { return Operands + NumOperands; } |
614 | |
615 | const_mop_iterator operands_begin() const { return Operands; } |
616 | const_mop_iterator operands_end() const { return Operands + NumOperands; } |
617 | |
618 | iterator_range<mop_iterator> operands() { |
619 | return make_range(operands_begin(), operands_end()); |
620 | } |
621 | iterator_range<const_mop_iterator> operands() const { |
622 | return make_range(operands_begin(), operands_end()); |
623 | } |
624 | iterator_range<mop_iterator> explicit_operands() { |
625 | return make_range(operands_begin(), |
626 | operands_begin() + getNumExplicitOperands()); |
627 | } |
628 | iterator_range<const_mop_iterator> explicit_operands() const { |
629 | return make_range(operands_begin(), |
630 | operands_begin() + getNumExplicitOperands()); |
631 | } |
632 | iterator_range<mop_iterator> implicit_operands() { |
633 | return make_range(explicit_operands().end(), operands_end()); |
634 | } |
635 | iterator_range<const_mop_iterator> implicit_operands() const { |
636 | return make_range(explicit_operands().end(), operands_end()); |
637 | } |
638 | /// Returns a range over all operands that are used to determine the variable |
639 | /// location for this DBG_VALUE instruction. |
640 | iterator_range<mop_iterator> debug_operands() { |
641 | assert(isDebugValue() && "Must be a debug value instruction.")((void)0); |
642 | return isDebugValueList() |
643 | ? make_range(operands_begin() + 2, operands_end()) |
644 | : make_range(operands_begin(), operands_begin() + 1); |
645 | } |
646 | /// \copydoc debug_operands() |
647 | iterator_range<const_mop_iterator> debug_operands() const { |
648 | assert(isDebugValue() && "Must be a debug value instruction.")((void)0); |
649 | return isDebugValueList() |
650 | ? make_range(operands_begin() + 2, operands_end()) |
651 | : make_range(operands_begin(), operands_begin() + 1); |
652 | } |
653 | /// Returns a range over all explicit operands that are register definitions. |
654 | /// Implicit definition are not included! |
655 | iterator_range<mop_iterator> defs() { |
656 | return make_range(operands_begin(), |
657 | operands_begin() + getNumExplicitDefs()); |
658 | } |
659 | /// \copydoc defs() |
660 | iterator_range<const_mop_iterator> defs() const { |
661 | return make_range(operands_begin(), |
662 | operands_begin() + getNumExplicitDefs()); |
663 | } |
664 | /// Returns a range that includes all operands that are register uses. |
665 | /// This may include unrelated operands which are not register uses. |
666 | iterator_range<mop_iterator> uses() { |
667 | return make_range(operands_begin() + getNumExplicitDefs(), operands_end()); |
668 | } |
669 | /// \copydoc uses() |
670 | iterator_range<const_mop_iterator> uses() const { |
671 | return make_range(operands_begin() + getNumExplicitDefs(), operands_end()); |
672 | } |
673 | iterator_range<mop_iterator> explicit_uses() { |
674 | return make_range(operands_begin() + getNumExplicitDefs(), |
675 | operands_begin() + getNumExplicitOperands()); |
676 | } |
677 | iterator_range<const_mop_iterator> explicit_uses() const { |
678 | return make_range(operands_begin() + getNumExplicitDefs(), |
679 | operands_begin() + getNumExplicitOperands()); |
680 | } |
681 | |
682 | /// Returns the number of the operand iterator \p I points to. |
683 | unsigned getOperandNo(const_mop_iterator I) const { |
684 | return I - operands_begin(); |
685 | } |
686 | |
687 | /// Access to memory operands of the instruction. If there are none, that does |
688 | /// not imply anything about whether the function accesses memory. Instead, |
689 | /// the caller must behave conservatively. |
690 | ArrayRef<MachineMemOperand *> memoperands() const { |
691 | if (!Info) |
692 | return {}; |
693 | |
694 | if (Info.is<EIIK_MMO>()) |
695 | return makeArrayRef(Info.getAddrOfZeroTagPointer(), 1); |
696 | |
697 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
698 | return EI->getMMOs(); |
699 | |
700 | return {}; |
701 | } |
702 | |
703 | /// Access to memory operands of the instruction. |
704 | /// |
705 | /// If `memoperands_begin() == memoperands_end()`, that does not imply |
706 | /// anything about whether the function accesses memory. Instead, the caller |
707 | /// must behave conservatively. |
708 | mmo_iterator memoperands_begin() const { return memoperands().begin(); } |
709 | |
710 | /// Access to memory operands of the instruction. |
711 | /// |
712 | /// If `memoperands_begin() == memoperands_end()`, that does not imply |
713 | /// anything about whether the function accesses memory. Instead, the caller |
714 | /// must behave conservatively. |
715 | mmo_iterator memoperands_end() const { return memoperands().end(); } |
716 | |
717 | /// Return true if we don't have any memory operands which described the |
718 | /// memory access done by this instruction. If this is true, calling code |
719 | /// must be conservative. |
720 | bool memoperands_empty() const { return memoperands().empty(); } |
721 | |
722 | /// Return true if this instruction has exactly one MachineMemOperand. |
723 | bool hasOneMemOperand() const { return memoperands().size() == 1; } |
724 | |
725 | /// Return the number of memory operands. |
726 | unsigned getNumMemOperands() const { return memoperands().size(); } |
727 | |
728 | /// Helper to extract a pre-instruction symbol if one has been added. |
729 | MCSymbol *getPreInstrSymbol() const { |
730 | if (!Info) |
731 | return nullptr; |
732 | if (MCSymbol *S = Info.get<EIIK_PreInstrSymbol>()) |
733 | return S; |
734 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
735 | return EI->getPreInstrSymbol(); |
736 | |
737 | return nullptr; |
738 | } |
739 | |
740 | /// Helper to extract a post-instruction symbol if one has been added. |
741 | MCSymbol *getPostInstrSymbol() const { |
742 | if (!Info) |
743 | return nullptr; |
744 | if (MCSymbol *S = Info.get<EIIK_PostInstrSymbol>()) |
745 | return S; |
746 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
747 | return EI->getPostInstrSymbol(); |
748 | |
749 | return nullptr; |
750 | } |
751 | |
752 | /// Helper to extract a heap alloc marker if one has been added. |
753 | MDNode *getHeapAllocMarker() const { |
754 | if (!Info) |
755 | return nullptr; |
756 | if (ExtraInfo *EI = Info.get<EIIK_OutOfLine>()) |
757 | return EI->getHeapAllocMarker(); |
758 | |
759 | return nullptr; |
760 | } |
761 | |
762 | /// API for querying MachineInstr properties. They are the same as MCInstrDesc |
763 | /// queries but they are bundle aware. |
764 | |
765 | enum QueryType { |
766 | IgnoreBundle, // Ignore bundles |
767 | AnyInBundle, // Return true if any instruction in bundle has property |
768 | AllInBundle // Return true if all instructions in bundle have property |
769 | }; |
770 | |
771 | /// Return true if the instruction (or in the case of a bundle, |
772 | /// the instructions inside the bundle) has the specified property. |
773 | /// The first argument is the property being queried. |
774 | /// The second argument indicates whether the query should look inside |
775 | /// instruction bundles. |
776 | bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const { |
777 | assert(MCFlag < 64 &&((void)0) |
778 | "MCFlag out of range for bit mask in getFlags/hasPropertyInBundle.")((void)0); |
779 | // Inline the fast path for unbundled or bundle-internal instructions. |
780 | if (Type == IgnoreBundle || !isBundled() || isBundledWithPred()) |
781 | return getDesc().getFlags() & (1ULL << MCFlag); |
782 | |
783 | // If this is the first instruction in a bundle, take the slow path. |
784 | return hasPropertyInBundle(1ULL << MCFlag, Type); |
785 | } |
786 | |
787 | /// Return true if this is an instruction that should go through the usual |
788 | /// legalization steps. |
789 | bool isPreISelOpcode(QueryType Type = IgnoreBundle) const { |
790 | return hasProperty(MCID::PreISelOpcode, Type); |
791 | } |
792 | |
793 | /// Return true if this instruction can have a variable number of operands. |
794 | /// In this case, the variable operands will be after the normal |
795 | /// operands but before the implicit definitions and uses (if any are |
796 | /// present). |
797 | bool isVariadic(QueryType Type = IgnoreBundle) const { |
798 | return hasProperty(MCID::Variadic, Type); |
799 | } |
800 | |
801 | /// Set if this instruction has an optional definition, e.g. |
802 | /// ARM instructions which can set condition code if 's' bit is set. |
803 | bool hasOptionalDef(QueryType Type = IgnoreBundle) const { |
804 | return hasProperty(MCID::HasOptionalDef, Type); |
805 | } |
806 | |
807 | /// Return true if this is a pseudo instruction that doesn't |
808 | /// correspond to a real machine instruction. |
809 | bool isPseudo(QueryType Type = IgnoreBundle) const { |
810 | return hasProperty(MCID::Pseudo, Type); |
811 | } |
812 | |
813 | bool isReturn(QueryType Type = AnyInBundle) const { |
814 | return hasProperty(MCID::Return, Type); |
815 | } |
816 | |
817 | /// Return true if this is an instruction that marks the end of an EH scope, |
818 | /// i.e., a catchpad or a cleanuppad instruction. |
819 | bool isEHScopeReturn(QueryType Type = AnyInBundle) const { |
820 | return hasProperty(MCID::EHScopeReturn, Type); |
821 | } |
822 | |
823 | bool isCall(QueryType Type = AnyInBundle) const { |
824 | return hasProperty(MCID::Call, Type); |
825 | } |
826 | |
827 | /// Return true if this is a call instruction that may have an associated |
828 | /// call site entry in the debug info. |
829 | bool isCandidateForCallSiteEntry(QueryType Type = IgnoreBundle) const; |
830 | /// Return true if copying, moving, or erasing this instruction requires |
831 | /// updating Call Site Info (see \ref copyCallSiteInfo, \ref moveCallSiteInfo, |
832 | /// \ref eraseCallSiteInfo). |
833 | bool shouldUpdateCallSiteInfo() const; |
834 | |
835 | /// Returns true if the specified instruction stops control flow |
836 | /// from executing the instruction immediately following it. Examples include |
837 | /// unconditional branches and return instructions. |
838 | bool isBarrier(QueryType Type = AnyInBundle) const { |
839 | return hasProperty(MCID::Barrier, Type); |
840 | } |
841 | |
842 | /// Returns true if this instruction part of the terminator for a basic block. |
843 | /// Typically this is things like return and branch instructions. |
844 | /// |
845 | /// Various passes use this to insert code into the bottom of a basic block, |
846 | /// but before control flow occurs. |
847 | bool isTerminator(QueryType Type = AnyInBundle) const { |
848 | return hasProperty(MCID::Terminator, Type); |
849 | } |
850 | |
851 | /// Returns true if this is a conditional, unconditional, or indirect branch. |
852 | /// Predicates below can be used to discriminate between |
853 | /// these cases, and the TargetInstrInfo::analyzeBranch method can be used to |
854 | /// get more information. |
855 | bool isBranch(QueryType Type = AnyInBundle) const { |
856 | return hasProperty(MCID::Branch, Type); |
857 | } |
858 | |
859 | /// Return true if this is an indirect branch, such as a |
860 | /// branch through a register. |
861 | bool isIndirectBranch(QueryType Type = AnyInBundle) const { |
862 | return hasProperty(MCID::IndirectBranch, Type); |
863 | } |
864 | |
865 | /// Return true if this is a branch which may fall |
866 | /// through to the next instruction or may transfer control flow to some other |
867 | /// block. The TargetInstrInfo::analyzeBranch method can be used to get more |
868 | /// information about this branch. |
869 | bool isConditionalBranch(QueryType Type = AnyInBundle) const { |
870 | return isBranch(Type) && !isBarrier(Type) && !isIndirectBranch(Type); |
871 | } |
872 | |
873 | /// Return true if this is a branch which always |
874 | /// transfers control flow to some other block. The |
875 | /// TargetInstrInfo::analyzeBranch method can be used to get more information |
876 | /// about this branch. |
877 | bool isUnconditionalBranch(QueryType Type = AnyInBundle) const { |
878 | return isBranch(Type) && isBarrier(Type) && !isIndirectBranch(Type); |
879 | } |
880 | |
881 | /// Return true if this instruction has a predicate operand that |
882 | /// controls execution. It may be set to 'always', or may be set to other |
883 | /// values. There are various methods in TargetInstrInfo that can be used to |
884 | /// control and modify the predicate in this instruction. |
885 | bool isPredicable(QueryType Type = AllInBundle) const { |
886 | // If it's a bundle than all bundled instructions must be predicable for this |
887 | // to return true. |
888 | return hasProperty(MCID::Predicable, Type); |
889 | } |
890 | |
891 | /// Return true if this instruction is a comparison. |
892 | bool isCompare(QueryType Type = IgnoreBundle) const { |
893 | return hasProperty(MCID::Compare, Type); |
894 | } |
895 | |
896 | /// Return true if this instruction is a move immediate |
897 | /// (including conditional moves) instruction. |
898 | bool isMoveImmediate(QueryType Type = IgnoreBundle) const { |
899 | return hasProperty(MCID::MoveImm, Type); |
900 | } |
901 | |
902 | /// Return true if this instruction is a register move. |
903 | /// (including moving values from subreg to reg) |
904 | bool isMoveReg(QueryType Type = IgnoreBundle) const { |
905 | return hasProperty(MCID::MoveReg, Type); |
906 | } |
907 | |
908 | /// Return true if this instruction is a bitcast instruction. |
909 | bool isBitcast(QueryType Type = IgnoreBundle) const { |
910 | return hasProperty(MCID::Bitcast, Type); |
911 | } |
912 | |
913 | /// Return true if this instruction is a select instruction. |
914 | bool isSelect(QueryType Type = IgnoreBundle) const { |
915 | return hasProperty(MCID::Select, Type); |
916 | } |
917 | |
918 | /// Return true if this instruction cannot be safely duplicated. |
919 | /// For example, if the instruction has a unique labels attached |
920 | /// to it, duplicating it would cause multiple definition errors. |
921 | bool isNotDuplicable(QueryType Type = AnyInBundle) const { |
922 | return hasProperty(MCID::NotDuplicable, Type); |
923 | } |
924 | |
925 | /// Return true if this instruction is convergent. |
926 | /// Convergent instructions can not be made control-dependent on any |
927 | /// additional values. |
928 | bool isConvergent(QueryType Type = AnyInBundle) const { |
929 | if (isInlineAsm()) { |
930 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); |
931 | if (ExtraInfo & InlineAsm::Extra_IsConvergent) |
932 | return true; |
933 | } |
934 | return hasProperty(MCID::Convergent, Type); |
935 | } |
936 | |
937 | /// Returns true if the specified instruction has a delay slot |
938 | /// which must be filled by the code generator. |
939 | bool hasDelaySlot(QueryType Type = AnyInBundle) const { |
940 | return hasProperty(MCID::DelaySlot, Type); |
941 | } |
942 | |
943 | /// Return true for instructions that can be folded as |
944 | /// memory operands in other instructions. The most common use for this |
945 | /// is instructions that are simple loads from memory that don't modify |
946 | /// the loaded value in any way, but it can also be used for instructions |
947 | /// that can be expressed as constant-pool loads, such as V_SETALLONES |
948 | /// on x86, to allow them to be folded when it is beneficial. |
949 | /// This should only be set on instructions that return a value in their |
950 | /// only virtual register definition. |
951 | bool canFoldAsLoad(QueryType Type = IgnoreBundle) const { |
952 | return hasProperty(MCID::FoldableAsLoad, Type); |
953 | } |
954 | |
955 | /// Return true if this instruction behaves |
956 | /// the same way as the generic REG_SEQUENCE instructions. |
957 | /// E.g., on ARM, |
958 | /// dX VMOVDRR rY, rZ |
959 | /// is equivalent to |
960 | /// dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1. |
961 | /// |
962 | /// Note that for the optimizers to be able to take advantage of |
963 | /// this property, TargetInstrInfo::getRegSequenceLikeInputs has to be |
964 | /// override accordingly. |
965 | bool isRegSequenceLike(QueryType Type = IgnoreBundle) const { |
966 | return hasProperty(MCID::RegSequence, Type); |
967 | } |
968 | |
969 | /// Return true if this instruction behaves |
970 | /// the same way as the generic EXTRACT_SUBREG instructions. |
971 | /// E.g., on ARM, |
972 | /// rX, rY VMOVRRD dZ |
973 | /// is equivalent to two EXTRACT_SUBREG: |
974 | /// rX = EXTRACT_SUBREG dZ, ssub_0 |
975 | /// rY = EXTRACT_SUBREG dZ, ssub_1 |
976 | /// |
977 | /// Note that for the optimizers to be able to take advantage of |
978 | /// this property, TargetInstrInfo::getExtractSubregLikeInputs has to be |
979 | /// override accordingly. |
980 | bool isExtractSubregLike(QueryType Type = IgnoreBundle) const { |
981 | return hasProperty(MCID::ExtractSubreg, Type); |
982 | } |
983 | |
984 | /// Return true if this instruction behaves |
985 | /// the same way as the generic INSERT_SUBREG instructions. |
986 | /// E.g., on ARM, |
987 | /// dX = VSETLNi32 dY, rZ, Imm |
988 | /// is equivalent to a INSERT_SUBREG: |
989 | /// dX = INSERT_SUBREG dY, rZ, translateImmToSubIdx(Imm) |
990 | /// |
991 | /// Note that for the optimizers to be able to take advantage of |
992 | /// this property, TargetInstrInfo::getInsertSubregLikeInputs has to be |
993 | /// override accordingly. |
994 | bool isInsertSubregLike(QueryType Type = IgnoreBundle) const { |
995 | return hasProperty(MCID::InsertSubreg, Type); |
996 | } |
997 | |
998 | //===--------------------------------------------------------------------===// |
999 | // Side Effect Analysis |
1000 | //===--------------------------------------------------------------------===// |
1001 | |
1002 | /// Return true if this instruction could possibly read memory. |
1003 | /// Instructions with this flag set are not necessarily simple load |
1004 | /// instructions, they may load a value and modify it, for example. |
1005 | bool mayLoad(QueryType Type = AnyInBundle) const { |
1006 | if (isInlineAsm()) { |
1007 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); |
1008 | if (ExtraInfo & InlineAsm::Extra_MayLoad) |
1009 | return true; |
1010 | } |
1011 | return hasProperty(MCID::MayLoad, Type); |
1012 | } |
1013 | |
1014 | /// Return true if this instruction could possibly modify memory. |
1015 | /// Instructions with this flag set are not necessarily simple store |
1016 | /// instructions, they may store a modified value based on their operands, or |
1017 | /// may not actually modify anything, for example. |
1018 | bool mayStore(QueryType Type = AnyInBundle) const { |
1019 | if (isInlineAsm()) { |
1020 | unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm(); |
1021 | if (ExtraInfo & InlineAsm::Extra_MayStore) |
1022 | return true; |
1023 | } |
1024 | return hasProperty(MCID::MayStore, Type); |
1025 | } |
1026 | |
1027 | /// Return true if this instruction could possibly read or modify memory. |
1028 | bool mayLoadOrStore(QueryType Type = AnyInBundle) const { |
1029 | return mayLoad(Type) || mayStore(Type); |
1030 | } |
1031 | |
1032 | /// Return true if this instruction could possibly raise a floating-point |
1033 | /// exception. This is the case if the instruction is a floating-point |
1034 | /// instruction that can in principle raise an exception, as indicated |
1035 | /// by the MCID::MayRaiseFPException property, *and* at the same time, |
1036 | /// the instruction is used in a context where we expect floating-point |
1037 | /// exceptions are not disabled, as indicated by the NoFPExcept MI flag. |
1038 | bool mayRaiseFPException() const { |
1039 | return hasProperty(MCID::MayRaiseFPException) && |
1040 | !getFlag(MachineInstr::MIFlag::NoFPExcept); |
1041 | } |
1042 | |
1043 | //===--------------------------------------------------------------------===// |
1044 | // Flags that indicate whether an instruction can be modified by a method. |
1045 | //===--------------------------------------------------------------------===// |
1046 | |
1047 | /// Return true if this may be a 2- or 3-address |
1048 | /// instruction (of the form "X = op Y, Z, ..."), which produces the same |
1049 | /// result if Y and Z are exchanged. If this flag is set, then the |
1050 | /// TargetInstrInfo::commuteInstruction method may be used to hack on the |
1051 | /// instruction. |
1052 | /// |
1053 | /// Note that this flag may be set on instructions that are only commutable |
1054 | /// sometimes. In these cases, the call to commuteInstruction will fail. |
1055 | /// Also note that some instructions require non-trivial modification to |
1056 | /// commute them. |
1057 | bool isCommutable(QueryType Type = IgnoreBundle) const { |
1058 | return hasProperty(MCID::Commutable, Type); |
1059 | } |
1060 | |
1061 | /// Return true if this is a 2-address instruction |
1062 | /// which can be changed into a 3-address instruction if needed. Doing this |
1063 | /// transformation can be profitable in the register allocator, because it |
1064 | /// means that the instruction can use a 2-address form if possible, but |
1065 | /// degrade into a less efficient form if the source and dest register cannot |
1066 | /// be assigned to the same register. For example, this allows the x86 |
1067 | /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which |
1068 | /// is the same speed as the shift but has bigger code size. |
1069 | /// |
1070 | /// If this returns true, then the target must implement the |
1071 | /// TargetInstrInfo::convertToThreeAddress method for this instruction, which |
1072 | /// is allowed to fail if the transformation isn't valid for this specific |
1073 | /// instruction (e.g. shl reg, 4 on x86). |
1074 | /// |
1075 | bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const { |
1076 | return hasProperty(MCID::ConvertibleTo3Addr, Type); |
1077 | } |
1078 | |
1079 | /// Return true if this instruction requires |
1080 | /// custom insertion support when the DAG scheduler is inserting it into a |
1081 | /// machine basic block. If this is true for the instruction, it basically |
1082 | /// means that it is a pseudo instruction used at SelectionDAG time that is |
1083 | /// expanded out into magic code by the target when MachineInstrs are formed. |
1084 | /// |
1085 | /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method |
1086 | /// is used to insert this into the MachineBasicBlock. |
1087 | bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const { |
1088 | return hasProperty(MCID::UsesCustomInserter, Type); |
1089 | } |
1090 | |
1091 | /// Return true if this instruction requires *adjustment* |
1092 | /// after instruction selection by calling a target hook. For example, this |
1093 | /// can be used to fill in ARM 's' optional operand depending on whether |
1094 | /// the conditional flag register is used. |
1095 | bool hasPostISelHook(QueryType Type = IgnoreBundle) const { |
1096 | return hasProperty(MCID::HasPostISelHook, Type); |
1097 | } |
1098 | |
1099 | /// Returns true if this instruction is a candidate for remat. |
1100 | /// This flag is deprecated, please don't use it anymore. If this |
1101 | /// flag is set, the isReallyTriviallyReMaterializable() method is called to |
1102 | /// verify the instruction is really rematable. |
1103 | bool isRematerializable(QueryType Type = AllInBundle) const { |
1104 | // It's only possible to re-mat a bundle if all bundled instructions are |
1105 | // re-materializable. |
1106 | return hasProperty(MCID::Rematerializable, Type); |
1107 | } |
1108 | |
1109 | /// Returns true if this instruction has the same cost (or less) than a move |
1110 | /// instruction. This is useful during certain types of optimizations |
1111 | /// (e.g., remat during two-address conversion or machine licm) |
1112 | /// where we would like to remat or hoist the instruction, but not if it costs |
1113 | /// more than moving the instruction into the appropriate register. Note, we |
1114 | /// are not marking copies from and to the same register class with this flag. |
1115 | bool isAsCheapAsAMove(QueryType Type = AllInBundle) const { |
1116 | // Only returns true for a bundle if all bundled instructions are cheap. |
1117 | return hasProperty(MCID::CheapAsAMove, Type); |
1118 | } |
1119 | |
1120 | /// Returns true if this instruction source operands |
1121 | /// have special register allocation requirements that are not captured by the |
1122 | /// operand register classes. e.g. ARM::STRD's two source registers must be an |
1123 | /// even / odd pair, ARM::STM registers have to be in ascending order. |
1124 | /// Post-register allocation passes should not attempt to change allocations |
1125 | /// for sources of instructions with this flag. |
1126 | bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const { |
1127 | return hasProperty(MCID::ExtraSrcRegAllocReq, Type); |
1128 | } |
1129 | |
1130 | /// Returns true if this instruction def operands |
1131 | /// have special register allocation requirements that are not captured by the |
1132 | /// operand register classes. e.g. ARM::LDRD's two def registers must be an |
1133 | /// even / odd pair, ARM::LDM registers have to be in ascending order. |
1134 | /// Post-register allocation passes should not attempt to change allocations |
1135 | /// for definitions of instructions with this flag. |
1136 | bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const { |
1137 | return hasProperty(MCID::ExtraDefRegAllocReq, Type); |
1138 | } |
1139 | |
1140 | enum MICheckType { |
1141 | CheckDefs, // Check all operands for equality |
1142 | CheckKillDead, // Check all operands including kill / dead markers |
1143 | IgnoreDefs, // Ignore all definitions |
1144 | IgnoreVRegDefs // Ignore virtual register definitions |
1145 | }; |
1146 | |
1147 | /// Return true if this instruction is identical to \p Other. |
1148 | /// Two instructions are identical if they have the same opcode and all their |
1149 | /// operands are identical (with respect to MachineOperand::isIdenticalTo()). |
1150 | /// Note that this means liveness related flags (dead, undef, kill) do not |
1151 | /// affect the notion of identical. |
1152 | bool isIdenticalTo(const MachineInstr &Other, |
1153 | MICheckType Check = CheckDefs) const; |
1154 | |
1155 | /// Unlink 'this' from the containing basic block, and return it without |
1156 | /// deleting it. |
1157 | /// |
1158 | /// This function can not be used on bundled instructions, use |
1159 | /// removeFromBundle() to remove individual instructions from a bundle. |
1160 | MachineInstr *removeFromParent(); |
1161 | |
1162 | /// Unlink this instruction from its basic block and return it without |
1163 | /// deleting it. |
1164 | /// |
1165 | /// If the instruction is part of a bundle, the other instructions in the |
1166 | /// bundle remain bundled. |
1167 | MachineInstr *removeFromBundle(); |
1168 | |
1169 | /// Unlink 'this' from the containing basic block and delete it. |
1170 | /// |
1171 | /// If this instruction is the header of a bundle, the whole bundle is erased. |
1172 | /// This function can not be used for instructions inside a bundle, use |
1173 | /// eraseFromBundle() to erase individual bundled instructions. |
1174 | void eraseFromParent(); |
1175 | |
1176 | /// Unlink 'this' from the containing basic block and delete it. |
1177 | /// |
1178 | /// For all definitions mark their uses in DBG_VALUE nodes |
1179 | /// as undefined. Otherwise like eraseFromParent(). |
1180 | void eraseFromParentAndMarkDBGValuesForRemoval(); |
1181 | |
1182 | /// Unlink 'this' form its basic block and delete it. |
1183 | /// |
1184 | /// If the instruction is part of a bundle, the other instructions in the |
1185 | /// bundle remain bundled. |
1186 | void eraseFromBundle(); |
1187 | |
1188 | bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; } |
1189 | bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; } |
1190 | bool isAnnotationLabel() const { |
1191 | return getOpcode() == TargetOpcode::ANNOTATION_LABEL; |
1192 | } |
1193 | |
1194 | /// Returns true if the MachineInstr represents a label. |
1195 | bool isLabel() const { |
1196 | return isEHLabel() || isGCLabel() || isAnnotationLabel(); |
1197 | } |
1198 | |
1199 | bool isCFIInstruction() const { |
1200 | return getOpcode() == TargetOpcode::CFI_INSTRUCTION; |
1201 | } |
1202 | |
1203 | bool isPseudoProbe() const { |
1204 | return getOpcode() == TargetOpcode::PSEUDO_PROBE; |
1205 | } |
1206 | |
1207 | // True if the instruction represents a position in the function. |
1208 | bool isPosition() const { return isLabel() || isCFIInstruction(); } |
1209 | |
1210 | bool isNonListDebugValue() const { |
1211 | return getOpcode() == TargetOpcode::DBG_VALUE; |
1212 | } |
1213 | bool isDebugValueList() const { |
1214 | return getOpcode() == TargetOpcode::DBG_VALUE_LIST; |
1215 | } |
1216 | bool isDebugValue() const { |
1217 | return isNonListDebugValue() || isDebugValueList(); |
1218 | } |
1219 | bool isDebugLabel() const { return getOpcode() == TargetOpcode::DBG_LABEL; } |
1220 | bool isDebugRef() const { return getOpcode() == TargetOpcode::DBG_INSTR_REF; } |
1221 | bool isDebugPHI() const { return getOpcode() == TargetOpcode::DBG_PHI; } |
1222 | bool isDebugInstr() const { |
1223 | return isDebugValue() || isDebugLabel() || isDebugRef() || isDebugPHI(); |
1224 | } |
1225 | bool isDebugOrPseudoInstr() const { |
1226 | return isDebugInstr() || isPseudoProbe(); |
1227 | } |
1228 | |
1229 | bool isDebugOffsetImm() const { |
1230 | return isNonListDebugValue() && getDebugOffset().isImm(); |
1231 | } |
1232 | |
1233 | /// A DBG_VALUE is indirect iff the location operand is a register and |
1234 | /// the offset operand is an immediate. |
1235 | bool isIndirectDebugValue() const { |
1236 | return isDebugOffsetImm() && getDebugOperand(0).isReg(); |
1237 | } |
1238 | |
1239 | /// A DBG_VALUE is an entry value iff its debug expression contains the |
1240 | /// DW_OP_LLVM_entry_value operation. |
1241 | bool isDebugEntryValue() const; |
1242 | |
1243 | /// Return true if the instruction is a debug value which describes a part of |
1244 | /// a variable as unavailable. |
1245 | bool isUndefDebugValue() const { |
1246 | if (!isDebugValue()) |
1247 | return false; |
1248 | // If any $noreg locations are given, this DV is undef. |
1249 | for (const MachineOperand &Op : debug_operands()) |
1250 | if (Op.isReg() && !Op.getReg().isValid()) |
1251 | return true; |
1252 | return false; |
1253 | } |
1254 | |
1255 | bool isPHI() const { |
1256 | return getOpcode() == TargetOpcode::PHI || |
1257 | getOpcode() == TargetOpcode::G_PHI; |
1258 | } |
1259 | bool isKill() const { return getOpcode() == TargetOpcode::KILL; } |
1260 | bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; } |
1261 | bool isInlineAsm() const { |
1262 | return getOpcode() == TargetOpcode::INLINEASM || |
1263 | getOpcode() == TargetOpcode::INLINEASM_BR; |
1264 | } |
1265 | |
1266 | /// FIXME: Seems like a layering violation that the AsmDialect, which is X86 |
1267 | /// specific, be attached to a generic MachineInstr. |
1268 | bool isMSInlineAsm() const { |
1269 | return isInlineAsm() && getInlineAsmDialect() == InlineAsm::AD_Intel; |
1270 | } |
1271 | |
1272 | bool isStackAligningInlineAsm() const; |
1273 | InlineAsm::AsmDialect getInlineAsmDialect() const; |
1274 | |
1275 | bool isInsertSubreg() const { |
1276 | return getOpcode() == TargetOpcode::INSERT_SUBREG; |
1277 | } |
1278 | |
1279 | bool isSubregToReg() const { |
1280 | return getOpcode() == TargetOpcode::SUBREG_TO_REG; |
1281 | } |
1282 | |
1283 | bool isRegSequence() const { |
1284 | return getOpcode() == TargetOpcode::REG_SEQUENCE; |
1285 | } |
1286 | |
1287 | bool isBundle() const { |
1288 | return getOpcode() == TargetOpcode::BUNDLE; |
1289 | } |
1290 | |
1291 | bool isCopy() const { |
1292 | return getOpcode() == TargetOpcode::COPY; |
1293 | } |
1294 | |
1295 | bool isFullCopy() const { |
1296 | return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg(); |
1297 | } |
1298 | |
1299 | bool isExtractSubreg() const { |
1300 | return getOpcode() == TargetOpcode::EXTRACT_SUBREG; |
1301 | } |
1302 | |
1303 | /// Return true if the instruction behaves like a copy. |
1304 | /// This does not include native copy instructions. |
1305 | bool isCopyLike() const { |
1306 | return isCopy() || isSubregToReg(); |
1307 | } |
1308 | |
1309 | /// Return true is the instruction is an identity copy. |
1310 | bool isIdentityCopy() const { |
1311 | return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() && |
1312 | getOperand(0).getSubReg() == getOperand(1).getSubReg(); |
1313 | } |
1314 | |
1315 | /// Return true if this instruction doesn't produce any output in the form of |
1316 | /// executable instructions. |
1317 | bool isMetaInstruction() const { |
1318 | switch (getOpcode()) { |
1319 | default: |
1320 | return false; |
1321 | case TargetOpcode::IMPLICIT_DEF: |
1322 | case TargetOpcode::KILL: |
1323 | case TargetOpcode::CFI_INSTRUCTION: |
1324 | case TargetOpcode::EH_LABEL: |
1325 | case TargetOpcode::GC_LABEL: |
1326 | case TargetOpcode::DBG_VALUE: |
1327 | case TargetOpcode::DBG_VALUE_LIST: |
1328 | case TargetOpcode::DBG_INSTR_REF: |
1329 | case TargetOpcode::DBG_PHI: |
1330 | case TargetOpcode::DBG_LABEL: |
1331 | case TargetOpcode::LIFETIME_START: |
1332 | case TargetOpcode::LIFETIME_END: |
1333 | case TargetOpcode::PSEUDO_PROBE: |
1334 | return true; |
1335 | } |
1336 | } |
1337 | |
1338 | /// Return true if this is a transient instruction that is either very likely |
1339 | /// to be eliminated during register allocation (such as copy-like |
1340 | /// instructions), or if this instruction doesn't have an execution-time cost. |
1341 | bool isTransient() const { |
1342 | switch (getOpcode()) { |
1343 | default: |
1344 | return isMetaInstruction(); |
1345 | // Copy-like instructions are usually eliminated during register allocation. |
1346 | case TargetOpcode::PHI: |
1347 | case TargetOpcode::G_PHI: |
1348 | case TargetOpcode::COPY: |
1349 | case TargetOpcode::INSERT_SUBREG: |
1350 | case TargetOpcode::SUBREG_TO_REG: |
1351 | case TargetOpcode::REG_SEQUENCE: |
1352 | return true; |
1353 | } |
1354 | } |
1355 | |
1356 | /// Return the number of instructions inside the MI bundle, excluding the |
1357 | /// bundle header. |
1358 | /// |
1359 | /// This is the number of instructions that MachineBasicBlock::iterator |
1360 | /// skips, 0 for unbundled instructions. |
1361 | unsigned getBundleSize() const; |
1362 | |
1363 | /// Return true if the MachineInstr reads the specified register. |
1364 | /// If TargetRegisterInfo is passed, then it also checks if there |
1365 | /// is a read of a super-register. |
1366 | /// This does not count partial redefines of virtual registers as reads: |
1367 | /// %reg1024:6 = OP. |
1368 | bool readsRegister(Register Reg, |
1369 | const TargetRegisterInfo *TRI = nullptr) const { |
1370 | return findRegisterUseOperandIdx(Reg, false, TRI) != -1; |
1371 | } |
1372 | |
1373 | /// Return true if the MachineInstr reads the specified virtual register. |
1374 | /// Take into account that a partial define is a |
1375 | /// read-modify-write operation. |
1376 | bool readsVirtualRegister(Register Reg) const { |
1377 | return readsWritesVirtualRegister(Reg).first; |
1378 | } |
1379 | |
1380 | /// Return a pair of bools (reads, writes) indicating if this instruction |
1381 | /// reads or writes Reg. This also considers partial defines. |
1382 | /// If Ops is not null, all operand indices for Reg are added. |
1383 | std::pair<bool,bool> readsWritesVirtualRegister(Register Reg, |
1384 | SmallVectorImpl<unsigned> *Ops = nullptr) const; |
1385 | |
1386 | /// Return true if the MachineInstr kills the specified register. |
1387 | /// If TargetRegisterInfo is passed, then it also checks if there is |
1388 | /// a kill of a super-register. |
1389 | bool killsRegister(Register Reg, |
1390 | const TargetRegisterInfo *TRI = nullptr) const { |
1391 | return findRegisterUseOperandIdx(Reg, true, TRI) != -1; |
1392 | } |
1393 | |
1394 | /// Return true if the MachineInstr fully defines the specified register. |
1395 | /// If TargetRegisterInfo is passed, then it also checks |
1396 | /// if there is a def of a super-register. |
1397 | /// NOTE: It's ignoring subreg indices on virtual registers. |
1398 | bool definesRegister(Register Reg, |
1399 | const TargetRegisterInfo *TRI = nullptr) const { |
1400 | return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; |
1401 | } |
1402 | |
1403 | /// Return true if the MachineInstr modifies (fully define or partially |
1404 | /// define) the specified register. |
1405 | /// NOTE: It's ignoring subreg indices on virtual registers. |
1406 | bool modifiesRegister(Register Reg, |
1407 | const TargetRegisterInfo *TRI = nullptr) const { |
1408 | return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; |
1409 | } |
1410 | |
1411 | /// Returns true if the register is dead in this machine instruction. |
1412 | /// If TargetRegisterInfo is passed, then it also checks |
1413 | /// if there is a dead def of a super-register. |
1414 | bool registerDefIsDead(Register Reg, |
1415 | const TargetRegisterInfo *TRI = nullptr) const { |
1416 | return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1; |
1417 | } |
1418 | |
1419 | /// Returns true if the MachineInstr has an implicit-use operand of exactly |
1420 | /// the given register (not considering sub/super-registers). |
1421 | bool hasRegisterImplicitUseOperand(Register Reg) const; |
1422 | |
1423 | /// Returns the operand index that is a use of the specific register or -1 |
1424 | /// if it is not found. It further tightens the search criteria to a use |
1425 | /// that kills the register if isKill is true. |
1426 | int findRegisterUseOperandIdx(Register Reg, bool isKill = false, |
1427 | const TargetRegisterInfo *TRI = nullptr) const; |
1428 | |
1429 | /// Wrapper for findRegisterUseOperandIdx, it returns |
1430 | /// a pointer to the MachineOperand rather than an index. |
1431 | MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false, |
1432 | const TargetRegisterInfo *TRI = nullptr) { |
1433 | int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); |
1434 | return (Idx == -1) ? nullptr : &getOperand(Idx); |
1435 | } |
1436 | |
1437 | const MachineOperand *findRegisterUseOperand( |
1438 | Register Reg, bool isKill = false, |
1439 | const TargetRegisterInfo *TRI = nullptr) const { |
1440 | return const_cast<MachineInstr *>(this)-> |
1441 | findRegisterUseOperand(Reg, isKill, TRI); |
1442 | } |
1443 | |
1444 | /// Returns the operand index that is a def of the specified register or |
1445 | /// -1 if it is not found. If isDead is true, defs that are not dead are |
1446 | /// skipped. If Overlap is true, then it also looks for defs that merely |
1447 | /// overlap the specified register. If TargetRegisterInfo is non-null, |
1448 | /// then it also checks if there is a def of a super-register. |
1449 | /// This may also return a register mask operand when Overlap is true. |
1450 | int findRegisterDefOperandIdx(Register Reg, |
1451 | bool isDead = false, bool Overlap = false, |
1452 | const TargetRegisterInfo *TRI = nullptr) const; |
1453 | |
1454 | /// Wrapper for findRegisterDefOperandIdx, it returns |
1455 | /// a pointer to the MachineOperand rather than an index. |
1456 | MachineOperand * |
1457 | findRegisterDefOperand(Register Reg, bool isDead = false, |
1458 | bool Overlap = false, |
1459 | const TargetRegisterInfo *TRI = nullptr) { |
1460 | int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI); |
1461 | return (Idx == -1) ? nullptr : &getOperand(Idx); |
1462 | } |
1463 | |
1464 | const MachineOperand * |
1465 | findRegisterDefOperand(Register Reg, bool isDead = false, |
1466 | bool Overlap = false, |
1467 | const TargetRegisterInfo *TRI = nullptr) const { |
1468 | return const_cast<MachineInstr *>(this)->findRegisterDefOperand( |
1469 | Reg, isDead, Overlap, TRI); |
1470 | } |
1471 | |
1472 | /// Find the index of the first operand in the |
1473 | /// operand list that is used to represent the predicate. It returns -1 if |
1474 | /// none is found. |
1475 | int findFirstPredOperandIdx() const; |
1476 | |
1477 | /// Find the index of the flag word operand that |
1478 | /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if |
1479 | /// getOperand(OpIdx) does not belong to an inline asm operand group. |
1480 | /// |
1481 | /// If GroupNo is not NULL, it will receive the number of the operand group |
1482 | /// containing OpIdx. |
1483 | int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const; |
1484 | |
1485 | /// Compute the static register class constraint for operand OpIdx. |
1486 | /// For normal instructions, this is derived from the MCInstrDesc. |
1487 | /// For inline assembly it is derived from the flag words. |
1488 | /// |
1489 | /// Returns NULL if the static register class constraint cannot be |
1490 | /// determined. |
1491 | const TargetRegisterClass* |
1492 | getRegClassConstraint(unsigned OpIdx, |
1493 | const TargetInstrInfo *TII, |
1494 | const TargetRegisterInfo *TRI) const; |
1495 | |
1496 | /// Applies the constraints (def/use) implied by this MI on \p Reg to |
1497 | /// the given \p CurRC. |
1498 | /// If \p ExploreBundle is set and MI is part of a bundle, all the |
1499 | /// instructions inside the bundle will be taken into account. In other words, |
1500 | /// this method accumulates all the constraints of the operand of this MI and |
1501 | /// the related bundle if MI is a bundle or inside a bundle. |
1502 | /// |
1503 | /// Returns the register class that satisfies both \p CurRC and the |
1504 | /// constraints set by MI. Returns NULL if such a register class does not |
1505 | /// exist. |
1506 | /// |
1507 | /// \pre CurRC must not be NULL. |
1508 | const TargetRegisterClass *getRegClassConstraintEffectForVReg( |
1509 | Register Reg, const TargetRegisterClass *CurRC, |
1510 | const TargetInstrInfo *TII, const TargetRegisterInfo *TRI, |
1511 | bool ExploreBundle = false) const; |
1512 | |
1513 | /// Applies the constraints (def/use) implied by the \p OpIdx operand |
1514 | /// to the given \p CurRC. |
1515 | /// |
1516 | /// Returns the register class that satisfies both \p CurRC and the |
1517 | /// constraints set by \p OpIdx MI. Returns NULL if such a register class |
1518 | /// does not exist. |
1519 | /// |
1520 | /// \pre CurRC must not be NULL. |
1521 | /// \pre The operand at \p OpIdx must be a register. |
1522 | const TargetRegisterClass * |
1523 | getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC, |
1524 | const TargetInstrInfo *TII, |
1525 | const TargetRegisterInfo *TRI) const; |
1526 | |
1527 | /// Add a tie between the register operands at DefIdx and UseIdx. |
1528 | /// The tie will cause the register allocator to ensure that the two |
1529 | /// operands are assigned the same physical register. |
1530 | /// |
1531 | /// Tied operands are managed automatically for explicit operands in the |
1532 | /// MCInstrDesc. This method is for exceptional cases like inline asm. |
1533 | void tieOperands(unsigned DefIdx, unsigned UseIdx); |
1534 | |
1535 | /// Given the index of a tied register operand, find the |
1536 | /// operand it is tied to. Defs are tied to uses and vice versa. Returns the |
1537 | /// index of the tied operand which must exist. |
1538 | unsigned findTiedOperandIdx(unsigned OpIdx) const; |
1539 | |
1540 | /// Given the index of a register def operand, |
1541 | /// check if the register def is tied to a source operand, due to either |
1542 | /// two-address elimination or inline assembly constraints. Returns the |
1543 | /// first tied use operand index by reference if UseOpIdx is not null. |
1544 | bool isRegTiedToUseOperand(unsigned DefOpIdx, |
1545 | unsigned *UseOpIdx = nullptr) const { |
1546 | const MachineOperand &MO = getOperand(DefOpIdx); |
1547 | if (!MO.isReg() || !MO.isDef() || !MO.isTied()) |
1548 | return false; |
1549 | if (UseOpIdx) |
1550 | *UseOpIdx = findTiedOperandIdx(DefOpIdx); |
1551 | return true; |
1552 | } |
1553 | |
1554 | /// Return true if the use operand of the specified index is tied to a def |
1555 | /// operand. It also returns the def operand index by reference if DefOpIdx |
1556 | /// is not null. |
1557 | bool isRegTiedToDefOperand(unsigned UseOpIdx, |
1558 | unsigned *DefOpIdx = nullptr) const { |
1559 | const MachineOperand &MO = getOperand(UseOpIdx); |
1560 | if (!MO.isReg() || !MO.isUse() || !MO.isTied()) |
1561 | return false; |
1562 | if (DefOpIdx) |
1563 | *DefOpIdx = findTiedOperandIdx(UseOpIdx); |
1564 | return true; |
1565 | } |
1566 | |
1567 | /// Clears kill flags on all operands. |
1568 | void clearKillInfo(); |
1569 | |
1570 | /// Replace all occurrences of FromReg with ToReg:SubIdx, |
1571 | /// properly composing subreg indices where necessary. |
1572 | void substituteRegister(Register FromReg, Register ToReg, unsigned SubIdx, |
1573 | const TargetRegisterInfo &RegInfo); |
1574 | |
1575 | /// We have determined MI kills a register. Look for the |
1576 | /// operand that uses it and mark it as IsKill. If AddIfNotFound is true, |
1577 | /// add a implicit operand if it's not found. Returns true if the operand |
1578 | /// exists / is added. |
1579 | bool addRegisterKilled(Register IncomingReg, |
1580 | const TargetRegisterInfo *RegInfo, |
1581 | bool AddIfNotFound = false); |
1582 | |
1583 | /// Clear all kill flags affecting Reg. If RegInfo is provided, this includes |
1584 | /// all aliasing registers. |
1585 | void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo); |
1586 | |
1587 | /// We have determined MI defined a register without a use. |
1588 | /// Look for the operand that defines it and mark it as IsDead. If |
1589 | /// AddIfNotFound is true, add a implicit operand if it's not found. Returns |
1590 | /// true if the operand exists / is added. |
1591 | bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo, |
1592 | bool AddIfNotFound = false); |
1593 | |
1594 | /// Clear all dead flags on operands defining register @p Reg. |
1595 | void clearRegisterDeads(Register Reg); |
1596 | |
1597 | /// Mark all subregister defs of register @p Reg with the undef flag. |
1598 | /// This function is used when we determined to have a subregister def in an |
1599 | /// otherwise undefined super register. |
1600 | void setRegisterDefReadUndef(Register Reg, bool IsUndef = true); |
1601 | |
1602 | /// We have determined MI defines a register. Make sure there is an operand |
1603 | /// defining Reg. |
1604 | void addRegisterDefined(Register Reg, |
1605 | const TargetRegisterInfo *RegInfo = nullptr); |
1606 | |
1607 | /// Mark every physreg used by this instruction as |
1608 | /// dead except those in the UsedRegs list. |
1609 | /// |
1610 | /// On instructions with register mask operands, also add implicit-def |
1611 | /// operands for all registers in UsedRegs. |
1612 | void setPhysRegsDeadExcept(ArrayRef<Register> UsedRegs, |
1613 | const TargetRegisterInfo &TRI); |
1614 | |
1615 | /// Return true if it is safe to move this instruction. If |
1616 | /// SawStore is set to true, it means that there is a store (or call) between |
1617 | /// the instruction's location and its intended destination. |
1618 | bool isSafeToMove(AAResults *AA, bool &SawStore) const; |
1619 | |
1620 | /// Returns true if this instruction's memory access aliases the memory |
1621 | /// access of Other. |
1622 | // |
1623 | /// Assumes any physical registers used to compute addresses |
1624 | /// have the same value for both instructions. Returns false if neither |
1625 | /// instruction writes to memory. |
1626 | /// |
1627 | /// @param AA Optional alias analysis, used to compare memory operands. |
1628 | /// @param Other MachineInstr to check aliasing against. |
1629 | /// @param UseTBAA Whether to pass TBAA information to alias analysis. |
1630 | bool mayAlias(AAResults *AA, const MachineInstr &Other, bool UseTBAA) const; |
1631 | |
1632 | /// Return true if this instruction may have an ordered |
1633 | /// or volatile memory reference, or if the information describing the memory |
1634 | /// reference is not available. Return false if it is known to have no |
1635 | /// ordered or volatile memory references. |
1636 | bool hasOrderedMemoryRef() const; |
1637 | |
1638 | /// Return true if this load instruction never traps and points to a memory |
1639 | /// location whose value doesn't change during the execution of this function. |
1640 | /// |
1641 | /// Examples include loading a value from the constant pool or from the |
1642 | /// argument area of a function (if it does not change). If the instruction |
1643 | /// does multiple loads, this returns true only if all of the loads are |
1644 | /// dereferenceable and invariant. |
1645 | bool isDereferenceableInvariantLoad(AAResults *AA) const; |
1646 | |
1647 | /// If the specified instruction is a PHI that always merges together the |
1648 | /// same virtual register, return the register, otherwise return 0. |
1649 | unsigned isConstantValuePHI() const; |
1650 | |
1651 | /// Return true if this instruction has side effects that are not modeled |
1652 | /// by mayLoad / mayStore, etc. |
1653 | /// For all instructions, the property is encoded in MCInstrDesc::Flags |
1654 | /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is |
1655 | /// INLINEASM instruction, in which case the side effect property is encoded |
1656 | /// in one of its operands (see InlineAsm::Extra_HasSideEffect). |
1657 | /// |
1658 | bool hasUnmodeledSideEffects() const; |
1659 | |
1660 | /// Returns true if it is illegal to fold a load across this instruction. |
1661 | bool isLoadFoldBarrier() const; |
1662 | |
1663 | /// Return true if all the defs of this instruction are dead. |
1664 | bool allDefsAreDead() const; |
1665 | |
1666 | /// Return a valid size if the instruction is a spill instruction. |
1667 | Optional<unsigned> getSpillSize(const TargetInstrInfo *TII) const; |
1668 | |
1669 | /// Return a valid size if the instruction is a folded spill instruction. |
1670 | Optional<unsigned> getFoldedSpillSize(const TargetInstrInfo *TII) const; |
1671 | |
1672 | /// Return a valid size if the instruction is a restore instruction. |
1673 | Optional<unsigned> getRestoreSize(const TargetInstrInfo *TII) const; |
1674 | |
1675 | /// Return a valid size if the instruction is a folded restore instruction. |
1676 | Optional<unsigned> |
1677 | getFoldedRestoreSize(const TargetInstrInfo *TII) const; |
1678 | |
1679 | /// Copy implicit register operands from specified |
1680 | /// instruction to this instruction. |
1681 | void copyImplicitOps(MachineFunction &MF, const MachineInstr &MI); |
1682 | |
1683 | /// Debugging support |
1684 | /// @{ |
1685 | /// Determine the generic type to be printed (if needed) on uses and defs. |
1686 | LLT getTypeToPrint(unsigned OpIdx, SmallBitVector &PrintedTypes, |
1687 | const MachineRegisterInfo &MRI) const; |
1688 | |
1689 | /// Return true when an instruction has tied register that can't be determined |
1690 | /// by the instruction's descriptor. This is useful for MIR printing, to |
1691 | /// determine whether we need to print the ties or not. |
1692 | bool hasComplexRegisterTies() const; |
1693 | |
1694 | /// Print this MI to \p OS. |
1695 | /// Don't print information that can be inferred from other instructions if |
1696 | /// \p IsStandalone is false. It is usually true when only a fragment of the |
1697 | /// function is printed. |
1698 | /// Only print the defs and the opcode if \p SkipOpers is true. |
1699 | /// Otherwise, also print operands if \p SkipDebugLoc is true. |
1700 | /// Otherwise, also print the debug loc, with a terminating newline. |
1701 | /// \p TII is used to print the opcode name. If it's not present, but the |
1702 | /// MI is in a function, the opcode will be printed using the function's TII. |
1703 | void print(raw_ostream &OS, bool IsStandalone = true, bool SkipOpers = false, |
1704 | bool SkipDebugLoc = false, bool AddNewLine = true, |
1705 | const TargetInstrInfo *TII = nullptr) const; |
1706 | void print(raw_ostream &OS, ModuleSlotTracker &MST, bool IsStandalone = true, |
1707 | bool SkipOpers = false, bool SkipDebugLoc = false, |
1708 | bool AddNewLine = true, |
1709 | const TargetInstrInfo *TII = nullptr) const; |
1710 | void dump() const; |
1711 | /// Print on dbgs() the current instruction and the instructions defining its |
1712 | /// operands and so on until we reach \p MaxDepth. |
1713 | void dumpr(const MachineRegisterInfo &MRI, |
1714 | unsigned MaxDepth = UINT_MAX(2147483647 *2U +1U)) const; |
1715 | /// @} |
1716 | |
1717 | //===--------------------------------------------------------------------===// |
1718 | // Accessors used to build up machine instructions. |
1719 | |
1720 | /// Add the specified operand to the instruction. If it is an implicit |
1721 | /// operand, it is added to the end of the operand list. If it is an |
1722 | /// explicit operand it is added at the end of the explicit operand list |
1723 | /// (before the first implicit operand). |
1724 | /// |
1725 | /// MF must be the machine function that was used to allocate this |
1726 | /// instruction. |
1727 | /// |
1728 | /// MachineInstrBuilder provides a more convenient interface for creating |
1729 | /// instructions and adding operands. |
1730 | void addOperand(MachineFunction &MF, const MachineOperand &Op); |
1731 | |
1732 | /// Add an operand without providing an MF reference. This only works for |
1733 | /// instructions that are inserted in a basic block. |
1734 | /// |
1735 | /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be |
1736 | /// preferred. |
1737 | void addOperand(const MachineOperand &Op); |
1738 | |
1739 | /// Replace the instruction descriptor (thus opcode) of |
1740 | /// the current instruction with a new one. |
1741 | void setDesc(const MCInstrDesc &tid) { MCID = &tid; } |
1742 | |
1743 | /// Replace current source information with new such. |
1744 | /// Avoid using this, the constructor argument is preferable. |
1745 | void setDebugLoc(DebugLoc dl) { |
1746 | debugLoc = std::move(dl); |
1747 | assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor")((void)0); |
1748 | } |
1749 | |
1750 | /// Erase an operand from an instruction, leaving it with one |
1751 | /// fewer operand than it started with. |
1752 | void RemoveOperand(unsigned OpNo); |
1753 | |
1754 | /// Clear this MachineInstr's memory reference descriptor list. This resets |
1755 | /// the memrefs to their most conservative state. This should be used only |
1756 | /// as a last resort since it greatly pessimizes our knowledge of the memory |
1757 | /// access performed by the instruction. |
1758 | void dropMemRefs(MachineFunction &MF); |
1759 | |
1760 | /// Assign this MachineInstr's memory reference descriptor list. |
1761 | /// |
1762 | /// Unlike other methods, this *will* allocate them into a new array |
1763 | /// associated with the provided `MachineFunction`. |
1764 | void setMemRefs(MachineFunction &MF, ArrayRef<MachineMemOperand *> MemRefs); |
1765 | |
1766 | /// Add a MachineMemOperand to the machine instruction. |
1767 | /// This function should be used only occasionally. The setMemRefs function |
1768 | /// is the primary method for setting up a MachineInstr's MemRefs list. |
1769 | void addMemOperand(MachineFunction &MF, MachineMemOperand *MO); |
1770 | |
1771 | /// Clone another MachineInstr's memory reference descriptor list and replace |
1772 | /// ours with it. |
1773 | /// |
1774 | /// Note that `*this` may be the incoming MI! |
1775 | /// |
1776 | /// Prefer this API whenever possible as it can avoid allocations in common |
1777 | /// cases. |
1778 | void cloneMemRefs(MachineFunction &MF, const MachineInstr &MI); |
1779 | |
1780 | /// Clone the merge of multiple MachineInstrs' memory reference descriptors |
1781 | /// list and replace ours with it. |
1782 | /// |
1783 | /// Note that `*this` may be one of the incoming MIs! |
1784 | /// |
1785 | /// Prefer this API whenever possible as it can avoid allocations in common |
1786 | /// cases. |
1787 | void cloneMergedMemRefs(MachineFunction &MF, |
1788 | ArrayRef<const MachineInstr *> MIs); |
1789 | |
1790 | /// Set a symbol that will be emitted just prior to the instruction itself. |
1791 | /// |
1792 | /// Setting this to a null pointer will remove any such symbol. |
1793 | /// |
1794 | /// FIXME: This is not fully implemented yet. |
1795 | void setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol); |
1796 | |
1797 | /// Set a symbol that will be emitted just after the instruction itself. |
1798 | /// |
1799 | /// Setting this to a null pointer will remove any such symbol. |
1800 | /// |
1801 | /// FIXME: This is not fully implemented yet. |
1802 | void setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol); |
1803 | |
1804 | /// Clone another MachineInstr's pre- and post- instruction symbols and |
1805 | /// replace ours with it. |
1806 | void cloneInstrSymbols(MachineFunction &MF, const MachineInstr &MI); |
1807 | |
1808 | /// Set a marker on instructions that denotes where we should create and emit |
1809 | /// heap alloc site labels. This waits until after instruction selection and |
1810 | /// optimizations to create the label, so it should still work if the |
1811 | /// instruction is removed or duplicated. |
1812 | void setHeapAllocMarker(MachineFunction &MF, MDNode *MD); |
1813 | |
1814 | /// Return the MIFlags which represent both MachineInstrs. This |
1815 | /// should be used when merging two MachineInstrs into one. This routine does |
1816 | /// not modify the MIFlags of this MachineInstr. |
1817 | uint16_t mergeFlagsWith(const MachineInstr& Other) const; |
1818 | |
1819 | static uint16_t copyFlagsFromInstruction(const Instruction &I); |
1820 | |
1821 | /// Copy all flags to MachineInst MIFlags |
1822 | void copyIRFlags(const Instruction &I); |
1823 | |
1824 | /// Break any tie involving OpIdx. |
1825 | void untieRegOperand(unsigned OpIdx) { |
1826 | MachineOperand &MO = getOperand(OpIdx); |
1827 | if (MO.isReg() && MO.isTied()) { |
1828 | getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0; |
1829 | MO.TiedTo = 0; |
1830 | } |
1831 | } |
1832 | |
1833 | /// Add all implicit def and use operands to this instruction. |
1834 | void addImplicitDefUseOperands(MachineFunction &MF); |
1835 | |
1836 | /// Scan instructions immediately following MI and collect any matching |
1837 | /// DBG_VALUEs. |
1838 | void collectDebugValues(SmallVectorImpl<MachineInstr *> &DbgValues); |
1839 | |
1840 | /// Find all DBG_VALUEs that point to the register def in this instruction |
1841 | /// and point them to \p Reg instead. |
1842 | void changeDebugValuesDefReg(Register Reg); |
1843 | |
1844 | /// Returns the Intrinsic::ID for this instruction. |
1845 | /// \pre Must have an intrinsic ID operand. |
1846 | unsigned getIntrinsicID() const { |
1847 | return getOperand(getNumExplicitDefs()).getIntrinsicID(); |
1848 | } |
1849 | |
1850 | /// Sets all register debug operands in this debug value instruction to be |
1851 | /// undef. |
1852 | void setDebugValueUndef() { |
1853 | assert(isDebugValue() && "Must be a debug value instruction.")((void)0); |
1854 | for (MachineOperand &MO : debug_operands()) { |
1855 | if (MO.isReg()) { |
1856 | MO.setReg(0); |
1857 | MO.setSubReg(0); |
1858 | } |
1859 | } |
1860 | } |
1861 | |
1862 | PseudoProbeAttributes getPseudoProbeAttribute() const { |
1863 | assert(isPseudoProbe() && "Must be a pseudo probe instruction")((void)0); |
1864 | return (PseudoProbeAttributes)getOperand(3).getImm(); |
1865 | } |
1866 | |
1867 | void addPseudoProbeAttribute(PseudoProbeAttributes Attr) { |
1868 | assert(isPseudoProbe() && "Must be a pseudo probe instruction")((void)0); |
1869 | MachineOperand &AttrOperand = getOperand(3); |
1870 | AttrOperand.setImm(AttrOperand.getImm() | (uint32_t)Attr); |
1871 | } |
1872 | |
1873 | private: |
1874 | /// If this instruction is embedded into a MachineFunction, return the |
1875 | /// MachineRegisterInfo object for the current function, otherwise |
1876 | /// return null. |
1877 | MachineRegisterInfo *getRegInfo(); |
1878 | |
1879 | /// Unlink all of the register operands in this instruction from their |
1880 | /// respective use lists. This requires that the operands already be on their |
1881 | /// use lists. |
1882 | void RemoveRegOperandsFromUseLists(MachineRegisterInfo&); |
1883 | |
1884 | /// Add all of the register operands in this instruction from their |
1885 | /// respective use lists. This requires that the operands not be on their |
1886 | /// use lists yet. |
1887 | void AddRegOperandsToUseLists(MachineRegisterInfo&); |
1888 | |
1889 | /// Slow path for hasProperty when we're dealing with a bundle. |
1890 | bool hasPropertyInBundle(uint64_t Mask, QueryType Type) const; |
1891 | |
1892 | /// Implements the logic of getRegClassConstraintEffectForVReg for the |
1893 | /// this MI and the given operand index \p OpIdx. |
1894 | /// If the related operand does not constrained Reg, this returns CurRC. |
1895 | const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl( |
1896 | unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC, |
1897 | const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const; |
1898 | |
1899 | /// Stores extra instruction information inline or allocates as ExtraInfo |
1900 | /// based on the number of pointers. |
1901 | void setExtraInfo(MachineFunction &MF, ArrayRef<MachineMemOperand *> MMOs, |
1902 | MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol, |
1903 | MDNode *HeapAllocMarker); |
1904 | }; |
1905 | |
1906 | /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the |
1907 | /// instruction rather than by pointer value. |
1908 | /// The hashing and equality testing functions ignore definitions so this is |
1909 | /// useful for CSE, etc. |
1910 | struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> { |
1911 | static inline MachineInstr *getEmptyKey() { |
1912 | return nullptr; |
1913 | } |
1914 | |
1915 | static inline MachineInstr *getTombstoneKey() { |
1916 | return reinterpret_cast<MachineInstr*>(-1); |
1917 | } |
1918 | |
1919 | static unsigned getHashValue(const MachineInstr* const &MI); |
1920 | |
1921 | static bool isEqual(const MachineInstr* const &LHS, |
1922 | const MachineInstr* const &RHS) { |
1923 | if (RHS == getEmptyKey() || RHS == getTombstoneKey() || |
1924 | LHS == getEmptyKey() || LHS == getTombstoneKey()) |
1925 | return LHS == RHS; |
1926 | return LHS->isIdenticalTo(*RHS, MachineInstr::IgnoreVRegDefs); |
1927 | } |
1928 | }; |
1929 | |
1930 | //===----------------------------------------------------------------------===// |
1931 | // Debugging Support |
1932 | |
1933 | inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) { |
1934 | MI.print(OS); |
1935 | return OS; |
1936 | } |
1937 | |
1938 | } // end namespace llvm |
1939 | |
1940 | #endif // LLVM_CODEGEN_MACHINEINSTR_H |
1 | //===- llvm/CodeGen/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | // |
9 | // This file describes the target machine instruction set to the code generator. |
10 | // |
11 | //===----------------------------------------------------------------------===// |
12 | |
13 | #ifndef LLVM_CODEGEN_TARGETINSTRINFO_H |
14 | #define LLVM_CODEGEN_TARGETINSTRINFO_H |
15 | |
16 | #include "llvm/ADT/ArrayRef.h" |
17 | #include "llvm/ADT/DenseMap.h" |
18 | #include "llvm/ADT/DenseMapInfo.h" |
19 | #include "llvm/ADT/None.h" |
20 | #include "llvm/CodeGen/MIRFormatter.h" |
21 | #include "llvm/CodeGen/MachineBasicBlock.h" |
22 | #include "llvm/CodeGen/MachineCombinerPattern.h" |
23 | #include "llvm/CodeGen/MachineFunction.h" |
24 | #include "llvm/CodeGen/MachineInstr.h" |
25 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
26 | #include "llvm/CodeGen/MachineOperand.h" |
27 | #include "llvm/CodeGen/MachineOutliner.h" |
28 | #include "llvm/CodeGen/RegisterClassInfo.h" |
29 | #include "llvm/CodeGen/VirtRegMap.h" |
30 | #include "llvm/MC/MCInstrInfo.h" |
31 | #include "llvm/Support/BranchProbability.h" |
32 | #include "llvm/Support/ErrorHandling.h" |
33 | #include <cassert> |
34 | #include <cstddef> |
35 | #include <cstdint> |
36 | #include <utility> |
37 | #include <vector> |
38 | |
39 | namespace llvm { |
40 | |
41 | class AAResults; |
42 | class DFAPacketizer; |
43 | class InstrItineraryData; |
44 | class LiveIntervals; |
45 | class LiveVariables; |
46 | class MachineLoop; |
47 | class MachineMemOperand; |
48 | class MachineRegisterInfo; |
49 | class MCAsmInfo; |
50 | class MCInst; |
51 | struct MCSchedModel; |
52 | class Module; |
53 | class ScheduleDAG; |
54 | class ScheduleDAGMI; |
55 | class ScheduleHazardRecognizer; |
56 | class SDNode; |
57 | class SelectionDAG; |
58 | class RegScavenger; |
59 | class TargetRegisterClass; |
60 | class TargetRegisterInfo; |
61 | class TargetSchedModel; |
62 | class TargetSubtargetInfo; |
63 | |
64 | template <class T> class SmallVectorImpl; |
65 | |
66 | using ParamLoadedValue = std::pair<MachineOperand, DIExpression*>; |
67 | |
68 | struct DestSourcePair { |
69 | const MachineOperand *Destination; |
70 | const MachineOperand *Source; |
71 | |
72 | DestSourcePair(const MachineOperand &Dest, const MachineOperand &Src) |
73 | : Destination(&Dest), Source(&Src) {} |
74 | }; |
75 | |
76 | /// Used to describe a register and immediate addition. |
77 | struct RegImmPair { |
78 | Register Reg; |
79 | int64_t Imm; |
80 | |
81 | RegImmPair(Register Reg, int64_t Imm) : Reg(Reg), Imm(Imm) {} |
82 | }; |
83 | |
84 | /// Used to describe addressing mode similar to ExtAddrMode in CodeGenPrepare. |
85 | /// It holds the register values, the scale value and the displacement. |
86 | struct ExtAddrMode { |
87 | Register BaseReg; |
88 | Register ScaledReg; |
89 | int64_t Scale; |
90 | int64_t Displacement; |
91 | }; |
92 | |
93 | //--------------------------------------------------------------------------- |
94 | /// |
95 | /// TargetInstrInfo - Interface to description of machine instruction set |
96 | /// |
97 | class TargetInstrInfo : public MCInstrInfo { |
98 | public: |
99 | TargetInstrInfo(unsigned CFSetupOpcode = ~0u, unsigned CFDestroyOpcode = ~0u, |
100 | unsigned CatchRetOpcode = ~0u, unsigned ReturnOpcode = ~0u) |
101 | : CallFrameSetupOpcode(CFSetupOpcode), |
102 | CallFrameDestroyOpcode(CFDestroyOpcode), CatchRetOpcode(CatchRetOpcode), |
103 | ReturnOpcode(ReturnOpcode) {} |
104 | TargetInstrInfo(const TargetInstrInfo &) = delete; |
105 | TargetInstrInfo &operator=(const TargetInstrInfo &) = delete; |
106 | virtual ~TargetInstrInfo(); |
107 | |
108 | static bool isGenericOpcode(unsigned Opc) { |
109 | return Opc <= TargetOpcode::GENERIC_OP_END; |
110 | } |
111 | |
112 | /// Given a machine instruction descriptor, returns the register |
113 | /// class constraint for OpNum, or NULL. |
114 | virtual |
115 | const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum, |
116 | const TargetRegisterInfo *TRI, |
117 | const MachineFunction &MF) const; |
118 | |
119 | /// Return true if the instruction is trivially rematerializable, meaning it |
120 | /// has no side effects and requires no operands that aren't always available. |
121 | /// This means the only allowed uses are constants and unallocatable physical |
122 | /// registers so that the instructions result is independent of the place |
123 | /// in the function. |
124 | bool isTriviallyReMaterializable(const MachineInstr &MI, |
125 | AAResults *AA = nullptr) const { |
126 | return MI.getOpcode() == TargetOpcode::IMPLICIT_DEF || |
127 | (MI.getDesc().isRematerializable() && |
128 | (isReallyTriviallyReMaterializable(MI, AA) || |
129 | isReallyTriviallyReMaterializableGeneric(MI, AA))); |
130 | } |
131 | |
132 | /// Given \p MO is a PhysReg use return if it can be ignored for the purpose |
133 | /// of instruction rematerialization. |
134 | virtual bool isIgnorableUse(const MachineOperand &MO) const { |
135 | return false; |
136 | } |
137 | |
138 | protected: |
139 | /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is |
140 | /// set, this hook lets the target specify whether the instruction is actually |
141 | /// trivially rematerializable, taking into consideration its operands. This |
142 | /// predicate must return false if the instruction has any side effects other |
143 | /// than producing a value, or if it requres any address registers that are |
144 | /// not always available. |
145 | /// Requirements must be check as stated in isTriviallyReMaterializable() . |
146 | virtual bool isReallyTriviallyReMaterializable(const MachineInstr &MI, |
147 | AAResults *AA) const { |
148 | return false; |
149 | } |
150 | |
151 | /// This method commutes the operands of the given machine instruction MI. |
152 | /// The operands to be commuted are specified by their indices OpIdx1 and |
153 | /// OpIdx2. |
154 | /// |
155 | /// If a target has any instructions that are commutable but require |
156 | /// converting to different instructions or making non-trivial changes |
157 | /// to commute them, this method can be overloaded to do that. |
158 | /// The default implementation simply swaps the commutable operands. |
159 | /// |
160 | /// If NewMI is false, MI is modified in place and returned; otherwise, a |
161 | /// new machine instruction is created and returned. |
162 | /// |
163 | /// Do not call this method for a non-commutable instruction. |
164 | /// Even though the instruction is commutable, the method may still |
165 | /// fail to commute the operands, null pointer is returned in such cases. |
166 | virtual MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI, |
167 | unsigned OpIdx1, |
168 | unsigned OpIdx2) const; |
169 | |
170 | /// Assigns the (CommutableOpIdx1, CommutableOpIdx2) pair of commutable |
171 | /// operand indices to (ResultIdx1, ResultIdx2). |
172 | /// One or both input values of the pair: (ResultIdx1, ResultIdx2) may be |
173 | /// predefined to some indices or be undefined (designated by the special |
174 | /// value 'CommuteAnyOperandIndex'). |
175 | /// The predefined result indices cannot be re-defined. |
176 | /// The function returns true iff after the result pair redefinition |
177 | /// the fixed result pair is equal to or equivalent to the source pair of |
178 | /// indices: (CommutableOpIdx1, CommutableOpIdx2). It is assumed here that |
179 | /// the pairs (x,y) and (y,x) are equivalent. |
180 | static bool fixCommutedOpIndices(unsigned &ResultIdx1, unsigned &ResultIdx2, |
181 | unsigned CommutableOpIdx1, |
182 | unsigned CommutableOpIdx2); |
183 | |
184 | private: |
185 | /// For instructions with opcodes for which the M_REMATERIALIZABLE flag is |
186 | /// set and the target hook isReallyTriviallyReMaterializable returns false, |
187 | /// this function does target-independent tests to determine if the |
188 | /// instruction is really trivially rematerializable. |
189 | bool isReallyTriviallyReMaterializableGeneric(const MachineInstr &MI, |
190 | AAResults *AA) const; |
191 | |
192 | public: |
193 | /// These methods return the opcode of the frame setup/destroy instructions |
194 | /// if they exist (-1 otherwise). Some targets use pseudo instructions in |
195 | /// order to abstract away the difference between operating with a frame |
196 | /// pointer and operating without, through the use of these two instructions. |
197 | /// |
198 | unsigned getCallFrameSetupOpcode() const { return CallFrameSetupOpcode; } |
199 | unsigned getCallFrameDestroyOpcode() const { return CallFrameDestroyOpcode; } |
200 | |
201 | /// Returns true if the argument is a frame pseudo instruction. |
202 | bool isFrameInstr(const MachineInstr &I) const { |
203 | return I.getOpcode() == getCallFrameSetupOpcode() || |
204 | I.getOpcode() == getCallFrameDestroyOpcode(); |
205 | } |
206 | |
207 | /// Returns true if the argument is a frame setup pseudo instruction. |
208 | bool isFrameSetup(const MachineInstr &I) const { |
209 | return I.getOpcode() == getCallFrameSetupOpcode(); |
210 | } |
211 | |
212 | /// Returns size of the frame associated with the given frame instruction. |
213 | /// For frame setup instruction this is frame that is set up space set up |
214 | /// after the instruction. For frame destroy instruction this is the frame |
215 | /// freed by the caller. |
216 | /// Note, in some cases a call frame (or a part of it) may be prepared prior |
217 | /// to the frame setup instruction. It occurs in the calls that involve |
218 | /// inalloca arguments. This function reports only the size of the frame part |
219 | /// that is set up between the frame setup and destroy pseudo instructions. |
220 | int64_t getFrameSize(const MachineInstr &I) const { |
221 | assert(isFrameInstr(I) && "Not a frame instruction")((void)0); |
222 | assert(I.getOperand(0).getImm() >= 0)((void)0); |
223 | return I.getOperand(0).getImm(); |
224 | } |
225 | |
226 | /// Returns the total frame size, which is made up of the space set up inside |
227 | /// the pair of frame start-stop instructions and the space that is set up |
228 | /// prior to the pair. |
229 | int64_t getFrameTotalSize(const MachineInstr &I) const { |
230 | if (isFrameSetup(I)) { |
231 | assert(I.getOperand(1).getImm() >= 0 &&((void)0) |
232 | "Frame size must not be negative")((void)0); |
233 | return getFrameSize(I) + I.getOperand(1).getImm(); |
234 | } |
235 | return getFrameSize(I); |
236 | } |
237 | |
238 | unsigned getCatchReturnOpcode() const { return CatchRetOpcode; } |
239 | unsigned getReturnOpcode() const { return ReturnOpcode; } |
240 | |
241 | /// Returns the actual stack pointer adjustment made by an instruction |
242 | /// as part of a call sequence. By default, only call frame setup/destroy |
243 | /// instructions adjust the stack, but targets may want to override this |
244 | /// to enable more fine-grained adjustment, or adjust by a different value. |
245 | virtual int getSPAdjust(const MachineInstr &MI) const; |
246 | |
247 | /// Return true if the instruction is a "coalescable" extension instruction. |
248 | /// That is, it's like a copy where it's legal for the source to overlap the |
249 | /// destination. e.g. X86::MOVSX64rr32. If this returns true, then it's |
250 | /// expected the pre-extension value is available as a subreg of the result |
251 | /// register. This also returns the sub-register index in SubIdx. |
252 | virtual bool isCoalescableExtInstr(const MachineInstr &MI, Register &SrcReg, |
253 | Register &DstReg, unsigned &SubIdx) const { |
254 | return false; |
255 | } |
256 | |
257 | /// If the specified machine instruction is a direct |
258 | /// load from a stack slot, return the virtual or physical register number of |
259 | /// the destination along with the FrameIndex of the loaded stack slot. If |
260 | /// not, return 0. This predicate must return 0 if the instruction has |
261 | /// any side effects other than loading from the stack slot. |
262 | virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, |
263 | int &FrameIndex) const { |
264 | return 0; |
265 | } |
266 | |
267 | /// Optional extension of isLoadFromStackSlot that returns the number of |
268 | /// bytes loaded from the stack. This must be implemented if a backend |
269 | /// supports partial stack slot spills/loads to further disambiguate |
270 | /// what the load does. |
271 | virtual unsigned isLoadFromStackSlot(const MachineInstr &MI, |
272 | int &FrameIndex, |
273 | unsigned &MemBytes) const { |
274 | MemBytes = 0; |
275 | return isLoadFromStackSlot(MI, FrameIndex); |
276 | } |
277 | |
278 | /// Check for post-frame ptr elimination stack locations as well. |
279 | /// This uses a heuristic so it isn't reliable for correctness. |
280 | virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI, |
281 | int &FrameIndex) const { |
282 | return 0; |
283 | } |
284 | |
285 | /// If the specified machine instruction has a load from a stack slot, |
286 | /// return true along with the FrameIndices of the loaded stack slot and the |
287 | /// machine mem operands containing the reference. |
288 | /// If not, return false. Unlike isLoadFromStackSlot, this returns true for |
289 | /// any instructions that loads from the stack. This is just a hint, as some |
290 | /// cases may be missed. |
291 | virtual bool hasLoadFromStackSlot( |
292 | const MachineInstr &MI, |
293 | SmallVectorImpl<const MachineMemOperand *> &Accesses) const; |
294 | |
295 | /// If the specified machine instruction is a direct |
296 | /// store to a stack slot, return the virtual or physical register number of |
297 | /// the source reg along with the FrameIndex of the loaded stack slot. If |
298 | /// not, return 0. This predicate must return 0 if the instruction has |
299 | /// any side effects other than storing to the stack slot. |
300 | virtual unsigned isStoreToStackSlot(const MachineInstr &MI, |
301 | int &FrameIndex) const { |
302 | return 0; |
303 | } |
304 | |
305 | /// Optional extension of isStoreToStackSlot that returns the number of |
306 | /// bytes stored to the stack. This must be implemented if a backend |
307 | /// supports partial stack slot spills/loads to further disambiguate |
308 | /// what the store does. |
309 | virtual unsigned isStoreToStackSlot(const MachineInstr &MI, |
310 | int &FrameIndex, |
311 | unsigned &MemBytes) const { |
312 | MemBytes = 0; |
313 | return isStoreToStackSlot(MI, FrameIndex); |
314 | } |
315 | |
316 | /// Check for post-frame ptr elimination stack locations as well. |
317 | /// This uses a heuristic, so it isn't reliable for correctness. |
318 | virtual unsigned isStoreToStackSlotPostFE(const MachineInstr &MI, |
319 | int &FrameIndex) const { |
320 | return 0; |
321 | } |
322 | |
323 | /// If the specified machine instruction has a store to a stack slot, |
324 | /// return true along with the FrameIndices of the loaded stack slot and the |
325 | /// machine mem operands containing the reference. |
326 | /// If not, return false. Unlike isStoreToStackSlot, |
327 | /// this returns true for any instructions that stores to the |
328 | /// stack. This is just a hint, as some cases may be missed. |
329 | virtual bool hasStoreToStackSlot( |
330 | const MachineInstr &MI, |
331 | SmallVectorImpl<const MachineMemOperand *> &Accesses) const; |
332 | |
333 | /// Return true if the specified machine instruction |
334 | /// is a copy of one stack slot to another and has no other effect. |
335 | /// Provide the identity of the two frame indices. |
336 | virtual bool isStackSlotCopy(const MachineInstr &MI, int &DestFrameIndex, |
337 | int &SrcFrameIndex) const { |
338 | return false; |
339 | } |
340 | |
341 | /// Compute the size in bytes and offset within a stack slot of a spilled |
342 | /// register or subregister. |
343 | /// |
344 | /// \param [out] Size in bytes of the spilled value. |
345 | /// \param [out] Offset in bytes within the stack slot. |
346 | /// \returns true if both Size and Offset are successfully computed. |
347 | /// |
348 | /// Not all subregisters have computable spill slots. For example, |
349 | /// subregisters registers may not be byte-sized, and a pair of discontiguous |
350 | /// subregisters has no single offset. |
351 | /// |
352 | /// Targets with nontrivial bigendian implementations may need to override |
353 | /// this, particularly to support spilled vector registers. |
354 | virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx, |
355 | unsigned &Size, unsigned &Offset, |
356 | const MachineFunction &MF) const; |
357 | |
358 | /// Return true if the given instruction is terminator that is unspillable, |
359 | /// according to isUnspillableTerminatorImpl. |
360 | bool isUnspillableTerminator(const MachineInstr *MI) const { |
361 | return MI->isTerminator() && isUnspillableTerminatorImpl(MI); |
362 | } |
363 | |
364 | /// Returns the size in bytes of the specified MachineInstr, or ~0U |
365 | /// when this function is not implemented by a target. |
366 | virtual unsigned getInstSizeInBytes(const MachineInstr &MI) const { |
367 | return ~0U; |
368 | } |
369 | |
370 | /// Return true if the instruction is as cheap as a move instruction. |
371 | /// |
372 | /// Targets for different archs need to override this, and different |
373 | /// micro-architectures can also be finely tuned inside. |
374 | virtual bool isAsCheapAsAMove(const MachineInstr &MI) const { |
375 | return MI.isAsCheapAsAMove(); |
376 | } |
377 | |
378 | /// Return true if the instruction should be sunk by MachineSink. |
379 | /// |
380 | /// MachineSink determines on its own whether the instruction is safe to sink; |
381 | /// this gives the target a hook to override the default behavior with regards |
382 | /// to which instructions should be sunk. |
383 | virtual bool shouldSink(const MachineInstr &MI) const { return true; } |
384 | |
385 | /// Re-issue the specified 'original' instruction at the |
386 | /// specific location targeting a new destination register. |
387 | /// The register in Orig->getOperand(0).getReg() will be substituted by |
388 | /// DestReg:SubIdx. Any existing subreg index is preserved or composed with |
389 | /// SubIdx. |
390 | virtual void reMaterialize(MachineBasicBlock &MBB, |
391 | MachineBasicBlock::iterator MI, Register DestReg, |
392 | unsigned SubIdx, const MachineInstr &Orig, |
393 | const TargetRegisterInfo &TRI) const; |
394 | |
395 | /// Clones instruction or the whole instruction bundle \p Orig and |
396 | /// insert into \p MBB before \p InsertBefore. The target may update operands |
397 | /// that are required to be unique. |
398 | /// |
399 | /// \p Orig must not return true for MachineInstr::isNotDuplicable(). |
400 | virtual MachineInstr &duplicate(MachineBasicBlock &MBB, |
401 | MachineBasicBlock::iterator InsertBefore, |
402 | const MachineInstr &Orig) const; |
403 | |
404 | /// This method must be implemented by targets that |
405 | /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target |
406 | /// may be able to convert a two-address instruction into one or more true |
407 | /// three-address instructions on demand. This allows the X86 target (for |
408 | /// example) to convert ADD and SHL instructions into LEA instructions if they |
409 | /// would require register copies due to two-addressness. |
410 | /// |
411 | /// This method returns a null pointer if the transformation cannot be |
412 | /// performed, otherwise it returns the last new instruction. |
413 | /// |
414 | virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI, |
415 | MachineInstr &MI, |
416 | LiveVariables *LV) const { |
417 | return nullptr; |
418 | } |
419 | |
420 | // This constant can be used as an input value of operand index passed to |
421 | // the method findCommutedOpIndices() to tell the method that the |
422 | // corresponding operand index is not pre-defined and that the method |
423 | // can pick any commutable operand. |
424 | static const unsigned CommuteAnyOperandIndex = ~0U; |
425 | |
426 | /// This method commutes the operands of the given machine instruction MI. |
427 | /// |
428 | /// The operands to be commuted are specified by their indices OpIdx1 and |
429 | /// OpIdx2. OpIdx1 and OpIdx2 arguments may be set to a special value |
430 | /// 'CommuteAnyOperandIndex', which means that the method is free to choose |
431 | /// any arbitrarily chosen commutable operand. If both arguments are set to |
432 | /// 'CommuteAnyOperandIndex' then the method looks for 2 different commutable |
433 | /// operands; then commutes them if such operands could be found. |
434 | /// |
435 | /// If NewMI is false, MI is modified in place and returned; otherwise, a |
436 | /// new machine instruction is created and returned. |
437 | /// |
438 | /// Do not call this method for a non-commutable instruction or |
439 | /// for non-commuable operands. |
440 | /// Even though the instruction is commutable, the method may still |
441 | /// fail to commute the operands, null pointer is returned in such cases. |
442 | MachineInstr * |
443 | commuteInstruction(MachineInstr &MI, bool NewMI = false, |
444 | unsigned OpIdx1 = CommuteAnyOperandIndex, |
445 | unsigned OpIdx2 = CommuteAnyOperandIndex) const; |
446 | |
447 | /// Returns true iff the routine could find two commutable operands in the |
448 | /// given machine instruction. |
449 | /// The 'SrcOpIdx1' and 'SrcOpIdx2' are INPUT and OUTPUT arguments. |
450 | /// If any of the INPUT values is set to the special value |
451 | /// 'CommuteAnyOperandIndex' then the method arbitrarily picks a commutable |
452 | /// operand, then returns its index in the corresponding argument. |
453 | /// If both of INPUT values are set to 'CommuteAnyOperandIndex' then method |
454 | /// looks for 2 commutable operands. |
455 | /// If INPUT values refer to some operands of MI, then the method simply |
456 | /// returns true if the corresponding operands are commutable and returns |
457 | /// false otherwise. |
458 | /// |
459 | /// For example, calling this method this way: |
460 | /// unsigned Op1 = 1, Op2 = CommuteAnyOperandIndex; |
461 | /// findCommutedOpIndices(MI, Op1, Op2); |
462 | /// can be interpreted as a query asking to find an operand that would be |
463 | /// commutable with the operand#1. |
464 | virtual bool findCommutedOpIndices(const MachineInstr &MI, |
465 | unsigned &SrcOpIdx1, |
466 | unsigned &SrcOpIdx2) const; |
467 | |
468 | /// Returns true if the target has a preference on the operands order of |
469 | /// the given machine instruction. And specify if \p Commute is required to |
470 | /// get the desired operands order. |
471 | virtual bool hasCommutePreference(MachineInstr &MI, bool &Commute) const { |
472 | return false; |
473 | } |
474 | |
475 | /// A pair composed of a register and a sub-register index. |
476 | /// Used to give some type checking when modeling Reg:SubReg. |
477 | struct RegSubRegPair { |
478 | Register Reg; |
479 | unsigned SubReg; |
480 | |
481 | RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0) |
482 | : Reg(Reg), SubReg(SubReg) {} |
483 | |
484 | bool operator==(const RegSubRegPair& P) const { |
485 | return Reg == P.Reg && SubReg == P.SubReg; |
486 | } |
487 | bool operator!=(const RegSubRegPair& P) const { |
488 | return !(*this == P); |
489 | } |
490 | }; |
491 | |
492 | /// A pair composed of a pair of a register and a sub-register index, |
493 | /// and another sub-register index. |
494 | /// Used to give some type checking when modeling Reg:SubReg1, SubReg2. |
495 | struct RegSubRegPairAndIdx : RegSubRegPair { |
496 | unsigned SubIdx; |
497 | |
498 | RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0, |
499 | unsigned SubIdx = 0) |
500 | : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} |
501 | }; |
502 | |
503 | /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI |
504 | /// and \p DefIdx. |
505 | /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of |
506 | /// the list is modeled as <Reg:SubReg, SubIdx>. Operands with the undef |
507 | /// flag are not added to this list. |
508 | /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce |
509 | /// two elements: |
510 | /// - %1:sub1, sub0 |
511 | /// - %2<:0>, sub1 |
512 | /// |
513 | /// \returns true if it is possible to build such an input sequence |
514 | /// with the pair \p MI, \p DefIdx. False otherwise. |
515 | /// |
516 | /// \pre MI.isRegSequence() or MI.isRegSequenceLike(). |
517 | /// |
518 | /// \note The generic implementation does not provide any support for |
519 | /// MI.isRegSequenceLike(). In other words, one has to override |
520 | /// getRegSequenceLikeInputs for target specific instructions. |
521 | bool |
522 | getRegSequenceInputs(const MachineInstr &MI, unsigned DefIdx, |
523 | SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const; |
524 | |
525 | /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI |
526 | /// and \p DefIdx. |
527 | /// \p [out] InputReg of the equivalent EXTRACT_SUBREG. |
528 | /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce: |
529 | /// - %1:sub1, sub0 |
530 | /// |
531 | /// \returns true if it is possible to build such an input sequence |
532 | /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. |
533 | /// False otherwise. |
534 | /// |
535 | /// \pre MI.isExtractSubreg() or MI.isExtractSubregLike(). |
536 | /// |
537 | /// \note The generic implementation does not provide any support for |
538 | /// MI.isExtractSubregLike(). In other words, one has to override |
539 | /// getExtractSubregLikeInputs for target specific instructions. |
540 | bool getExtractSubregInputs(const MachineInstr &MI, unsigned DefIdx, |
541 | RegSubRegPairAndIdx &InputReg) const; |
542 | |
543 | /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI |
544 | /// and \p DefIdx. |
545 | /// \p [out] BaseReg and \p [out] InsertedReg contain |
546 | /// the equivalent inputs of INSERT_SUBREG. |
547 | /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce: |
548 | /// - BaseReg: %0:sub0 |
549 | /// - InsertedReg: %1:sub1, sub3 |
550 | /// |
551 | /// \returns true if it is possible to build such an input sequence |
552 | /// with the pair \p MI, \p DefIdx and the operand has no undef flag set. |
553 | /// False otherwise. |
554 | /// |
555 | /// \pre MI.isInsertSubreg() or MI.isInsertSubregLike(). |
556 | /// |
557 | /// \note The generic implementation does not provide any support for |
558 | /// MI.isInsertSubregLike(). In other words, one has to override |
559 | /// getInsertSubregLikeInputs for target specific instructions. |
560 | bool getInsertSubregInputs(const MachineInstr &MI, unsigned DefIdx, |
561 | RegSubRegPair &BaseReg, |
562 | RegSubRegPairAndIdx &InsertedReg) const; |
563 | |
564 | /// Return true if two machine instructions would produce identical values. |
565 | /// By default, this is only true when the two instructions |
566 | /// are deemed identical except for defs. If this function is called when the |
567 | /// IR is still in SSA form, the caller can pass the MachineRegisterInfo for |
568 | /// aggressive checks. |
569 | virtual bool produceSameValue(const MachineInstr &MI0, |
570 | const MachineInstr &MI1, |
571 | const MachineRegisterInfo *MRI = nullptr) const; |
572 | |
573 | /// \returns true if a branch from an instruction with opcode \p BranchOpc |
574 | /// bytes is capable of jumping to a position \p BrOffset bytes away. |
575 | virtual bool isBranchOffsetInRange(unsigned BranchOpc, |
576 | int64_t BrOffset) const { |
577 | llvm_unreachable("target did not implement")__builtin_unreachable(); |
578 | } |
579 | |
580 | /// \returns The block that branch instruction \p MI jumps to. |
581 | virtual MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const { |
582 | llvm_unreachable("target did not implement")__builtin_unreachable(); |
583 | } |
584 | |
585 | /// Insert an unconditional indirect branch at the end of \p MBB to \p |
586 | /// NewDestBB. \p BrOffset indicates the offset of \p NewDestBB relative to |
587 | /// the offset of the position to insert the new branch. |
588 | /// |
589 | /// \returns The number of bytes added to the block. |
590 | virtual unsigned insertIndirectBranch(MachineBasicBlock &MBB, |
591 | MachineBasicBlock &NewDestBB, |
592 | const DebugLoc &DL, |
593 | int64_t BrOffset = 0, |
594 | RegScavenger *RS = nullptr) const { |
595 | llvm_unreachable("target did not implement")__builtin_unreachable(); |
596 | } |
597 | |
598 | /// Analyze the branching code at the end of MBB, returning |
599 | /// true if it cannot be understood (e.g. it's a switch dispatch or isn't |
600 | /// implemented for a target). Upon success, this returns false and returns |
601 | /// with the following information in various cases: |
602 | /// |
603 | /// 1. If this block ends with no branches (it just falls through to its succ) |
604 | /// just return false, leaving TBB/FBB null. |
605 | /// 2. If this block ends with only an unconditional branch, it sets TBB to be |
606 | /// the destination block. |
607 | /// 3. If this block ends with a conditional branch and it falls through to a |
608 | /// successor block, it sets TBB to be the branch destination block and a |
609 | /// list of operands that evaluate the condition. These operands can be |
610 | /// passed to other TargetInstrInfo methods to create new branches. |
611 | /// 4. If this block ends with a conditional branch followed by an |
612 | /// unconditional branch, it returns the 'true' destination in TBB, the |
613 | /// 'false' destination in FBB, and a list of operands that evaluate the |
614 | /// condition. These operands can be passed to other TargetInstrInfo |
615 | /// methods to create new branches. |
616 | /// |
617 | /// Note that removeBranch and insertBranch must be implemented to support |
618 | /// cases where this method returns success. |
619 | /// |
620 | /// If AllowModify is true, then this routine is allowed to modify the basic |
621 | /// block (e.g. delete instructions after the unconditional branch). |
622 | /// |
623 | /// The CFG information in MBB.Predecessors and MBB.Successors must be valid |
624 | /// before calling this function. |
625 | virtual bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, |
626 | MachineBasicBlock *&FBB, |
627 | SmallVectorImpl<MachineOperand> &Cond, |
628 | bool AllowModify = false) const { |
629 | return true; |
630 | } |
631 | |
632 | /// Represents a predicate at the MachineFunction level. The control flow a |
633 | /// MachineBranchPredicate represents is: |
634 | /// |
635 | /// Reg = LHS `Predicate` RHS == ConditionDef |
636 | /// if Reg then goto TrueDest else goto FalseDest |
637 | /// |
638 | struct MachineBranchPredicate { |
639 | enum ComparePredicate { |
640 | PRED_EQ, // True if two values are equal |
641 | PRED_NE, // True if two values are not equal |
642 | PRED_INVALID // Sentinel value |
643 | }; |
644 | |
645 | ComparePredicate Predicate = PRED_INVALID; |
646 | MachineOperand LHS = MachineOperand::CreateImm(0); |
647 | MachineOperand RHS = MachineOperand::CreateImm(0); |
648 | MachineBasicBlock *TrueDest = nullptr; |
649 | MachineBasicBlock *FalseDest = nullptr; |
650 | MachineInstr *ConditionDef = nullptr; |
651 | |
652 | /// SingleUseCondition is true if ConditionDef is dead except for the |
653 | /// branch(es) at the end of the basic block. |
654 | /// |
655 | bool SingleUseCondition = false; |
656 | |
657 | explicit MachineBranchPredicate() = default; |
658 | }; |
659 | |
660 | /// Analyze the branching code at the end of MBB and parse it into the |
661 | /// MachineBranchPredicate structure if possible. Returns false on success |
662 | /// and true on failure. |
663 | /// |
664 | /// If AllowModify is true, then this routine is allowed to modify the basic |
665 | /// block (e.g. delete instructions after the unconditional branch). |
666 | /// |
667 | virtual bool analyzeBranchPredicate(MachineBasicBlock &MBB, |
668 | MachineBranchPredicate &MBP, |
669 | bool AllowModify = false) const { |
670 | return true; |
671 | } |
672 | |
673 | /// Remove the branching code at the end of the specific MBB. |
674 | /// This is only invoked in cases where analyzeBranch returns success. It |
675 | /// returns the number of instructions that were removed. |
676 | /// If \p BytesRemoved is non-null, report the change in code size from the |
677 | /// removed instructions. |
678 | virtual unsigned removeBranch(MachineBasicBlock &MBB, |
679 | int *BytesRemoved = nullptr) const { |
680 | llvm_unreachable("Target didn't implement TargetInstrInfo::removeBranch!")__builtin_unreachable(); |
681 | } |
682 | |
683 | /// Insert branch code into the end of the specified MachineBasicBlock. The |
684 | /// operands to this method are the same as those returned by analyzeBranch. |
685 | /// This is only invoked in cases where analyzeBranch returns success. It |
686 | /// returns the number of instructions inserted. If \p BytesAdded is non-null, |
687 | /// report the change in code size from the added instructions. |
688 | /// |
689 | /// It is also invoked by tail merging to add unconditional branches in |
690 | /// cases where analyzeBranch doesn't apply because there was no original |
691 | /// branch to analyze. At least this much must be implemented, else tail |
692 | /// merging needs to be disabled. |
693 | /// |
694 | /// The CFG information in MBB.Predecessors and MBB.Successors must be valid |
695 | /// before calling this function. |
696 | virtual unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, |
697 | MachineBasicBlock *FBB, |
698 | ArrayRef<MachineOperand> Cond, |
699 | const DebugLoc &DL, |
700 | int *BytesAdded = nullptr) const { |
701 | llvm_unreachable("Target didn't implement TargetInstrInfo::insertBranch!")__builtin_unreachable(); |
702 | } |
703 | |
704 | unsigned insertUnconditionalBranch(MachineBasicBlock &MBB, |
705 | MachineBasicBlock *DestBB, |
706 | const DebugLoc &DL, |
707 | int *BytesAdded = nullptr) const { |
708 | return insertBranch(MBB, DestBB, nullptr, ArrayRef<MachineOperand>(), DL, |
709 | BytesAdded); |
710 | } |
711 | |
712 | /// Object returned by analyzeLoopForPipelining. Allows software pipelining |
713 | /// implementations to query attributes of the loop being pipelined and to |
714 | /// apply target-specific updates to the loop once pipelining is complete. |
715 | class PipelinerLoopInfo { |
716 | public: |
717 | virtual ~PipelinerLoopInfo(); |
718 | /// Return true if the given instruction should not be pipelined and should |
719 | /// be ignored. An example could be a loop comparison, or induction variable |
720 | /// update with no users being pipelined. |
721 | virtual bool shouldIgnoreForPipelining(const MachineInstr *MI) const = 0; |
722 | |
723 | /// Create a condition to determine if the trip count of the loop is greater |
724 | /// than TC. |
725 | /// |
726 | /// If the trip count is statically known to be greater than TC, return |
727 | /// true. If the trip count is statically known to be not greater than TC, |
728 | /// return false. Otherwise return nullopt and fill out Cond with the test |
729 | /// condition. |
730 | virtual Optional<bool> |
731 | createTripCountGreaterCondition(int TC, MachineBasicBlock &MBB, |
732 | SmallVectorImpl<MachineOperand> &Cond) = 0; |
733 | |
734 | /// Modify the loop such that the trip count is |
735 | /// OriginalTC + TripCountAdjust. |
736 | virtual void adjustTripCount(int TripCountAdjust) = 0; |
737 | |
738 | /// Called when the loop's preheader has been modified to NewPreheader. |
739 | virtual void setPreheader(MachineBasicBlock *NewPreheader) = 0; |
740 | |
741 | /// Called when the loop is being removed. Any instructions in the preheader |
742 | /// should be removed. |
743 | /// |
744 | /// Once this function is called, no other functions on this object are |
745 | /// valid; the loop has been removed. |
746 | virtual void disposed() = 0; |
747 | }; |
748 | |
749 | /// Analyze loop L, which must be a single-basic-block loop, and if the |
750 | /// conditions can be understood enough produce a PipelinerLoopInfo object. |
751 | virtual std::unique_ptr<PipelinerLoopInfo> |
752 | analyzeLoopForPipelining(MachineBasicBlock *LoopBB) const { |
753 | return nullptr; |
754 | } |
755 | |
756 | /// Analyze the loop code, return true if it cannot be understood. Upon |
757 | /// success, this function returns false and returns information about the |
758 | /// induction variable and compare instruction used at the end. |
759 | virtual bool analyzeLoop(MachineLoop &L, MachineInstr *&IndVarInst, |
760 | MachineInstr *&CmpInst) const { |
761 | return true; |
762 | } |
763 | |
764 | /// Generate code to reduce the loop iteration by one and check if the loop |
765 | /// is finished. Return the value/register of the new loop count. We need |
766 | /// this function when peeling off one or more iterations of a loop. This |
767 | /// function assumes the nth iteration is peeled first. |
768 | virtual unsigned reduceLoopCount(MachineBasicBlock &MBB, |
769 | MachineBasicBlock &PreHeader, |
770 | MachineInstr *IndVar, MachineInstr &Cmp, |
771 | SmallVectorImpl<MachineOperand> &Cond, |
772 | SmallVectorImpl<MachineInstr *> &PrevInsts, |
773 | unsigned Iter, unsigned MaxIter) const { |
774 | llvm_unreachable("Target didn't implement ReduceLoopCount")__builtin_unreachable(); |
775 | } |
776 | |
777 | /// Delete the instruction OldInst and everything after it, replacing it with |
778 | /// an unconditional branch to NewDest. This is used by the tail merging pass. |
779 | virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail, |
780 | MachineBasicBlock *NewDest) const; |
781 | |
782 | /// Return true if it's legal to split the given basic |
783 | /// block at the specified instruction (i.e. instruction would be the start |
784 | /// of a new basic block). |
785 | virtual bool isLegalToSplitMBBAt(MachineBasicBlock &MBB, |
786 | MachineBasicBlock::iterator MBBI) const { |
787 | return true; |
788 | } |
789 | |
790 | /// Return true if it's profitable to predicate |
791 | /// instructions with accumulated instruction latency of "NumCycles" |
792 | /// of the specified basic block, where the probability of the instructions |
793 | /// being executed is given by Probability, and Confidence is a measure |
794 | /// of our confidence that it will be properly predicted. |
795 | virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles, |
796 | unsigned ExtraPredCycles, |
797 | BranchProbability Probability) const { |
798 | return false; |
799 | } |
800 | |
801 | /// Second variant of isProfitableToIfCvt. This one |
802 | /// checks for the case where two basic blocks from true and false path |
803 | /// of a if-then-else (diamond) are predicated on mutually exclusive |
804 | /// predicates, where the probability of the true path being taken is given |
805 | /// by Probability, and Confidence is a measure of our confidence that it |
806 | /// will be properly predicted. |
807 | virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTCycles, |
808 | unsigned ExtraTCycles, |
809 | MachineBasicBlock &FMBB, unsigned NumFCycles, |
810 | unsigned ExtraFCycles, |
811 | BranchProbability Probability) const { |
812 | return false; |
813 | } |
814 | |
815 | /// Return true if it's profitable for if-converter to duplicate instructions |
816 | /// of specified accumulated instruction latencies in the specified MBB to |
817 | /// enable if-conversion. |
818 | /// The probability of the instructions being executed is given by |
819 | /// Probability, and Confidence is a measure of our confidence that it |
820 | /// will be properly predicted. |
821 | virtual bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, |
822 | unsigned NumCycles, |
823 | BranchProbability Probability) const { |
824 | return false; |
825 | } |
826 | |
827 | /// Return the increase in code size needed to predicate a contiguous run of |
828 | /// NumInsts instructions. |
829 | virtual unsigned extraSizeToPredicateInstructions(const MachineFunction &MF, |
830 | unsigned NumInsts) const { |
831 | return 0; |
832 | } |
833 | |
834 | /// Return an estimate for the code size reduction (in bytes) which will be |
835 | /// caused by removing the given branch instruction during if-conversion. |
836 | virtual unsigned predictBranchSizeForIfCvt(MachineInstr &MI) const { |
837 | return getInstSizeInBytes(MI); |
838 | } |
839 | |
840 | /// Return true if it's profitable to unpredicate |
841 | /// one side of a 'diamond', i.e. two sides of if-else predicated on mutually |
842 | /// exclusive predicates. |
843 | /// e.g. |
844 | /// subeq r0, r1, #1 |
845 | /// addne r0, r1, #1 |
846 | /// => |
847 | /// sub r0, r1, #1 |
848 | /// addne r0, r1, #1 |
849 | /// |
850 | /// This may be profitable is conditional instructions are always executed. |
851 | virtual bool isProfitableToUnpredicate(MachineBasicBlock &TMBB, |
852 | MachineBasicBlock &FMBB) const { |
853 | return false; |
854 | } |
855 | |
856 | /// Return true if it is possible to insert a select |
857 | /// instruction that chooses between TrueReg and FalseReg based on the |
858 | /// condition code in Cond. |
859 | /// |
860 | /// When successful, also return the latency in cycles from TrueReg, |
861 | /// FalseReg, and Cond to the destination register. In most cases, a select |
862 | /// instruction will be 1 cycle, so CondCycles = TrueCycles = FalseCycles = 1 |
863 | /// |
864 | /// Some x86 implementations have 2-cycle cmov instructions. |
865 | /// |
866 | /// @param MBB Block where select instruction would be inserted. |
867 | /// @param Cond Condition returned by analyzeBranch. |
868 | /// @param DstReg Virtual dest register that the result should write to. |
869 | /// @param TrueReg Virtual register to select when Cond is true. |
870 | /// @param FalseReg Virtual register to select when Cond is false. |
871 | /// @param CondCycles Latency from Cond+Branch to select output. |
872 | /// @param TrueCycles Latency from TrueReg to select output. |
873 | /// @param FalseCycles Latency from FalseReg to select output. |
874 | virtual bool canInsertSelect(const MachineBasicBlock &MBB, |
875 | ArrayRef<MachineOperand> Cond, Register DstReg, |
876 | Register TrueReg, Register FalseReg, |
877 | int &CondCycles, int &TrueCycles, |
878 | int &FalseCycles) const { |
879 | return false; |
880 | } |
881 | |
882 | /// Insert a select instruction into MBB before I that will copy TrueReg to |
883 | /// DstReg when Cond is true, and FalseReg to DstReg when Cond is false. |
884 | /// |
885 | /// This function can only be called after canInsertSelect() returned true. |
886 | /// The condition in Cond comes from analyzeBranch, and it can be assumed |
887 | /// that the same flags or registers required by Cond are available at the |
888 | /// insertion point. |
889 | /// |
890 | /// @param MBB Block where select instruction should be inserted. |
891 | /// @param I Insertion point. |
892 | /// @param DL Source location for debugging. |
893 | /// @param DstReg Virtual register to be defined by select instruction. |
894 | /// @param Cond Condition as computed by analyzeBranch. |
895 | /// @param TrueReg Virtual register to copy when Cond is true. |
896 | /// @param FalseReg Virtual register to copy when Cons is false. |
897 | virtual void insertSelect(MachineBasicBlock &MBB, |
898 | MachineBasicBlock::iterator I, const DebugLoc &DL, |
899 | Register DstReg, ArrayRef<MachineOperand> Cond, |
900 | Register TrueReg, Register FalseReg) const { |
901 | llvm_unreachable("Target didn't implement TargetInstrInfo::insertSelect!")__builtin_unreachable(); |
902 | } |
903 | |
904 | /// Analyze the given select instruction, returning true if |
905 | /// it cannot be understood. It is assumed that MI->isSelect() is true. |
906 | /// |
907 | /// When successful, return the controlling condition and the operands that |
908 | /// determine the true and false result values. |
909 | /// |
910 | /// Result = SELECT Cond, TrueOp, FalseOp |
911 | /// |
912 | /// Some targets can optimize select instructions, for example by predicating |
913 | /// the instruction defining one of the operands. Such targets should set |
914 | /// Optimizable. |
915 | /// |
916 | /// @param MI Select instruction to analyze. |
917 | /// @param Cond Condition controlling the select. |
918 | /// @param TrueOp Operand number of the value selected when Cond is true. |
919 | /// @param FalseOp Operand number of the value selected when Cond is false. |
920 | /// @param Optimizable Returned as true if MI is optimizable. |
921 | /// @returns False on success. |
922 | virtual bool analyzeSelect(const MachineInstr &MI, |
923 | SmallVectorImpl<MachineOperand> &Cond, |
924 | unsigned &TrueOp, unsigned &FalseOp, |
925 | bool &Optimizable) const { |
926 | assert(MI.getDesc().isSelect() && "MI must be a select instruction")((void)0); |
927 | return true; |
928 | } |
929 | |
930 | /// Given a select instruction that was understood by |
931 | /// analyzeSelect and returned Optimizable = true, attempt to optimize MI by |
932 | /// merging it with one of its operands. Returns NULL on failure. |
933 | /// |
934 | /// When successful, returns the new select instruction. The client is |
935 | /// responsible for deleting MI. |
936 | /// |
937 | /// If both sides of the select can be optimized, PreferFalse is used to pick |
938 | /// a side. |
939 | /// |
940 | /// @param MI Optimizable select instruction. |
941 | /// @param NewMIs Set that record all MIs in the basic block up to \p |
942 | /// MI. Has to be updated with any newly created MI or deleted ones. |
943 | /// @param PreferFalse Try to optimize FalseOp instead of TrueOp. |
944 | /// @returns Optimized instruction or NULL. |
945 | virtual MachineInstr *optimizeSelect(MachineInstr &MI, |
946 | SmallPtrSetImpl<MachineInstr *> &NewMIs, |
947 | bool PreferFalse = false) const { |
948 | // This function must be implemented if Optimizable is ever set. |
949 | llvm_unreachable("Target must implement TargetInstrInfo::optimizeSelect!")__builtin_unreachable(); |
950 | } |
951 | |
952 | /// Emit instructions to copy a pair of physical registers. |
953 | /// |
954 | /// This function should support copies within any legal register class as |
955 | /// well as any cross-class copies created during instruction selection. |
956 | /// |
957 | /// The source and destination registers may overlap, which may require a |
958 | /// careful implementation when multiple copy instructions are required for |
959 | /// large registers. See for example the ARM target. |
960 | virtual void copyPhysReg(MachineBasicBlock &MBB, |
961 | MachineBasicBlock::iterator MI, const DebugLoc &DL, |
962 | MCRegister DestReg, MCRegister SrcReg, |
963 | bool KillSrc) const { |
964 | llvm_unreachable("Target didn't implement TargetInstrInfo::copyPhysReg!")__builtin_unreachable(); |
965 | } |
966 | |
967 | /// Allow targets to tell MachineVerifier whether a specific register |
968 | /// MachineOperand can be used as part of PC-relative addressing. |
969 | /// PC-relative addressing modes in many CISC architectures contain |
970 | /// (non-PC) registers as offsets or scaling values, which inherently |
971 | /// tags the corresponding MachineOperand with OPERAND_PCREL. |
972 | /// |
973 | /// @param MO The MachineOperand in question. MO.isReg() should always |
974 | /// be true. |
975 | /// @return Whether this operand is allowed to be used PC-relatively. |
976 | virtual bool isPCRelRegisterOperandLegal(const MachineOperand &MO) const { |
977 | return false; |
978 | } |
979 | |
980 | protected: |
981 | /// Target-dependent implementation for IsCopyInstr. |
982 | /// If the specific machine instruction is a instruction that moves/copies |
983 | /// value from one register to another register return destination and source |
984 | /// registers as machine operands. |
985 | virtual Optional<DestSourcePair> |
986 | isCopyInstrImpl(const MachineInstr &MI) const { |
987 | return None; |
988 | } |
989 | |
990 | /// Return true if the given terminator MI is not expected to spill. This |
991 | /// sets the live interval as not spillable and adjusts phi node lowering to |
992 | /// not introduce copies after the terminator. Use with care, these are |
993 | /// currently used for hardware loop intrinsics in very controlled situations, |
994 | /// created prior to registry allocation in loops that only have single phi |
995 | /// users for the terminators value. They may run out of registers if not used |
996 | /// carefully. |
997 | virtual bool isUnspillableTerminatorImpl(const MachineInstr *MI) const { |
998 | return false; |
999 | } |
1000 | |
1001 | public: |
1002 | /// If the specific machine instruction is a instruction that moves/copies |
1003 | /// value from one register to another register return destination and source |
1004 | /// registers as machine operands. |
1005 | /// For COPY-instruction the method naturally returns destination and source |
1006 | /// registers as machine operands, for all other instructions the method calls |
1007 | /// target-dependent implementation. |
1008 | Optional<DestSourcePair> isCopyInstr(const MachineInstr &MI) const { |
1009 | if (MI.isCopy()) { |
1010 | return DestSourcePair{MI.getOperand(0), MI.getOperand(1)}; |
1011 | } |
1012 | return isCopyInstrImpl(MI); |
1013 | } |
1014 | |
1015 | /// If the specific machine instruction is an instruction that adds an |
1016 | /// immediate value and a physical register, and stores the result in |
1017 | /// the given physical register \c Reg, return a pair of the source |
1018 | /// register and the offset which has been added. |
1019 | virtual Optional<RegImmPair> isAddImmediate(const MachineInstr &MI, |
1020 | Register Reg) const { |
1021 | return None; |
1022 | } |
1023 | |
1024 | /// Returns true if MI is an instruction that defines Reg to have a constant |
1025 | /// value and the value is recorded in ImmVal. The ImmVal is a result that |
1026 | /// should be interpreted as modulo size of Reg. |
1027 | virtual bool getConstValDefinedInReg(const MachineInstr &MI, |
1028 | const Register Reg, |
1029 | int64_t &ImmVal) const { |
1030 | return false; |
1031 | } |
1032 | |
1033 | /// Store the specified register of the given register class to the specified |
1034 | /// stack frame index. The store instruction is to be added to the given |
1035 | /// machine basic block before the specified machine instruction. If isKill |
1036 | /// is true, the register operand is the last use and must be marked kill. |
1037 | virtual void storeRegToStackSlot(MachineBasicBlock &MBB, |
1038 | MachineBasicBlock::iterator MI, |
1039 | Register SrcReg, bool isKill, int FrameIndex, |
1040 | const TargetRegisterClass *RC, |
1041 | const TargetRegisterInfo *TRI) const { |
1042 | llvm_unreachable("Target didn't implement "__builtin_unreachable() |
1043 | "TargetInstrInfo::storeRegToStackSlot!")__builtin_unreachable(); |
1044 | } |
1045 | |
1046 | /// Load the specified register of the given register class from the specified |
1047 | /// stack frame index. The load instruction is to be added to the given |
1048 | /// machine basic block before the specified machine instruction. |
1049 | virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, |
1050 | MachineBasicBlock::iterator MI, |
1051 | Register DestReg, int FrameIndex, |
1052 | const TargetRegisterClass *RC, |
1053 | const TargetRegisterInfo *TRI) const { |
1054 | llvm_unreachable("Target didn't implement "__builtin_unreachable() |
1055 | "TargetInstrInfo::loadRegFromStackSlot!")__builtin_unreachable(); |
1056 | } |
1057 | |
1058 | /// This function is called for all pseudo instructions |
1059 | /// that remain after register allocation. Many pseudo instructions are |
1060 | /// created to help register allocation. This is the place to convert them |
1061 | /// into real instructions. The target can edit MI in place, or it can insert |
1062 | /// new instructions and erase MI. The function should return true if |
1063 | /// anything was changed. |
1064 | virtual bool expandPostRAPseudo(MachineInstr &MI) const { return false; } |
1065 | |
1066 | /// Check whether the target can fold a load that feeds a subreg operand |
1067 | /// (or a subreg operand that feeds a store). |
1068 | /// For example, X86 may want to return true if it can fold |
1069 | /// movl (%esp), %eax |
1070 | /// subb, %al, ... |
1071 | /// Into: |
1072 | /// subb (%esp), ... |
1073 | /// |
1074 | /// Ideally, we'd like the target implementation of foldMemoryOperand() to |
1075 | /// reject subregs - but since this behavior used to be enforced in the |
1076 | /// target-independent code, moving this responsibility to the targets |
1077 | /// has the potential of causing nasty silent breakage in out-of-tree targets. |
1078 | virtual bool isSubregFoldable() const { return false; } |
1079 | |
1080 | /// For a patchpoint, stackmap, or statepoint intrinsic, return the range of |
1081 | /// operands which can't be folded into stack references. Operands outside |
1082 | /// of the range are most likely foldable but it is not guaranteed. |
1083 | /// These instructions are unique in that stack references for some operands |
1084 | /// have the same execution cost (e.g. none) as the unfolded register forms. |
1085 | /// The ranged return is guaranteed to include all operands which can't be |
1086 | /// folded at zero cost. |
1087 | virtual std::pair<unsigned, unsigned> |
1088 | getPatchpointUnfoldableRange(const MachineInstr &MI) const; |
1089 | |
1090 | /// Attempt to fold a load or store of the specified stack |
1091 | /// slot into the specified machine instruction for the specified operand(s). |
1092 | /// If this is possible, a new instruction is returned with the specified |
1093 | /// operand folded, otherwise NULL is returned. |
1094 | /// The new instruction is inserted before MI, and the client is responsible |
1095 | /// for removing the old instruction. |
1096 | /// If VRM is passed, the assigned physregs can be inspected by target to |
1097 | /// decide on using an opcode (note that those assignments can still change). |
1098 | MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops, |
1099 | int FI, |
1100 | LiveIntervals *LIS = nullptr, |
1101 | VirtRegMap *VRM = nullptr) const; |
1102 | |
1103 | /// Same as the previous version except it allows folding of any load and |
1104 | /// store from / to any address, not just from a specific stack slot. |
1105 | MachineInstr *foldMemoryOperand(MachineInstr &MI, ArrayRef<unsigned> Ops, |
1106 | MachineInstr &LoadMI, |
1107 | LiveIntervals *LIS = nullptr) const; |
1108 | |
1109 | /// Return true when there is potentially a faster code sequence |
1110 | /// for an instruction chain ending in \p Root. All potential patterns are |
1111 | /// returned in the \p Pattern vector. Pattern should be sorted in priority |
1112 | /// order since the pattern evaluator stops checking as soon as it finds a |
1113 | /// faster sequence. |
1114 | /// \param Root - Instruction that could be combined with one of its operands |
1115 | /// \param Patterns - Vector of possible combination patterns |
1116 | virtual bool |
1117 | getMachineCombinerPatterns(MachineInstr &Root, |
1118 | SmallVectorImpl<MachineCombinerPattern> &Patterns, |
1119 | bool DoRegPressureReduce) const; |
1120 | |
1121 | /// Return true if target supports reassociation of instructions in machine |
1122 | /// combiner pass to reduce register pressure for a given BB. |
1123 | virtual bool |
1124 | shouldReduceRegisterPressure(MachineBasicBlock *MBB, |
1125 | RegisterClassInfo *RegClassInfo) const { |
1126 | return false; |
1127 | } |
1128 | |
1129 | /// Fix up the placeholder we may add in genAlternativeCodeSequence(). |
1130 | virtual void |
1131 | finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P, |
1132 | SmallVectorImpl<MachineInstr *> &InsInstrs) const {} |
1133 | |
1134 | /// Return true when a code sequence can improve throughput. It |
1135 | /// should be called only for instructions in loops. |
1136 | /// \param Pattern - combiner pattern |
1137 | virtual bool isThroughputPattern(MachineCombinerPattern Pattern) const; |
1138 | |
1139 | /// Return true if the input \P Inst is part of a chain of dependent ops |
1140 | /// that are suitable for reassociation, otherwise return false. |
1141 | /// If the instruction's operands must be commuted to have a previous |
1142 | /// instruction of the same type define the first source operand, \P Commuted |
1143 | /// will be set to true. |
1144 | bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const; |
1145 | |
1146 | /// Return true when \P Inst is both associative and commutative. |
1147 | virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const { |
1148 | return false; |
1149 | } |
1150 | |
1151 | /// Return true when \P Inst has reassociable operands in the same \P MBB. |
1152 | virtual bool hasReassociableOperands(const MachineInstr &Inst, |
1153 | const MachineBasicBlock *MBB) const; |
1154 | |
1155 | /// Return true when \P Inst has reassociable sibling. |
1156 | bool hasReassociableSibling(const MachineInstr &Inst, bool &Commuted) const; |
1157 | |
1158 | /// When getMachineCombinerPatterns() finds patterns, this function generates |
1159 | /// the instructions that could replace the original code sequence. The client |
1160 | /// has to decide whether the actual replacement is beneficial or not. |
1161 | /// \param Root - Instruction that could be combined with one of its operands |
1162 | /// \param Pattern - Combination pattern for Root |
1163 | /// \param InsInstrs - Vector of new instructions that implement P |
1164 | /// \param DelInstrs - Old instructions, including Root, that could be |
1165 | /// replaced by InsInstr |
1166 | /// \param InstIdxForVirtReg - map of virtual register to instruction in |
1167 | /// InsInstr that defines it |
1168 | virtual void genAlternativeCodeSequence( |
1169 | MachineInstr &Root, MachineCombinerPattern Pattern, |
1170 | SmallVectorImpl<MachineInstr *> &InsInstrs, |
1171 | SmallVectorImpl<MachineInstr *> &DelInstrs, |
1172 | DenseMap<unsigned, unsigned> &InstIdxForVirtReg) const; |
1173 | |
1174 | /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to |
1175 | /// reduce critical path length. |
1176 | void reassociateOps(MachineInstr &Root, MachineInstr &Prev, |
1177 | MachineCombinerPattern Pattern, |
1178 | SmallVectorImpl<MachineInstr *> &InsInstrs, |
1179 | SmallVectorImpl<MachineInstr *> &DelInstrs, |
1180 | DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const; |
1181 | |
1182 | /// The limit on resource length extension we accept in MachineCombiner Pass. |
1183 | virtual int getExtendResourceLenLimit() const { return 0; } |
1184 | |
1185 | /// This is an architecture-specific helper function of reassociateOps. |
1186 | /// Set special operand attributes for new instructions after reassociation. |
1187 | virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2, |
1188 | MachineInstr &NewMI1, |
1189 | MachineInstr &NewMI2) const {} |
1190 | |
1191 | virtual void setSpecialOperandAttr(MachineInstr &MI, uint16_t Flags) const {} |
1192 | |
1193 | /// Return true when a target supports MachineCombiner. |
1194 | virtual bool useMachineCombiner() const { return false; } |
1195 | |
1196 | /// Return true if the given SDNode can be copied during scheduling |
1197 | /// even if it has glue. |
1198 | virtual bool canCopyGluedNodeDuringSchedule(SDNode *N) const { return false; } |
1199 | |
1200 | protected: |
1201 | /// Target-dependent implementation for foldMemoryOperand. |
1202 | /// Target-independent code in foldMemoryOperand will |
1203 | /// take care of adding a MachineMemOperand to the newly created instruction. |
1204 | /// The instruction and any auxiliary instructions necessary will be inserted |
1205 | /// at InsertPt. |
1206 | virtual MachineInstr * |
1207 | foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI, |
1208 | ArrayRef<unsigned> Ops, |
1209 | MachineBasicBlock::iterator InsertPt, int FrameIndex, |
1210 | LiveIntervals *LIS = nullptr, |
1211 | VirtRegMap *VRM = nullptr) const { |
1212 | return nullptr; |
1213 | } |
1214 | |
1215 | /// Target-dependent implementation for foldMemoryOperand. |
1216 | /// Target-independent code in foldMemoryOperand will |
1217 | /// take care of adding a MachineMemOperand to the newly created instruction. |
1218 | /// The instruction and any auxiliary instructions necessary will be inserted |
1219 | /// at InsertPt. |
1220 | virtual MachineInstr *foldMemoryOperandImpl( |
1221 | MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops, |
1222 | MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI, |
1223 | LiveIntervals *LIS = nullptr) const { |
1224 | return nullptr; |
1225 | } |
1226 | |
1227 | /// Target-dependent implementation of getRegSequenceInputs. |
1228 | /// |
1229 | /// \returns true if it is possible to build the equivalent |
1230 | /// REG_SEQUENCE inputs with the pair \p MI, \p DefIdx. False otherwise. |
1231 | /// |
1232 | /// \pre MI.isRegSequenceLike(). |
1233 | /// |
1234 | /// \see TargetInstrInfo::getRegSequenceInputs. |
1235 | virtual bool getRegSequenceLikeInputs( |
1236 | const MachineInstr &MI, unsigned DefIdx, |
1237 | SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const { |
1238 | return false; |
1239 | } |
1240 | |
1241 | /// Target-dependent implementation of getExtractSubregInputs. |
1242 | /// |
1243 | /// \returns true if it is possible to build the equivalent |
1244 | /// EXTRACT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise. |
1245 | /// |
1246 | /// \pre MI.isExtractSubregLike(). |
1247 | /// |
1248 | /// \see TargetInstrInfo::getExtractSubregInputs. |
1249 | virtual bool getExtractSubregLikeInputs(const MachineInstr &MI, |
1250 | unsigned DefIdx, |
1251 | RegSubRegPairAndIdx &InputReg) const { |
1252 | return false; |
1253 | } |
1254 | |
1255 | /// Target-dependent implementation of getInsertSubregInputs. |
1256 | /// |
1257 | /// \returns true if it is possible to build the equivalent |
1258 | /// INSERT_SUBREG inputs with the pair \p MI, \p DefIdx. False otherwise. |
1259 | /// |
1260 | /// \pre MI.isInsertSubregLike(). |
1261 | /// |
1262 | /// \see TargetInstrInfo::getInsertSubregInputs. |
1263 | virtual bool |
1264 | getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx, |
1265 | RegSubRegPair &BaseReg, |
1266 | RegSubRegPairAndIdx &InsertedReg) const { |
1267 | return false; |
1268 | } |
1269 | |
1270 | public: |
1271 | /// getAddressSpaceForPseudoSourceKind - Given the kind of memory |
1272 | /// (e.g. stack) the target returns the corresponding address space. |
1273 | virtual unsigned |
1274 | getAddressSpaceForPseudoSourceKind(unsigned Kind) const { |
1275 | return 0; |
1276 | } |
1277 | |
1278 | /// unfoldMemoryOperand - Separate a single instruction which folded a load or |
1279 | /// a store or a load and a store into two or more instruction. If this is |
1280 | /// possible, returns true as well as the new instructions by reference. |
1281 | virtual bool |
1282 | unfoldMemoryOperand(MachineFunction &MF, MachineInstr &MI, unsigned Reg, |
1283 | bool UnfoldLoad, bool UnfoldStore, |
1284 | SmallVectorImpl<MachineInstr *> &NewMIs) const { |
1285 | return false; |
1286 | } |
1287 | |
1288 | virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, |
1289 | SmallVectorImpl<SDNode *> &NewNodes) const { |
1290 | return false; |
1291 | } |
1292 | |
1293 | /// Returns the opcode of the would be new |
1294 | /// instruction after load / store are unfolded from an instruction of the |
1295 | /// specified opcode. It returns zero if the specified unfolding is not |
1296 | /// possible. If LoadRegIndex is non-null, it is filled in with the operand |
1297 | /// index of the operand which will hold the register holding the loaded |
1298 | /// value. |
1299 | virtual unsigned |
1300 | getOpcodeAfterMemoryUnfold(unsigned Opc, bool UnfoldLoad, bool UnfoldStore, |
1301 | unsigned *LoadRegIndex = nullptr) const { |
1302 | return 0; |
1303 | } |
1304 | |
1305 | /// This is used by the pre-regalloc scheduler to determine if two loads are |
1306 | /// loading from the same base address. It should only return true if the base |
1307 | /// pointers are the same and the only differences between the two addresses |
1308 | /// are the offset. It also returns the offsets by reference. |
1309 | virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, |
1310 | int64_t &Offset1, |
1311 | int64_t &Offset2) const { |
1312 | return false; |
1313 | } |
1314 | |
1315 | /// This is a used by the pre-regalloc scheduler to determine (in conjunction |
1316 | /// with areLoadsFromSameBasePtr) if two loads should be scheduled together. |
1317 | /// On some targets if two loads are loading from |
1318 | /// addresses in the same cache line, it's better if they are scheduled |
1319 | /// together. This function takes two integers that represent the load offsets |
1320 | /// from the common base address. It returns true if it decides it's desirable |
1321 | /// to schedule the two loads together. "NumLoads" is the number of loads that |
1322 | /// have already been scheduled after Load1. |
1323 | virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2, |
1324 | int64_t Offset1, int64_t Offset2, |
1325 | unsigned NumLoads) const { |
1326 | return false; |
1327 | } |
1328 | |
1329 | /// Get the base operand and byte offset of an instruction that reads/writes |
1330 | /// memory. This is a convenience function for callers that are only prepared |
1331 | /// to handle a single base operand. |
1332 | bool getMemOperandWithOffset(const MachineInstr &MI, |
1333 | const MachineOperand *&BaseOp, int64_t &Offset, |
1334 | bool &OffsetIsScalable, |
1335 | const TargetRegisterInfo *TRI) const; |
1336 | |
1337 | /// Get zero or more base operands and the byte offset of an instruction that |
1338 | /// reads/writes memory. Note that there may be zero base operands if the |
1339 | /// instruction accesses a constant address. |
1340 | /// It returns false if MI does not read/write memory. |
1341 | /// It returns false if base operands and offset could not be determined. |
1342 | /// It is not guaranteed to always recognize base operands and offsets in all |
1343 | /// cases. |
1344 | virtual bool getMemOperandsWithOffsetWidth( |
1345 | const MachineInstr &MI, SmallVectorImpl<const MachineOperand *> &BaseOps, |
1346 | int64_t &Offset, bool &OffsetIsScalable, unsigned &Width, |
1347 | const TargetRegisterInfo *TRI) const { |
1348 | return false; |
1349 | } |
1350 | |
1351 | /// Return true if the instruction contains a base register and offset. If |
1352 | /// true, the function also sets the operand position in the instruction |
1353 | /// for the base register and offset. |
1354 | virtual bool getBaseAndOffsetPosition(const MachineInstr &MI, |
1355 | unsigned &BasePos, |
1356 | unsigned &OffsetPos) const { |
1357 | return false; |
1358 | } |
1359 | |
1360 | /// Target dependent implementation to get the values constituting the address |
1361 | /// MachineInstr that is accessing memory. These values are returned as a |
1362 | /// struct ExtAddrMode which contains all relevant information to make up the |
1363 | /// address. |
1364 | virtual Optional<ExtAddrMode> |
1365 | getAddrModeFromMemoryOp(const MachineInstr &MemI, |
1366 | const TargetRegisterInfo *TRI) const { |
1367 | return None; |
1368 | } |
1369 | |
1370 | /// Returns true if MI's Def is NullValueReg, and the MI |
1371 | /// does not change the Zero value. i.e. cases such as rax = shr rax, X where |
1372 | /// NullValueReg = rax. Note that if the NullValueReg is non-zero, this |
1373 | /// function can return true even if becomes zero. Specifically cases such as |
1374 | /// NullValueReg = shl NullValueReg, 63. |
1375 | virtual bool preservesZeroValueInReg(const MachineInstr *MI, |
1376 | const Register NullValueReg, |
1377 | const TargetRegisterInfo *TRI) const { |
1378 | return false; |
1379 | } |
1380 | |
1381 | /// If the instruction is an increment of a constant value, return the amount. |
1382 | virtual bool getIncrementValue(const MachineInstr &MI, int &Value) const { |
1383 | return false; |
1384 | } |
1385 | |
1386 | /// Returns true if the two given memory operations should be scheduled |
1387 | /// adjacent. Note that you have to add: |
1388 | /// DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI)); |
1389 | /// or |
1390 | /// DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI)); |
1391 | /// to TargetPassConfig::createMachineScheduler() to have an effect. |
1392 | /// |
1393 | /// \p BaseOps1 and \p BaseOps2 are memory operands of two memory operations. |
1394 | /// \p NumLoads is the number of loads that will be in the cluster if this |
1395 | /// hook returns true. |
1396 | /// \p NumBytes is the number of bytes that will be loaded from all the |
1397 | /// clustered loads if this hook returns true. |
1398 | virtual bool shouldClusterMemOps(ArrayRef<const MachineOperand *> BaseOps1, |
1399 | ArrayRef<const MachineOperand *> BaseOps2, |
1400 | unsigned NumLoads, unsigned NumBytes) const { |
1401 | llvm_unreachable("target did not implement shouldClusterMemOps()")__builtin_unreachable(); |
1402 | } |
1403 | |
1404 | /// Reverses the branch condition of the specified condition list, |
1405 | /// returning false on success and true if it cannot be reversed. |
1406 | virtual bool |
1407 | reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const { |
1408 | return true; |
1409 | } |
1410 | |
1411 | /// Insert a noop into the instruction stream at the specified point. |
1412 | virtual void insertNoop(MachineBasicBlock &MBB, |
1413 | MachineBasicBlock::iterator MI) const; |
1414 | |
1415 | /// Insert noops into the instruction stream at the specified point. |
1416 | virtual void insertNoops(MachineBasicBlock &MBB, |
1417 | MachineBasicBlock::iterator MI, |
1418 | unsigned Quantity) const; |
1419 | |
1420 | /// Return the noop instruction to use for a noop. |
1421 | virtual MCInst getNop() const; |
1422 | |
1423 | /// Return true for post-incremented instructions. |
1424 | virtual bool isPostIncrement(const MachineInstr &MI) const { return false; } |
1425 | |
1426 | /// Returns true if the instruction is already predicated. |
1427 | virtual bool isPredicated(const MachineInstr &MI) const { return false; } |
1428 | |
1429 | // Returns a MIRPrinter comment for this machine operand. |
1430 | virtual std::string |
1431 | createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op, |
1432 | unsigned OpIdx, const TargetRegisterInfo *TRI) const; |
1433 | |
1434 | /// Returns true if the instruction is a |
1435 | /// terminator instruction that has not been predicated. |
1436 | bool isUnpredicatedTerminator(const MachineInstr &MI) const; |
1437 | |
1438 | /// Returns true if MI is an unconditional tail call. |
1439 | virtual bool isUnconditionalTailCall(const MachineInstr &MI) const { |
1440 | return false; |
1441 | } |
1442 | |
1443 | /// Returns true if the tail call can be made conditional on BranchCond. |
1444 | virtual bool canMakeTailCallConditional(SmallVectorImpl<MachineOperand> &Cond, |
1445 | const MachineInstr &TailCall) const { |
1446 | return false; |
1447 | } |
1448 | |
1449 | /// Replace the conditional branch in MBB with a conditional tail call. |
1450 | virtual void replaceBranchWithTailCall(MachineBasicBlock &MBB, |
1451 | SmallVectorImpl<MachineOperand> &Cond, |
1452 | const MachineInstr &TailCall) const { |
1453 | llvm_unreachable("Target didn't implement replaceBranchWithTailCall!")__builtin_unreachable(); |
1454 | } |
1455 | |
1456 | /// Convert the instruction into a predicated instruction. |
1457 | /// It returns true if the operation was successful. |
1458 | virtual bool PredicateInstruction(MachineInstr &MI, |
1459 | ArrayRef<MachineOperand> Pred) const; |
1460 | |
1461 | /// Returns true if the first specified predicate |
1462 | /// subsumes the second, e.g. GE subsumes GT. |
1463 | virtual bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1, |
1464 | ArrayRef<MachineOperand> Pred2) const { |
1465 | return false; |
1466 | } |
1467 | |
1468 | /// If the specified instruction defines any predicate |
1469 | /// or condition code register(s) used for predication, returns true as well |
1470 | /// as the definition predicate(s) by reference. |
1471 | /// SkipDead should be set to false at any point that dead |
1472 | /// predicate instructions should be considered as being defined. |
1473 | /// A dead predicate instruction is one that is guaranteed to be removed |
1474 | /// after a call to PredicateInstruction. |
1475 | virtual bool ClobbersPredicate(MachineInstr &MI, |
1476 | std::vector<MachineOperand> &Pred, |
1477 | bool SkipDead) const { |
1478 | return false; |
1479 | } |
1480 | |
1481 | /// Return true if the specified instruction can be predicated. |
1482 | /// By default, this returns true for every instruction with a |
1483 | /// PredicateOperand. |
1484 | virtual bool isPredicable(const MachineInstr &MI) const { |
1485 | return MI.getDesc().isPredicable(); |
1486 | } |
1487 | |
1488 | /// Return true if it's safe to move a machine |
1489 | /// instruction that defines the specified register class. |
1490 | virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const { |
1491 | return true; |
1492 | } |
1493 | |
1494 | /// Test if the given instruction should be considered a scheduling boundary. |
1495 | /// This primarily includes labels and terminators. |
1496 | virtual bool isSchedulingBoundary(const MachineInstr &MI, |
1497 | const MachineBasicBlock *MBB, |
1498 | const MachineFunction &MF) const; |
1499 | |
1500 | /// Measure the specified inline asm to determine an approximation of its |
1501 | /// length. |
1502 | virtual unsigned getInlineAsmLength( |
1503 | const char *Str, const MCAsmInfo &MAI, |
1504 | const TargetSubtargetInfo *STI = nullptr) const; |
1505 | |
1506 | /// Allocate and return a hazard recognizer to use for this target when |
1507 | /// scheduling the machine instructions before register allocation. |
1508 | virtual ScheduleHazardRecognizer * |
1509 | CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI, |
1510 | const ScheduleDAG *DAG) const; |
1511 | |
1512 | /// Allocate and return a hazard recognizer to use for this target when |
1513 | /// scheduling the machine instructions before register allocation. |
1514 | virtual ScheduleHazardRecognizer * |
1515 | CreateTargetMIHazardRecognizer(const InstrItineraryData *, |
1516 | const ScheduleDAGMI *DAG) const; |
1517 | |
1518 | /// Allocate and return a hazard recognizer to use for this target when |
1519 | /// scheduling the machine instructions after register allocation. |
1520 | virtual ScheduleHazardRecognizer * |
1521 | CreateTargetPostRAHazardRecognizer(const InstrItineraryData *, |
1522 | const ScheduleDAG *DAG) const; |
1523 | |
1524 | /// Allocate and return a hazard recognizer to use for by non-scheduling |
1525 | /// passes. |
1526 | virtual ScheduleHazardRecognizer * |
1527 | CreateTargetPostRAHazardRecognizer(const MachineFunction &MF) const { |
1528 | return nullptr; |
1529 | } |
1530 | |
1531 | /// Provide a global flag for disabling the PreRA hazard recognizer that |
1532 | /// targets may choose to honor. |
1533 | bool usePreRAHazardRecognizer() const; |
1534 | |
1535 | /// For a comparison instruction, return the source registers |
1536 | /// in SrcReg and SrcReg2 if having two register operands, and the value it |
1537 | /// compares against in CmpValue. Return true if the comparison instruction |
1538 | /// can be analyzed. |
1539 | virtual bool analyzeCompare(const MachineInstr &MI, Register &SrcReg, |
1540 | Register &SrcReg2, int &Mask, int &Value) const { |
1541 | return false; |
1542 | } |
1543 | |
1544 | /// See if the comparison instruction can be converted |
1545 | /// into something more efficient. E.g., on ARM most instructions can set the |
1546 | /// flags register, obviating the need for a separate CMP. |
1547 | virtual bool optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, |
1548 | Register SrcReg2, int Mask, int Value, |
1549 | const MachineRegisterInfo *MRI) const { |
1550 | return false; |
1551 | } |
1552 | virtual bool optimizeCondBranch(MachineInstr &MI) const { return false; } |
1553 | |
1554 | /// Try to remove the load by folding it to a register operand at the use. |
1555 | /// We fold the load instructions if and only if the |
1556 | /// def and use are in the same BB. We only look at one load and see |
1557 | /// whether it can be folded into MI. FoldAsLoadDefReg is the virtual register |
1558 | /// defined by the load we are trying to fold. DefMI returns the machine |
1559 | /// instruction that defines FoldAsLoadDefReg, and the function returns |
1560 | /// the machine instruction generated due to folding. |
1561 | virtual MachineInstr *optimizeLoadInstr(MachineInstr &MI, |
1562 | const MachineRegisterInfo *MRI, |
1563 | Register &FoldAsLoadDefReg, |
1564 | MachineInstr *&DefMI) const { |
1565 | return nullptr; |
1566 | } |
1567 | |
1568 | /// 'Reg' is known to be defined by a move immediate instruction, |
1569 | /// try to fold the immediate into the use instruction. |
1570 | /// If MRI->hasOneNonDBGUse(Reg) is true, and this function returns true, |
1571 | /// then the caller may assume that DefMI has been erased from its parent |
1572 | /// block. The caller may assume that it will not be erased by this |
1573 | /// function otherwise. |
1574 | virtual bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, |
1575 | Register Reg, MachineRegisterInfo *MRI) const { |
1576 | return false; |
1577 | } |
1578 | |
1579 | /// Return the number of u-operations the given machine |
1580 | /// instruction will be decoded to on the target cpu. The itinerary's |
1581 | /// IssueWidth is the number of microops that can be dispatched each |
1582 | /// cycle. An instruction with zero microops takes no dispatch resources. |
1583 | virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData, |
1584 | const MachineInstr &MI) const; |
1585 | |
1586 | /// Return true for pseudo instructions that don't consume any |
1587 | /// machine resources in their current form. These are common cases that the |
1588 | /// scheduler should consider free, rather than conservatively handling them |
1589 | /// as instructions with no itinerary. |
1590 | bool isZeroCost(unsigned Opcode) const { |
1591 | return Opcode <= TargetOpcode::COPY; |
1592 | } |
1593 | |
1594 | virtual int getOperandLatency(const InstrItineraryData *ItinData, |
1595 | SDNode *DefNode, unsigned DefIdx, |
1596 | SDNode *UseNode, unsigned UseIdx) const; |
1597 | |
1598 | /// Compute and return the use operand latency of a given pair of def and use. |
1599 | /// In most cases, the static scheduling itinerary was enough to determine the |
1600 | /// operand latency. But it may not be possible for instructions with variable |
1601 | /// number of defs / uses. |
1602 | /// |
1603 | /// This is a raw interface to the itinerary that may be directly overridden |
1604 | /// by a target. Use computeOperandLatency to get the best estimate of |
1605 | /// latency. |
1606 | virtual int getOperandLatency(const InstrItineraryData *ItinData, |
1607 | const MachineInstr &DefMI, unsigned DefIdx, |
1608 | const MachineInstr &UseMI, |
1609 | unsigned UseIdx) const; |
1610 | |
1611 | /// Compute the instruction latency of a given instruction. |
1612 | /// If the instruction has higher cost when predicated, it's returned via |
1613 | /// PredCost. |
1614 | virtual unsigned getInstrLatency(const InstrItineraryData *ItinData, |
1615 | const MachineInstr &MI, |
1616 | unsigned *PredCost = nullptr) const; |
1617 | |
1618 | virtual unsigned getPredicationCost(const MachineInstr &MI) const; |
1619 | |
1620 | virtual int getInstrLatency(const InstrItineraryData *ItinData, |
1621 | SDNode *Node) const; |
1622 | |
1623 | /// Return the default expected latency for a def based on its opcode. |
1624 | unsigned defaultDefLatency(const MCSchedModel &SchedModel, |
1625 | const MachineInstr &DefMI) const; |
1626 | |
1627 | int computeDefOperandLatency(const InstrItineraryData *ItinData, |
1628 | const MachineInstr &DefMI) const; |
1629 | |
1630 | /// Return true if this opcode has high latency to its result. |
1631 | virtual bool isHighLatencyDef(int opc) const { return false; } |
1632 | |
1633 | /// Compute operand latency between a def of 'Reg' |
1634 | /// and a use in the current loop. Return true if the target considered |
1635 | /// it 'high'. This is used by optimization passes such as machine LICM to |
1636 | /// determine whether it makes sense to hoist an instruction out even in a |
1637 | /// high register pressure situation. |
1638 | virtual bool hasHighOperandLatency(const TargetSchedModel &SchedModel, |
1639 | const MachineRegisterInfo *MRI, |
1640 | const MachineInstr &DefMI, unsigned DefIdx, |
1641 | const MachineInstr &UseMI, |
1642 | unsigned UseIdx) const { |
1643 | return false; |
1644 | } |
1645 | |
1646 | /// Compute operand latency of a def of 'Reg'. Return true |
1647 | /// if the target considered it 'low'. |
1648 | virtual bool hasLowDefLatency(const TargetSchedModel &SchedModel, |
1649 | const MachineInstr &DefMI, |
1650 | unsigned DefIdx) const; |
1651 | |
1652 | /// Perform target-specific instruction verification. |
1653 | virtual bool verifyInstruction(const MachineInstr &MI, |
1654 | StringRef &ErrInfo) const { |
1655 | return true; |
1656 | } |
1657 | |
1658 | /// Return the current execution domain and bit mask of |
1659 | /// possible domains for instruction. |
1660 | /// |
1661 | /// Some micro-architectures have multiple execution domains, and multiple |
1662 | /// opcodes that perform the same operation in different domains. For |
1663 | /// example, the x86 architecture provides the por, orps, and orpd |
1664 | /// instructions that all do the same thing. There is a latency penalty if a |
1665 | /// register is written in one domain and read in another. |
1666 | /// |
1667 | /// This function returns a pair (domain, mask) containing the execution |
1668 | /// domain of MI, and a bit mask of possible domains. The setExecutionDomain |
1669 | /// function can be used to change the opcode to one of the domains in the |
1670 | /// bit mask. Instructions whose execution domain can't be changed should |
1671 | /// return a 0 mask. |
1672 | /// |
1673 | /// The execution domain numbers don't have any special meaning except domain |
1674 | /// 0 is used for instructions that are not associated with any interesting |
1675 | /// execution domain. |
1676 | /// |
1677 | virtual std::pair<uint16_t, uint16_t> |
1678 | getExecutionDomain(const MachineInstr &MI) const { |
1679 | return std::make_pair(0, 0); |
1680 | } |
1681 | |
1682 | /// Change the opcode of MI to execute in Domain. |
1683 | /// |
1684 | /// The bit (1 << Domain) must be set in the mask returned from |
1685 | /// getExecutionDomain(MI). |
1686 | virtual void setExecutionDomain(MachineInstr &MI, unsigned Domain) const {} |
1687 | |
1688 | /// Returns the preferred minimum clearance |
1689 | /// before an instruction with an unwanted partial register update. |
1690 | /// |
1691 | /// Some instructions only write part of a register, and implicitly need to |
1692 | /// read the other parts of the register. This may cause unwanted stalls |
1693 | /// preventing otherwise unrelated instructions from executing in parallel in |
1694 | /// an out-of-order CPU. |
1695 | /// |
1696 | /// For example, the x86 instruction cvtsi2ss writes its result to bits |
1697 | /// [31:0] of the destination xmm register. Bits [127:32] are unaffected, so |
1698 | /// the instruction needs to wait for the old value of the register to become |
1699 | /// available: |
1700 | /// |
1701 | /// addps %xmm1, %xmm0 |
1702 | /// movaps %xmm0, (%rax) |
1703 | /// cvtsi2ss %rbx, %xmm0 |
1704 | /// |
1705 | /// In the code above, the cvtsi2ss instruction needs to wait for the addps |
1706 | /// instruction before it can issue, even though the high bits of %xmm0 |
1707 | /// probably aren't needed. |
1708 | /// |
1709 | /// This hook returns the preferred clearance before MI, measured in |
1710 | /// instructions. Other defs of MI's operand OpNum are avoided in the last N |
1711 | /// instructions before MI. It should only return a positive value for |
1712 | /// unwanted dependencies. If the old bits of the defined register have |
1713 | /// useful values, or if MI is determined to otherwise read the dependency, |
1714 | /// the hook should return 0. |
1715 | /// |
1716 | /// The unwanted dependency may be handled by: |
1717 | /// |
1718 | /// 1. Allocating the same register for an MI def and use. That makes the |
1719 | /// unwanted dependency identical to a required dependency. |
1720 | /// |
1721 | /// 2. Allocating a register for the def that has no defs in the previous N |
1722 | /// instructions. |
1723 | /// |
1724 | /// 3. Calling breakPartialRegDependency() with the same arguments. This |
1725 | /// allows the target to insert a dependency breaking instruction. |
1726 | /// |
1727 | virtual unsigned |
1728 | getPartialRegUpdateClearance(const MachineInstr &MI, unsigned OpNum, |
1729 | const TargetRegisterInfo *TRI) const { |
1730 | // The default implementation returns 0 for no partial register dependency. |
1731 | return 0; |
1732 | } |
1733 | |
1734 | /// Return the minimum clearance before an instruction that reads an |
1735 | /// unused register. |
1736 | /// |
1737 | /// For example, AVX instructions may copy part of a register operand into |
1738 | /// the unused high bits of the destination register. |
1739 | /// |
1740 | /// vcvtsi2sdq %rax, undef %xmm0, %xmm14 |
1741 | /// |
1742 | /// In the code above, vcvtsi2sdq copies %xmm0[127:64] into %xmm14 creating a |
1743 | /// false dependence on any previous write to %xmm0. |
1744 | /// |
1745 | /// This hook works similarly to getPartialRegUpdateClearance, except that it |
1746 | /// does not take an operand index. Instead sets \p OpNum to the index of the |
1747 | /// unused register. |
1748 | virtual unsigned getUndefRegClearance(const MachineInstr &MI, unsigned OpNum, |
1749 | const TargetRegisterInfo *TRI) const { |
1750 | // The default implementation returns 0 for no undef register dependency. |
1751 | return 0; |
1752 | } |
1753 | |
1754 | /// Insert a dependency-breaking instruction |
1755 | /// before MI to eliminate an unwanted dependency on OpNum. |
1756 | /// |
1757 | /// If it wasn't possible to avoid a def in the last N instructions before MI |
1758 | /// (see getPartialRegUpdateClearance), this hook will be called to break the |
1759 | /// unwanted dependency. |
1760 | /// |
1761 | /// On x86, an xorps instruction can be used as a dependency breaker: |
1762 | /// |
1763 | /// addps %xmm1, %xmm0 |
1764 | /// movaps %xmm0, (%rax) |
1765 | /// xorps %xmm0, %xmm0 |
1766 | /// cvtsi2ss %rbx, %xmm0 |
1767 | /// |
1768 | /// An <imp-kill> operand should be added to MI if an instruction was |
1769 | /// inserted. This ties the instructions together in the post-ra scheduler. |
1770 | /// |
1771 | virtual void breakPartialRegDependency(MachineInstr &MI, unsigned OpNum, |
1772 | const TargetRegisterInfo *TRI) const {} |
1773 | |
1774 | /// Create machine specific model for scheduling. |
1775 | virtual DFAPacketizer * |
1776 | CreateTargetScheduleState(const TargetSubtargetInfo &) const { |
1777 | return nullptr; |
1778 | } |
1779 | |
1780 | /// Sometimes, it is possible for the target |
1781 | /// to tell, even without aliasing information, that two MIs access different |
1782 | /// memory addresses. This function returns true if two MIs access different |
1783 | /// memory addresses and false otherwise. |
1784 | /// |
1785 | /// Assumes any physical registers used to compute addresses have the same |
1786 | /// value for both instructions. (This is the most useful assumption for |
1787 | /// post-RA scheduling.) |
1788 | /// |
1789 | /// See also MachineInstr::mayAlias, which is implemented on top of this |
1790 | /// function. |
1791 | virtual bool |
1792 | areMemAccessesTriviallyDisjoint(const MachineInstr &MIa, |
1793 | const MachineInstr &MIb) const { |
1794 | assert(MIa.mayLoadOrStore() &&((void)0) |
1795 | "MIa must load from or modify a memory location")((void)0); |
1796 | assert(MIb.mayLoadOrStore() &&((void)0) |
1797 | "MIb must load from or modify a memory location")((void)0); |
1798 | return false; |
1799 | } |
1800 | |
1801 | /// Return the value to use for the MachineCSE's LookAheadLimit, |
1802 | /// which is a heuristic used for CSE'ing phys reg defs. |
1803 | virtual unsigned getMachineCSELookAheadLimit() const { |
1804 | // The default lookahead is small to prevent unprofitable quadratic |
1805 | // behavior. |
1806 | return 5; |
1807 | } |
1808 | |
1809 | /// Return the maximal number of alias checks on memory operands. For |
1810 | /// instructions with more than one memory operands, the alias check on a |
1811 | /// single MachineInstr pair has quadratic overhead and results in |
1812 | /// unacceptable performance in the worst case. The limit here is to clamp |
1813 | /// that maximal checks performed. Usually, that's the product of memory |
1814 | /// operand numbers from that pair of MachineInstr to be checked. For |
1815 | /// instance, with two MachineInstrs with 4 and 5 memory operands |
1816 | /// correspondingly, a total of 20 checks are required. With this limit set to |
1817 | /// 16, their alias check is skipped. We choose to limit the product instead |
1818 | /// of the individual instruction as targets may have special MachineInstrs |
1819 | /// with a considerably high number of memory operands, such as `ldm` in ARM. |
1820 | /// Setting this limit per MachineInstr would result in either too high |
1821 | /// overhead or too rigid restriction. |
1822 | virtual unsigned getMemOperandAACheckLimit() const { return 16; } |
1823 | |
1824 | /// Return an array that contains the ids of the target indices (used for the |
1825 | /// TargetIndex machine operand) and their names. |
1826 | /// |
1827 | /// MIR Serialization is able to serialize only the target indices that are |
1828 | /// defined by this method. |
1829 | virtual ArrayRef<std::pair<int, const char *>> |
1830 | getSerializableTargetIndices() const { |
1831 | return None; |
1832 | } |
1833 | |
1834 | /// Decompose the machine operand's target flags into two values - the direct |
1835 | /// target flag value and any of bit flags that are applied. |
1836 | virtual std::pair<unsigned, unsigned> |
1837 | decomposeMachineOperandsTargetFlags(unsigned /*TF*/) const { |
1838 | return std::make_pair(0u, 0u); |
1839 | } |
1840 | |
1841 | /// Return an array that contains the direct target flag values and their |
1842 | /// names. |
1843 | /// |
1844 | /// MIR Serialization is able to serialize only the target flags that are |
1845 | /// defined by this method. |
1846 | virtual ArrayRef<std::pair<unsigned, const char *>> |
1847 | getSerializableDirectMachineOperandTargetFlags() const { |
1848 | return None; |
1849 | } |
1850 | |
1851 | /// Return an array that contains the bitmask target flag values and their |
1852 | /// names. |
1853 | /// |
1854 | /// MIR Serialization is able to serialize only the target flags that are |
1855 | /// defined by this method. |
1856 | virtual ArrayRef<std::pair<unsigned, const char *>> |
1857 | getSerializableBitmaskMachineOperandTargetFlags() const { |
1858 | return None; |
1859 | } |
1860 | |
1861 | /// Return an array that contains the MMO target flag values and their |
1862 | /// names. |
1863 | /// |
1864 | /// MIR Serialization is able to serialize only the MMO target flags that are |
1865 | /// defined by this method. |
1866 | virtual ArrayRef<std::pair<MachineMemOperand::Flags, const char *>> |
1867 | getSerializableMachineMemOperandTargetFlags() const { |
1868 | return None; |
1869 | } |
1870 | |
1871 | /// Determines whether \p Inst is a tail call instruction. Override this |
1872 | /// method on targets that do not properly set MCID::Return and MCID::Call on |
1873 | /// tail call instructions." |
1874 | virtual bool isTailCall(const MachineInstr &Inst) const { |
1875 | return Inst.isReturn() && Inst.isCall(); |
1876 | } |
1877 | |
1878 | /// True if the instruction is bound to the top of its basic block and no |
1879 | /// other instructions shall be inserted before it. This can be implemented |
1880 | /// to prevent register allocator to insert spills before such instructions. |
1881 | virtual bool isBasicBlockPrologue(const MachineInstr &MI) const { |
1882 | return false; |
1883 | } |
1884 | |
1885 | /// During PHI eleimination lets target to make necessary checks and |
1886 | /// insert the copy to the PHI destination register in a target specific |
1887 | /// manner. |
1888 | virtual MachineInstr *createPHIDestinationCopy( |
1889 | MachineBasicBlock &MBB, MachineBasicBlock::iterator InsPt, |
1890 | const DebugLoc &DL, Register Src, Register Dst) const { |
1891 | return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst) |
1892 | .addReg(Src); |
1893 | } |
1894 | |
1895 | /// During PHI eleimination lets target to make necessary checks and |
1896 | /// insert the copy to the PHI destination register in a target specific |
1897 | /// manner. |
1898 | virtual MachineInstr *createPHISourceCopy(MachineBasicBlock &MBB, |
1899 | MachineBasicBlock::iterator InsPt, |
1900 | const DebugLoc &DL, Register Src, |
1901 | unsigned SrcSubReg, |
1902 | Register Dst) const { |
1903 | return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst) |
1904 | .addReg(Src, 0, SrcSubReg); |
1905 | } |
1906 | |
1907 | /// Returns a \p outliner::OutlinedFunction struct containing target-specific |
1908 | /// information for a set of outlining candidates. |
1909 | virtual outliner::OutlinedFunction getOutliningCandidateInfo( |
1910 | std::vector<outliner::Candidate> &RepeatedSequenceLocs) const { |
1911 | llvm_unreachable(__builtin_unreachable() |
1912 | "Target didn't implement TargetInstrInfo::getOutliningCandidateInfo!")__builtin_unreachable(); |
1913 | } |
1914 | |
1915 | /// Returns how or if \p MI should be outlined. |
1916 | virtual outliner::InstrType |
1917 | getOutliningType(MachineBasicBlock::iterator &MIT, unsigned Flags) const { |
1918 | llvm_unreachable(__builtin_unreachable() |
1919 | "Target didn't implement TargetInstrInfo::getOutliningType!")__builtin_unreachable(); |
1920 | } |
1921 | |
1922 | /// Optional target hook that returns true if \p MBB is safe to outline from, |
1923 | /// and returns any target-specific information in \p Flags. |
1924 | virtual bool isMBBSafeToOutlineFrom(MachineBasicBlock &MBB, |
1925 | unsigned &Flags) const { |
1926 | return true; |
1927 | } |
1928 | |
1929 | /// Insert a custom frame for outlined functions. |
1930 | virtual void buildOutlinedFrame(MachineBasicBlock &MBB, MachineFunction &MF, |
1931 | const outliner::OutlinedFunction &OF) const { |
1932 | llvm_unreachable(__builtin_unreachable() |
1933 | "Target didn't implement TargetInstrInfo::buildOutlinedFrame!")__builtin_unreachable(); |
1934 | } |
1935 | |
1936 | /// Insert a call to an outlined function into the program. |
1937 | /// Returns an iterator to the spot where we inserted the call. This must be |
1938 | /// implemented by the target. |
1939 | virtual MachineBasicBlock::iterator |
1940 | insertOutlinedCall(Module &M, MachineBasicBlock &MBB, |
1941 | MachineBasicBlock::iterator &It, MachineFunction &MF, |
1942 | const outliner::Candidate &C) const { |
1943 | llvm_unreachable(__builtin_unreachable() |
1944 | "Target didn't implement TargetInstrInfo::insertOutlinedCall!")__builtin_unreachable(); |
1945 | } |
1946 | |
1947 | /// Return true if the function can safely be outlined from. |
1948 | /// A function \p MF is considered safe for outlining if an outlined function |
1949 | /// produced from instructions in F will produce a program which produces the |
1950 | /// same output for any set of given inputs. |
1951 | virtual bool isFunctionSafeToOutlineFrom(MachineFunction &MF, |
1952 | bool OutlineFromLinkOnceODRs) const { |
1953 | llvm_unreachable("Target didn't implement "__builtin_unreachable() |
1954 | "TargetInstrInfo::isFunctionSafeToOutlineFrom!")__builtin_unreachable(); |
1955 | } |
1956 | |
1957 | /// Return true if the function should be outlined from by default. |
1958 | virtual bool shouldOutlineFromFunctionByDefault(MachineFunction &MF) const { |
1959 | return false; |
1960 | } |
1961 | |
1962 | /// Produce the expression describing the \p MI loading a value into |
1963 | /// the physical register \p Reg. This hook should only be used with |
1964 | /// \p MIs belonging to VReg-less functions. |
1965 | virtual Optional<ParamLoadedValue> describeLoadedValue(const MachineInstr &MI, |
1966 | Register Reg) const; |
1967 | |
1968 | /// Given the generic extension instruction \p ExtMI, returns true if this |
1969 | /// extension is a likely candidate for being folded into an another |
1970 | /// instruction. |
1971 | virtual bool isExtendLikelyToBeFolded(MachineInstr &ExtMI, |
1972 | MachineRegisterInfo &MRI) const { |
1973 | return false; |
1974 | } |
1975 | |
1976 | /// Return MIR formatter to format/parse MIR operands. Target can override |
1977 | /// this virtual function and return target specific MIR formatter. |
1978 | virtual const MIRFormatter *getMIRFormatter() const { |
1979 | if (!Formatter.get()) |
1980 | Formatter = std::make_unique<MIRFormatter>(); |
1981 | return Formatter.get(); |
1982 | } |
1983 | |
1984 | /// Returns the target-specific default value for tail duplication. |
1985 | /// This value will be used if the tail-dup-placement-threshold argument is |
1986 | /// not provided. |
1987 | virtual unsigned getTailDuplicateSize(CodeGenOpt::Level OptLevel) const { |
1988 | return OptLevel >= CodeGenOpt::Aggressive ? 4 : 2; |
1989 | } |
1990 | |
1991 | /// Returns the callee operand from the given \p MI. |
1992 | virtual const MachineOperand &getCalleeOperand(const MachineInstr &MI) const { |
1993 | return MI.getOperand(0); |
1994 | } |
1995 | |
1996 | private: |
1997 | mutable std::unique_ptr<MIRFormatter> Formatter; |
1998 | unsigned CallFrameSetupOpcode, CallFrameDestroyOpcode; |
1999 | unsigned CatchRetOpcode; |
2000 | unsigned ReturnOpcode; |
2001 | }; |
2002 | |
2003 | /// Provide DenseMapInfo for TargetInstrInfo::RegSubRegPair. |
2004 | template <> struct DenseMapInfo<TargetInstrInfo::RegSubRegPair> { |
2005 | using RegInfo = DenseMapInfo<unsigned>; |
2006 | |
2007 | static inline TargetInstrInfo::RegSubRegPair getEmptyKey() { |
2008 | return TargetInstrInfo::RegSubRegPair(RegInfo::getEmptyKey(), |
2009 | RegInfo::getEmptyKey()); |
2010 | } |
2011 | |
2012 | static inline TargetInstrInfo::RegSubRegPair getTombstoneKey() { |
2013 | return TargetInstrInfo::RegSubRegPair(RegInfo::getTombstoneKey(), |
2014 | RegInfo::getTombstoneKey()); |
2015 | } |
2016 | |
2017 | /// Reuse getHashValue implementation from |
2018 | /// std::pair<unsigned, unsigned>. |
2019 | static unsigned getHashValue(const TargetInstrInfo::RegSubRegPair &Val) { |
2020 | std::pair<unsigned, unsigned> PairVal = std::make_pair(Val.Reg, Val.SubReg); |
2021 | return DenseMapInfo<std::pair<unsigned, unsigned>>::getHashValue(PairVal); |
2022 | } |
2023 | |
2024 | static bool isEqual(const TargetInstrInfo::RegSubRegPair &LHS, |
2025 | const TargetInstrInfo::RegSubRegPair &RHS) { |
2026 | return RegInfo::isEqual(LHS.Reg, RHS.Reg) && |
2027 | RegInfo::isEqual(LHS.SubReg, RHS.SubReg); |
2028 | } |
2029 | }; |
2030 | |
2031 | } // end namespace llvm |
2032 | |
2033 | #endif // LLVM_CODEGEN_TARGETINSTRINFO_H |
1 | //===-- llvm/CodeGen/Register.h ---------------------------------*- C++ -*-===// |
2 | // |
3 | // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
4 | // See https://llvm.org/LICENSE.txt for license information. |
5 | // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
6 | // |
7 | //===----------------------------------------------------------------------===// |
8 | |
9 | #ifndef LLVM_CODEGEN_REGISTER_H |
10 | #define LLVM_CODEGEN_REGISTER_H |
11 | |
12 | #include "llvm/MC/MCRegister.h" |
13 | #include <cassert> |
14 | |
15 | namespace llvm { |
16 | |
17 | /// Wrapper class representing virtual and physical registers. Should be passed |
18 | /// by value. |
19 | class Register { |
20 | unsigned Reg; |
21 | |
22 | public: |
23 | constexpr Register(unsigned Val = 0): Reg(Val) {} |
24 | constexpr Register(MCRegister Val): Reg(Val) {} |
25 | |
26 | // Register numbers can represent physical registers, virtual registers, and |
27 | // sometimes stack slots. The unsigned values are divided into these ranges: |
28 | // |
29 | // 0 Not a register, can be used as a sentinel. |
30 | // [1;2^30) Physical registers assigned by TableGen. |
31 | // [2^30;2^31) Stack slots. (Rarely used.) |
32 | // [2^31;2^32) Virtual registers assigned by MachineRegisterInfo. |
33 | // |
34 | // Further sentinels can be allocated from the small negative integers. |
35 | // DenseMapInfo<unsigned> uses -1u and -2u. |
36 | static_assert(std::numeric_limits<decltype(Reg)>::max() >= 0xFFFFFFFF, |
37 | "Reg isn't large enough to hold full range."); |
38 | |
39 | /// isStackSlot - Sometimes it is useful the be able to store a non-negative |
40 | /// frame index in a variable that normally holds a register. isStackSlot() |
41 | /// returns true if Reg is in the range used for stack slots. |
42 | /// |
43 | /// FIXME: remove in favor of member. |
44 | static bool isStackSlot(unsigned Reg) { |
45 | return MCRegister::isStackSlot(Reg); |
46 | } |
47 | |
48 | /// Return true if this is a stack slot. |
49 | bool isStack() const { return MCRegister::isStackSlot(Reg); } |
50 | |
51 | /// Compute the frame index from a register value representing a stack slot. |
52 | static int stackSlot2Index(Register Reg) { |
53 | assert(Reg.isStack() && "Not a stack slot")((void)0); |
54 | return int(Reg - MCRegister::FirstStackSlot); |
55 | } |
56 | |
57 | /// Convert a non-negative frame index to a stack slot register value. |
58 | static Register index2StackSlot(int FI) { |
59 | assert(FI >= 0 && "Cannot hold a negative frame index.")((void)0); |
60 | return Register(FI + MCRegister::FirstStackSlot); |
61 | } |
62 | |
63 | /// Return true if the specified register number is in |
64 | /// the physical register namespace. |
65 | static bool isPhysicalRegister(unsigned Reg) { |
66 | return MCRegister::isPhysicalRegister(Reg); |
67 | } |
68 | |
69 | /// Return true if the specified register number is in |
70 | /// the virtual register namespace. |
71 | static bool isVirtualRegister(unsigned Reg) { |
72 | return Reg & MCRegister::VirtualRegFlag && !isStackSlot(Reg); |
73 | } |
74 | |
75 | /// Convert a virtual register number to a 0-based index. |
76 | /// The first virtual register in a function will get the index 0. |
77 | static unsigned virtReg2Index(Register Reg) { |
78 | assert(isVirtualRegister(Reg) && "Not a virtual register")((void)0); |
79 | return Reg & ~MCRegister::VirtualRegFlag; |
80 | } |
81 | |
82 | /// Convert a 0-based index to a virtual register number. |
83 | /// This is the inverse operation of VirtReg2IndexFunctor below. |
84 | static Register index2VirtReg(unsigned Index) { |
85 | assert(Index < (1u << 31) && "Index too large for virtual register range.")((void)0); |
86 | return Index | MCRegister::VirtualRegFlag; |
87 | } |
88 | |
89 | /// Return true if the specified register number is in the virtual register |
90 | /// namespace. |
91 | bool isVirtual() const { |
92 | return isVirtualRegister(Reg); |
93 | } |
94 | |
95 | /// Return true if the specified register number is in the physical register |
96 | /// namespace. |
97 | bool isPhysical() const { |
98 | return isPhysicalRegister(Reg); |
99 | } |
100 | |
101 | /// Convert a virtual register number to a 0-based index. The first virtual |
102 | /// register in a function will get the index 0. |
103 | unsigned virtRegIndex() const { |
104 | return virtReg2Index(Reg); |
105 | } |
106 | |
107 | constexpr operator unsigned() const { |
108 | return Reg; |
109 | } |
110 | |
111 | unsigned id() const { return Reg; } |
112 | |
113 | operator MCRegister() const { |
114 | return MCRegister(Reg); |
115 | } |
116 | |
117 | /// Utility to check-convert this value to a MCRegister. The caller is |
118 | /// expected to have already validated that this Register is, indeed, |
119 | /// physical. |
120 | MCRegister asMCReg() const { |
121 | assert(Reg == MCRegister::NoRegister ||((void)0) |
122 | MCRegister::isPhysicalRegister(Reg))((void)0); |
123 | return MCRegister(Reg); |
124 | } |
125 | |
126 | bool isValid() const { return Reg != MCRegister::NoRegister; } |
127 | |
128 | /// Comparisons between register objects |
129 | bool operator==(const Register &Other) const { return Reg == Other.Reg; } |
130 | bool operator!=(const Register &Other) const { return Reg != Other.Reg; } |
131 | bool operator==(const MCRegister &Other) const { return Reg == Other.id(); } |
132 | bool operator!=(const MCRegister &Other) const { return Reg != Other.id(); } |
133 | |
134 | /// Comparisons against register constants. E.g. |
135 | /// * R == AArch64::WZR |
136 | /// * R == 0 |
137 | /// * R == VirtRegMap::NO_PHYS_REG |
138 | bool operator==(unsigned Other) const { return Reg == Other; } |
139 | bool operator!=(unsigned Other) const { return Reg != Other; } |
140 | bool operator==(int Other) const { return Reg == unsigned(Other); } |
141 | bool operator!=(int Other) const { return Reg != unsigned(Other); } |
142 | // MSVC requires that we explicitly declare these two as well. |
143 | bool operator==(MCPhysReg Other) const { return Reg == unsigned(Other); } |
144 | bool operator!=(MCPhysReg Other) const { return Reg != unsigned(Other); } |
145 | }; |
146 | |
147 | // Provide DenseMapInfo for Register |
148 | template<> struct DenseMapInfo<Register> { |
149 | static inline unsigned getEmptyKey() { |
150 | return DenseMapInfo<unsigned>::getEmptyKey(); |
151 | } |
152 | static inline unsigned getTombstoneKey() { |
153 | return DenseMapInfo<unsigned>::getTombstoneKey(); |
154 | } |
155 | static unsigned getHashValue(const Register &Val) { |
156 | return DenseMapInfo<unsigned>::getHashValue(Val.id()); |
157 | } |
158 | static bool isEqual(const Register &LHS, const Register &RHS) { |
159 | return DenseMapInfo<unsigned>::isEqual(LHS.id(), RHS.id()); |
160 | } |
161 | }; |
162 | |
163 | } |
164 | |
165 | #endif // LLVM_CODEGEN_REGISTER_H |