Bug Summary

File:dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
Warning:line 978, column 3
Value stored to 'value' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name smu7_powertune.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/smu7_powertune.c
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "pp_debug.h"
24#include "hwmgr.h"
25#include "smumgr.h"
26#include "smu7_hwmgr.h"
27#include "smu7_powertune.h"
28#include "smu7_common.h"
29
30#define VOLTAGE_SCALE4 4
31
32static uint32_t DIDTBlock_Info = SQ_IR_MASK0x2 | TCP_IR_MASK0x200 | TD_PCC_MASK0x40000;
33
34static uint32_t Polaris11_DIDTBlock_Info = SQ_PCC_MASK0x4 | TCP_IR_MASK0x200 | TD_PCC_MASK0x40000;
35
36static const struct gpu_pt_config_reg GCCACConfig_Polaris10[] = {
37/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
38 * Offset Mask Shift Value Type
39 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
40 */
41 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x00060013, GPU_CONFIGREG_GC_CAC_IND },
42 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x00860013, GPU_CONFIGREG_GC_CAC_IND },
43 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x01060013, GPU_CONFIGREG_GC_CAC_IND },
44 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x01860013, GPU_CONFIGREG_GC_CAC_IND },
45 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x02060013, GPU_CONFIGREG_GC_CAC_IND },
46 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x02860013, GPU_CONFIGREG_GC_CAC_IND },
47 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x03060013, GPU_CONFIGREG_GC_CAC_IND },
48 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x03860013, GPU_CONFIGREG_GC_CAC_IND },
49 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x04060013, GPU_CONFIGREG_GC_CAC_IND },
50
51 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x000E0013, GPU_CONFIGREG_GC_CAC_IND },
52 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x008E0013, GPU_CONFIGREG_GC_CAC_IND },
53 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x010E0013, GPU_CONFIGREG_GC_CAC_IND },
54 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x018E0013, GPU_CONFIGREG_GC_CAC_IND },
55 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x020E0013, GPU_CONFIGREG_GC_CAC_IND },
56
57 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x00100013, GPU_CONFIGREG_GC_CAC_IND },
58 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x00900013, GPU_CONFIGREG_GC_CAC_IND },
59 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x01100013, GPU_CONFIGREG_GC_CAC_IND },
60 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x01900013, GPU_CONFIGREG_GC_CAC_IND },
61 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x02100013, GPU_CONFIGREG_GC_CAC_IND },
62 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x02900013, GPU_CONFIGREG_GC_CAC_IND },
63
64 { 0xFFFFFFFF }
65};
66
67static const struct gpu_pt_config_reg GCCACConfig_Polaris11[] = {
68/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
69 * Offset Mask Shift Value Type
70 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
71 */
72 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x00060011, GPU_CONFIGREG_GC_CAC_IND },
73 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x00860011, GPU_CONFIGREG_GC_CAC_IND },
74 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x01060011, GPU_CONFIGREG_GC_CAC_IND },
75 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x01860011, GPU_CONFIGREG_GC_CAC_IND },
76 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x02060011, GPU_CONFIGREG_GC_CAC_IND },
77 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x02860011, GPU_CONFIGREG_GC_CAC_IND },
78 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x03060011, GPU_CONFIGREG_GC_CAC_IND },
79 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x03860011, GPU_CONFIGREG_GC_CAC_IND },
80 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x04060011, GPU_CONFIGREG_GC_CAC_IND },
81
82 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x000E0011, GPU_CONFIGREG_GC_CAC_IND },
83 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x008E0011, GPU_CONFIGREG_GC_CAC_IND },
84 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x010E0011, GPU_CONFIGREG_GC_CAC_IND },
85 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x018E0011, GPU_CONFIGREG_GC_CAC_IND },
86 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x020E0011, GPU_CONFIGREG_GC_CAC_IND },
87
88 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x00100011, GPU_CONFIGREG_GC_CAC_IND },
89 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x00900011, GPU_CONFIGREG_GC_CAC_IND },
90 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x01100011, GPU_CONFIGREG_GC_CAC_IND },
91 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x01900011, GPU_CONFIGREG_GC_CAC_IND },
92 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x02100011, GPU_CONFIGREG_GC_CAC_IND },
93 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x02900011, GPU_CONFIGREG_GC_CAC_IND },
94
95 { 0xFFFFFFFF }
96};
97
98static const struct gpu_pt_config_reg DIDTConfig_Polaris10[] = {
99/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
100 * Offset Mask Shift Value Type
101 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
102 */
103 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x0073, GPU_CONFIGREG_DIDT_IND },
104 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x00ab, GPU_CONFIGREG_DIDT_IND },
105 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0084, GPU_CONFIGREG_DIDT_IND },
106 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x005a, GPU_CONFIGREG_DIDT_IND },
107
108 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0067, GPU_CONFIGREG_DIDT_IND },
109 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x0084, GPU_CONFIGREG_DIDT_IND },
110 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0027, GPU_CONFIGREG_DIDT_IND },
111 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0046, GPU_CONFIGREG_DIDT_IND },
112
113 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK0xff, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT0x0, 0x00aa, GPU_CONFIGREG_DIDT_IND },
114 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK0xff00, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT0x8, 0x0000, GPU_CONFIGREG_DIDT_IND },
115 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK0xff0000, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
116 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK0xff000000, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
117
118 { ixDIDT_SQ_CTRL10x1, DIDT_SQ_CTRL1__MIN_POWER_MASK0xffff, DIDT_SQ_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
119 { ixDIDT_SQ_CTRL10x1, DIDT_SQ_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_SQ_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
120
121 { ixDIDT_SQ_CTRL_OCP0x3, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
122 { ixDIDT_SQ_CTRL_OCP0x3, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
123
124 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3853, GPU_CONFIGREG_DIDT_IND },
125 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_0_MASK0xc000, DIDT_SQ_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
126 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x005a, GPU_CONFIGREG_DIDT_IND },
127 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_1_MASK0x4000000, DIDT_SQ_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
128 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
129 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_2_MASK0x80000000, DIDT_SQ_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
130
131 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
132 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007e, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
133 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
134 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x0ebb, GPU_CONFIGREG_DIDT_IND },
135 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
136
137 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
138 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x3853, GPU_CONFIGREG_DIDT_IND },
139 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x3153, GPU_CONFIGREG_DIDT_IND },
140 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
141
142 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
143 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
144 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
145 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
146 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
147 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0010, GPU_CONFIGREG_DIDT_IND },
148 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0010, GPU_CONFIGREG_DIDT_IND },
149 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_SQ_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
150
151 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x000a, GPU_CONFIGREG_DIDT_IND },
152 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x0010, GPU_CONFIGREG_DIDT_IND },
153 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0017, GPU_CONFIGREG_DIDT_IND },
154 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x002f, GPU_CONFIGREG_DIDT_IND },
155
156 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0046, GPU_CONFIGREG_DIDT_IND },
157 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x005d, GPU_CONFIGREG_DIDT_IND },
158 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
159 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
160
161 { ixDIDT_TD_CTRL10x41, DIDT_TD_CTRL1__MIN_POWER_MASK0xffff, DIDT_TD_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
162 { ixDIDT_TD_CTRL10x41, DIDT_TD_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_TD_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
163
164 { ixDIDT_TD_CTRL_OCP0x43, DIDT_TD_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
165 { ixDIDT_TD_CTRL_OCP0x43, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0x00ff, GPU_CONFIGREG_DIDT_IND },
166
167 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3fff, GPU_CONFIGREG_DIDT_IND },
168 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_0_MASK0xc000, DIDT_TD_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
169 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x000f, GPU_CONFIGREG_DIDT_IND },
170 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_1_MASK0x4000000, DIDT_TD_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
171 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
172 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_2_MASK0x80000000, DIDT_TD_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
173
174 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001L, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
175 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007eL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
176 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
177 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x01aa, GPU_CONFIGREG_DIDT_IND },
178 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
179
180 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0000, GPU_CONFIGREG_DIDT_IND },
181 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x0dde, GPU_CONFIGREG_DIDT_IND },
182 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x0dde, GPU_CONFIGREG_DIDT_IND },
183 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
184
185 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
186 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
187 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
188 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
189 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
190 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0009, GPU_CONFIGREG_DIDT_IND },
191 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0009, GPU_CONFIGREG_DIDT_IND },
192 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_TD_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
193
194 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x0004, GPU_CONFIGREG_DIDT_IND },
195 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x0037, GPU_CONFIGREG_DIDT_IND },
196 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0001, GPU_CONFIGREG_DIDT_IND },
197 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x00ff, GPU_CONFIGREG_DIDT_IND },
198
199 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0054, GPU_CONFIGREG_DIDT_IND },
200 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x0000, GPU_CONFIGREG_DIDT_IND },
201 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
202 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
203
204 { ixDIDT_TCP_CTRL10x61, DIDT_TCP_CTRL1__MIN_POWER_MASK0xffff, DIDT_TCP_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
205 { ixDIDT_TCP_CTRL10x61, DIDT_TCP_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_TCP_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
206
207 { ixDIDT_TCP_CTRL_OCP0x63, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
208 { ixDIDT_TCP_CTRL_OCP0x63, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
209
210 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3dde, GPU_CONFIGREG_DIDT_IND },
211 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_0_MASK0xc000, DIDT_TCP_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
212 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x0032, GPU_CONFIGREG_DIDT_IND },
213 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_1_MASK0x4000000, DIDT_TCP_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
214 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
215 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_2_MASK0x80000000, DIDT_TCP_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
216
217 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001L, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
218 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007eL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
219 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
220 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x01aa, GPU_CONFIGREG_DIDT_IND },
221 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
222
223 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
224 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x3dde, GPU_CONFIGREG_DIDT_IND },
225 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x3dde, GPU_CONFIGREG_DIDT_IND },
226 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
227
228 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
229 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
230 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
231 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
232 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
233 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0010, GPU_CONFIGREG_DIDT_IND },
234 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0010, GPU_CONFIGREG_DIDT_IND },
235 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_TCP_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
236
237 { 0xFFFFFFFF }
238};
239
240static const struct gpu_pt_config_reg DIDTConfig_Polaris11[] = {
241/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
242 * Offset Mask Shift Value Type
243 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
244 */
245 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x0073, GPU_CONFIGREG_DIDT_IND },
246 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x00ab, GPU_CONFIGREG_DIDT_IND },
247 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0084, GPU_CONFIGREG_DIDT_IND },
248 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x005a, GPU_CONFIGREG_DIDT_IND },
249
250 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0067, GPU_CONFIGREG_DIDT_IND },
251 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x0084, GPU_CONFIGREG_DIDT_IND },
252 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0027, GPU_CONFIGREG_DIDT_IND },
253 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0046, GPU_CONFIGREG_DIDT_IND },
254
255 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK0xff, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT0x0, 0x00aa, GPU_CONFIGREG_DIDT_IND },
256 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK0xff00, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT0x8, 0x0000, GPU_CONFIGREG_DIDT_IND },
257 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK0xff0000, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
258 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK0xff000000, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
259
260 { ixDIDT_SQ_CTRL10x1, DIDT_SQ_CTRL1__MIN_POWER_MASK0xffff, DIDT_SQ_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
261 { ixDIDT_SQ_CTRL10x1, DIDT_SQ_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_SQ_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
262
263 { ixDIDT_SQ_CTRL_OCP0x3, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
264 { ixDIDT_SQ_CTRL_OCP0x3, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
265
266 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3fff, GPU_CONFIGREG_DIDT_IND },
267 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_0_MASK0xc000, DIDT_SQ_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
268 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x000f, GPU_CONFIGREG_DIDT_IND },
269 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_1_MASK0x4000000, DIDT_SQ_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
270 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
271 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_2_MASK0x80000000, DIDT_SQ_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
272
273 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
274 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007e, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
275 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
276 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x01aa, GPU_CONFIGREG_DIDT_IND },
277 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
278
279 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0000, GPU_CONFIGREG_DIDT_IND },
280 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x0dde, GPU_CONFIGREG_DIDT_IND },
281 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x0dde, GPU_CONFIGREG_DIDT_IND },
282 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
283
284 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
285 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
286 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
287 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
288 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
289 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0008, GPU_CONFIGREG_DIDT_IND },
290 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0008, GPU_CONFIGREG_DIDT_IND },
291 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_SQ_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
292
293 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x000a, GPU_CONFIGREG_DIDT_IND },
294 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x0010, GPU_CONFIGREG_DIDT_IND },
295 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0017, GPU_CONFIGREG_DIDT_IND },
296 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x002f, GPU_CONFIGREG_DIDT_IND },
297
298 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0046, GPU_CONFIGREG_DIDT_IND },
299 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x005d, GPU_CONFIGREG_DIDT_IND },
300 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
301 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
302
303 { ixDIDT_TD_CTRL10x41, DIDT_TD_CTRL1__MIN_POWER_MASK0xffff, DIDT_TD_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
304 { ixDIDT_TD_CTRL10x41, DIDT_TD_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_TD_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
305
306 { ixDIDT_TD_CTRL_OCP0x43, DIDT_TD_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
307 { ixDIDT_TD_CTRL_OCP0x43, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0x00ff, GPU_CONFIGREG_DIDT_IND },
308
309 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3fff, GPU_CONFIGREG_DIDT_IND },
310 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_0_MASK0xc000, DIDT_TD_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
311 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x000f, GPU_CONFIGREG_DIDT_IND },
312 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_1_MASK0x4000000, DIDT_TD_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
313 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
314 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_2_MASK0x80000000, DIDT_TD_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
315
316 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001L, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
317 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007eL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
318 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
319 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x01aa, GPU_CONFIGREG_DIDT_IND },
320 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
321
322 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0000, GPU_CONFIGREG_DIDT_IND },
323 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x0dde, GPU_CONFIGREG_DIDT_IND },
324 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x0dde, GPU_CONFIGREG_DIDT_IND },
325 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
326
327 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
328 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
329 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
330 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
331 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
332 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0008, GPU_CONFIGREG_DIDT_IND },
333 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0008, GPU_CONFIGREG_DIDT_IND },
334 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_TD_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
335
336 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x0004, GPU_CONFIGREG_DIDT_IND },
337 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x0037, GPU_CONFIGREG_DIDT_IND },
338 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0001, GPU_CONFIGREG_DIDT_IND },
339 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x00ff, GPU_CONFIGREG_DIDT_IND },
340
341 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0054, GPU_CONFIGREG_DIDT_IND },
342 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x0000, GPU_CONFIGREG_DIDT_IND },
343 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
344 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
345
346 { ixDIDT_TCP_CTRL10x61, DIDT_TCP_CTRL1__MIN_POWER_MASK0xffff, DIDT_TCP_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
347 { ixDIDT_TCP_CTRL10x61, DIDT_TCP_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_TCP_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
348
349 { ixDIDT_TCP_CTRL_OCP0x63, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
350 { ixDIDT_TCP_CTRL_OCP0x63, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
351
352 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3dde, GPU_CONFIGREG_DIDT_IND },
353 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_0_MASK0xc000, DIDT_TCP_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
354 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x0032, GPU_CONFIGREG_DIDT_IND },
355 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_1_MASK0x4000000, DIDT_TCP_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
356 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
357 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_2_MASK0x80000000, DIDT_TCP_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
358
359 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001L, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
360 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007eL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
361 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
362 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x01aa, GPU_CONFIGREG_DIDT_IND },
363 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
364
365 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
366 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x3dde, GPU_CONFIGREG_DIDT_IND },
367 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x3dde, GPU_CONFIGREG_DIDT_IND },
368 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
369
370 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
371 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
372 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
373 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
374 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
375 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0010, GPU_CONFIGREG_DIDT_IND },
376 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0010, GPU_CONFIGREG_DIDT_IND },
377 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_TCP_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
378
379 { 0xFFFFFFFF }
380};
381
382static const struct gpu_pt_config_reg DIDTConfig_Polaris12[] = {
383/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
384 * Offset Mask Shift Value Type
385 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
386 */
387 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x0073, GPU_CONFIGREG_DIDT_IND },
388 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x00ab, GPU_CONFIGREG_DIDT_IND },
389 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0084, GPU_CONFIGREG_DIDT_IND },
390 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x005a, GPU_CONFIGREG_DIDT_IND },
391
392 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0067, GPU_CONFIGREG_DIDT_IND },
393 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x0084, GPU_CONFIGREG_DIDT_IND },
394 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0027, GPU_CONFIGREG_DIDT_IND },
395 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0046, GPU_CONFIGREG_DIDT_IND },
396
397 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK0xff, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT0x0, 0x00aa, GPU_CONFIGREG_DIDT_IND },
398 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK0xff00, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT0x8, 0x0000, GPU_CONFIGREG_DIDT_IND },
399 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK0xff0000, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
400 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK0xff000000, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
401
402 { ixDIDT_SQ_CTRL10x1, DIDT_SQ_CTRL1__MIN_POWER_MASK0xffff, DIDT_SQ_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
403 { ixDIDT_SQ_CTRL10x1, DIDT_SQ_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_SQ_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
404
405 { ixDIDT_SQ_CTRL_OCP0x3, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
406 { ixDIDT_SQ_CTRL_OCP0x3, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
407
408 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3853, GPU_CONFIGREG_DIDT_IND },
409 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_0_MASK0xc000, DIDT_SQ_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
410 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x005a, GPU_CONFIGREG_DIDT_IND },
411 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_1_MASK0x4000000, DIDT_SQ_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
412 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
413 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_2_MASK0x80000000, DIDT_SQ_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
414
415 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
416 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007e, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
417 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
418 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x0ebb, GPU_CONFIGREG_DIDT_IND },
419 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
420
421 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
422 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x3853, GPU_CONFIGREG_DIDT_IND },
423 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x3153, GPU_CONFIGREG_DIDT_IND },
424 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
425
426 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
427 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
428 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
429 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
430 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
431 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0010, GPU_CONFIGREG_DIDT_IND },
432 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0010, GPU_CONFIGREG_DIDT_IND },
433 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_SQ_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
434
435 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x000a, GPU_CONFIGREG_DIDT_IND },
436 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x0010, GPU_CONFIGREG_DIDT_IND },
437 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0017, GPU_CONFIGREG_DIDT_IND },
438 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x002f, GPU_CONFIGREG_DIDT_IND },
439
440 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0046, GPU_CONFIGREG_DIDT_IND },
441 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x005d, GPU_CONFIGREG_DIDT_IND },
442 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
443 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
444
445 { ixDIDT_TD_CTRL10x41, DIDT_TD_CTRL1__MIN_POWER_MASK0xffff, DIDT_TD_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
446 { ixDIDT_TD_CTRL10x41, DIDT_TD_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_TD_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
447
448 { ixDIDT_TD_CTRL_OCP0x43, DIDT_TD_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
449 { ixDIDT_TD_CTRL_OCP0x43, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0x00ff, GPU_CONFIGREG_DIDT_IND },
450
451 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3fff, GPU_CONFIGREG_DIDT_IND },
452 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_0_MASK0xc000, DIDT_TD_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
453 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x000f, GPU_CONFIGREG_DIDT_IND },
454 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_1_MASK0x4000000, DIDT_TD_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
455 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
456 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_2_MASK0x80000000, DIDT_TD_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
457
458 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001L, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
459 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007eL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
460 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
461 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x01aa, GPU_CONFIGREG_DIDT_IND },
462 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
463
464 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0000, GPU_CONFIGREG_DIDT_IND },
465 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x0dde, GPU_CONFIGREG_DIDT_IND },
466 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x0dde, GPU_CONFIGREG_DIDT_IND },
467 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
468
469 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
470 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
471 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
472 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
473 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
474 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0008, GPU_CONFIGREG_DIDT_IND },
475 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0008, GPU_CONFIGREG_DIDT_IND },
476 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_TD_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
477
478 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x0004, GPU_CONFIGREG_DIDT_IND },
479 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x0037, GPU_CONFIGREG_DIDT_IND },
480 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0001, GPU_CONFIGREG_DIDT_IND },
481 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x00ff, GPU_CONFIGREG_DIDT_IND },
482
483 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0054, GPU_CONFIGREG_DIDT_IND },
484 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x0000, GPU_CONFIGREG_DIDT_IND },
485 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
486 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
487
488 { ixDIDT_TCP_CTRL10x61, DIDT_TCP_CTRL1__MIN_POWER_MASK0xffff, DIDT_TCP_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
489 { ixDIDT_TCP_CTRL10x61, DIDT_TCP_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_TCP_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
490
491 { ixDIDT_TCP_CTRL_OCP0x63, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
492 { ixDIDT_TCP_CTRL_OCP0x63, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
493
494 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3dde, GPU_CONFIGREG_DIDT_IND },
495 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_0_MASK0xc000, DIDT_TCP_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
496 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x0032, GPU_CONFIGREG_DIDT_IND },
497 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_1_MASK0x4000000, DIDT_TCP_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
498 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
499 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_2_MASK0x80000000, DIDT_TCP_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
500
501 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001L, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
502 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007eL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
503 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
504 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x01aa, GPU_CONFIGREG_DIDT_IND },
505 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
506
507 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
508 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x3dde, GPU_CONFIGREG_DIDT_IND },
509 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x3dde, GPU_CONFIGREG_DIDT_IND },
510 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
511
512 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
513 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
514 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
515 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
516 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
517 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0010, GPU_CONFIGREG_DIDT_IND },
518 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0010, GPU_CONFIGREG_DIDT_IND },
519 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_TCP_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
520 { 0xFFFFFFFF }
521};
522
523static const struct gpu_pt_config_reg DIDTConfig_Polaris11_Kicker[] =
524{
525/* ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
526 * Offset Mask Shift Value Type
527 * ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
528 */
529 /* DIDT_SQ */
530 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x004c, GPU_CONFIGREG_DIDT_IND },
531 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x00d0, GPU_CONFIGREG_DIDT_IND },
532 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0069, GPU_CONFIGREG_DIDT_IND },
533 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x0048, GPU_CONFIGREG_DIDT_IND },
534
535 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x005f, GPU_CONFIGREG_DIDT_IND },
536 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x007a, GPU_CONFIGREG_DIDT_IND },
537 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x001f, GPU_CONFIGREG_DIDT_IND },
538 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x002d, GPU_CONFIGREG_DIDT_IND },
539
540 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK0xff, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT0x0, 0x0088, GPU_CONFIGREG_DIDT_IND },
541 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK0xff00, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT0x8, 0x0000, GPU_CONFIGREG_DIDT_IND },
542 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK0xff0000, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
543 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK0xff000000, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
544
545 { ixDIDT_SQ_CTRL10x1, DIDT_SQ_CTRL1__MIN_POWER_MASK0xffff, DIDT_SQ_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
546 { ixDIDT_SQ_CTRL10x1, DIDT_SQ_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_SQ_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
547
548 { ixDIDT_SQ_CTRL_OCP0x3, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
549 { ixDIDT_SQ_CTRL_OCP0x3, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0x00ff, GPU_CONFIGREG_DIDT_IND },
550
551 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3fff, GPU_CONFIGREG_DIDT_IND },
552 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_0_MASK0xc000, DIDT_SQ_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
553 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x000f, GPU_CONFIGREG_DIDT_IND },
554 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_1_MASK0x4000000, DIDT_SQ_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
555 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
556 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_2_MASK0x80000000, DIDT_SQ_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
557
558 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
559 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007e, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
560 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
561 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x01aa, GPU_CONFIGREG_DIDT_IND },
562 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
563
564 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0000, GPU_CONFIGREG_DIDT_IND },
565 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x0dde, GPU_CONFIGREG_DIDT_IND },
566 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x0dde, GPU_CONFIGREG_DIDT_IND },
567 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
568
569 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
570 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
571 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
572 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
573 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
574 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0008, GPU_CONFIGREG_DIDT_IND },
575 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0008, GPU_CONFIGREG_DIDT_IND },
576 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_SQ_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
577
578 /* DIDT_TD */
579 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x000a, GPU_CONFIGREG_DIDT_IND },
580 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x0010, GPU_CONFIGREG_DIDT_IND },
581 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0017, GPU_CONFIGREG_DIDT_IND },
582 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x002f, GPU_CONFIGREG_DIDT_IND },
583
584 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0046, GPU_CONFIGREG_DIDT_IND },
585 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x005d, GPU_CONFIGREG_DIDT_IND },
586 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
587 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
588
589 { ixDIDT_TD_CTRL10x41, DIDT_TD_CTRL1__MIN_POWER_MASK0xffff, DIDT_TD_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
590 { ixDIDT_TD_CTRL10x41, DIDT_TD_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_TD_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
591
592 { ixDIDT_TD_CTRL_OCP0x43, DIDT_TD_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
593 { ixDIDT_TD_CTRL_OCP0x43, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0x00ff, GPU_CONFIGREG_DIDT_IND },
594
595 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3fff, GPU_CONFIGREG_DIDT_IND },
596 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_0_MASK0xc000, DIDT_TD_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
597 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x000f, GPU_CONFIGREG_DIDT_IND },
598 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_1_MASK0x4000000, DIDT_TD_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
599 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
600 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_2_MASK0x80000000, DIDT_TD_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
601
602 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001L, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
603 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007eL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
604 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
605 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x01aa, GPU_CONFIGREG_DIDT_IND },
606 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
607
608 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0000, GPU_CONFIGREG_DIDT_IND },
609 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x0dde, GPU_CONFIGREG_DIDT_IND },
610 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x0dde, GPU_CONFIGREG_DIDT_IND },
611 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
612
613 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
614 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
615 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
616 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
617 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
618 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0008, GPU_CONFIGREG_DIDT_IND },
619 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0008, GPU_CONFIGREG_DIDT_IND },
620 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_TD_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
621
622 /* DIDT_TCP */
623 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x0004, GPU_CONFIGREG_DIDT_IND },
624 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x0037, GPU_CONFIGREG_DIDT_IND },
625 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0001, GPU_CONFIGREG_DIDT_IND },
626 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x00ff, GPU_CONFIGREG_DIDT_IND },
627
628 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0054, GPU_CONFIGREG_DIDT_IND },
629 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x0000, GPU_CONFIGREG_DIDT_IND },
630 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
631 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
632
633 { ixDIDT_TCP_CTRL10x61, DIDT_TCP_CTRL1__MIN_POWER_MASK0xffff, DIDT_TCP_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
634 { ixDIDT_TCP_CTRL10x61, DIDT_TCP_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_TCP_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
635
636 { ixDIDT_TCP_CTRL_OCP0x63, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
637 { ixDIDT_TCP_CTRL_OCP0x63, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
638
639 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3dde, GPU_CONFIGREG_DIDT_IND },
640 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_0_MASK0xc000, DIDT_TCP_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
641 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x0032, GPU_CONFIGREG_DIDT_IND },
642 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_1_MASK0x4000000, DIDT_TCP_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
643 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
644 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_2_MASK0x80000000, DIDT_TCP_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
645
646 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001L, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
647 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007eL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
648 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
649 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d,0x01aa, GPU_CONFIGREG_DIDT_IND },
650 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
651
652 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
653 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x3dde, GPU_CONFIGREG_DIDT_IND },
654 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x3dde, GPU_CONFIGREG_DIDT_IND },
655 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
656
657 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
658 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
659 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
660 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
661 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
662 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0010, GPU_CONFIGREG_DIDT_IND },
663 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0010, GPU_CONFIGREG_DIDT_IND },
664 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_TCP_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
665
666 { 0xFFFFFFFF } /* End of list */
667};
668
669static const struct gpu_pt_config_reg GCCACConfig_VegaM[] =
670{
671// ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
672// Offset Mask Shift Value Type
673// ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
674 // DIDT_SQ
675 //
676 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x00060013, GPU_CONFIGREG_GC_CAC_IND },
677 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x00860013, GPU_CONFIGREG_GC_CAC_IND },
678 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x01060013, GPU_CONFIGREG_GC_CAC_IND },
679 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x01860013, GPU_CONFIGREG_GC_CAC_IND },
680 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x02060013, GPU_CONFIGREG_GC_CAC_IND },
681 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x02860013, GPU_CONFIGREG_GC_CAC_IND },
682 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x03060013, GPU_CONFIGREG_GC_CAC_IND },
683 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x03860013, GPU_CONFIGREG_GC_CAC_IND },
684 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x04060013, GPU_CONFIGREG_GC_CAC_IND },
685
686 // DIDT_TD
687 //
688 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x000E0013, GPU_CONFIGREG_GC_CAC_IND },
689 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x008E0013, GPU_CONFIGREG_GC_CAC_IND },
690 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x010E0013, GPU_CONFIGREG_GC_CAC_IND },
691 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x018E0013, GPU_CONFIGREG_GC_CAC_IND },
692 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x020E0013, GPU_CONFIGREG_GC_CAC_IND },
693
694 // DIDT_TCP
695 //
696 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x00100013, GPU_CONFIGREG_GC_CAC_IND },
697 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x00900013, GPU_CONFIGREG_GC_CAC_IND },
698 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x01100013, GPU_CONFIGREG_GC_CAC_IND },
699 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x01900013, GPU_CONFIGREG_GC_CAC_IND },
700 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x02100013, GPU_CONFIGREG_GC_CAC_IND },
701 { ixGC_CAC_CNTL0x0000, 0xFFFFFFFF, 0, 0x02900013, GPU_CONFIGREG_GC_CAC_IND },
702
703 { 0xFFFFFFFF } // End of list
704};
705
706static const struct gpu_pt_config_reg DIDTConfig_VegaM[] =
707{
708// ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
709// Offset Mask Shift Value Type
710// ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
711 // DIDT_SQ
712 //
713 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_SQ_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x0073, GPU_CONFIGREG_DIDT_IND },
714 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_SQ_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x00ab, GPU_CONFIGREG_DIDT_IND },
715 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_SQ_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0084, GPU_CONFIGREG_DIDT_IND },
716 { ixDIDT_SQ_WEIGHT0_30x10, DIDT_SQ_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_SQ_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x005a, GPU_CONFIGREG_DIDT_IND },
717
718 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_SQ_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0067, GPU_CONFIGREG_DIDT_IND },
719 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_SQ_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x0084, GPU_CONFIGREG_DIDT_IND },
720 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_SQ_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0027, GPU_CONFIGREG_DIDT_IND },
721 { ixDIDT_SQ_WEIGHT4_70x11, DIDT_SQ_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_SQ_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0046, GPU_CONFIGREG_DIDT_IND },
722
723 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT8_MASK0xff, DIDT_SQ_WEIGHT8_11__WEIGHT8__SHIFT0x0, 0x00aa, GPU_CONFIGREG_DIDT_IND },
724 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT9_MASK0xff00, DIDT_SQ_WEIGHT8_11__WEIGHT9__SHIFT0x8, 0x0000, GPU_CONFIGREG_DIDT_IND },
725 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT10_MASK0xff0000, DIDT_SQ_WEIGHT8_11__WEIGHT10__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
726 { ixDIDT_SQ_WEIGHT8_110x12, DIDT_SQ_WEIGHT8_11__WEIGHT11_MASK0xff000000, DIDT_SQ_WEIGHT8_11__WEIGHT11__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
727
728 { ixDIDT_SQ_CTRL10x1, DIDT_SQ_CTRL1__MIN_POWER_MASK0xffff, DIDT_SQ_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
729 { ixDIDT_SQ_CTRL10x1, DIDT_SQ_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_SQ_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
730
731 { ixDIDT_SQ_CTRL_OCP0x3, DIDT_SQ_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_SQ_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
732 { ixDIDT_SQ_CTRL_OCP0x3, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_SQ_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
733
734 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_SQ_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3853, GPU_CONFIGREG_DIDT_IND },
735 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_0_MASK0xc000, DIDT_SQ_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
736 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_SQ_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x005a, GPU_CONFIGREG_DIDT_IND },
737 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_1_MASK0x4000000, DIDT_SQ_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
738 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_SQ_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
739 { ixDIDT_SQ_CTRL20x2, DIDT_SQ_CTRL2__UNUSED_2_MASK0x80000000, DIDT_SQ_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
740
741 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001, DIDT_SQ_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
742 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007e, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
743 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_SQ_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
744 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_SQ_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x0ebb, GPU_CONFIGREG_DIDT_IND },
745 { ixDIDT_SQ_STALL_CTRL0x0004, DIDT_SQ_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_SQ_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
746
747 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_SQ_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
748 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x3853, GPU_CONFIGREG_DIDT_IND },
749 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_SQ_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x3153, GPU_CONFIGREG_DIDT_IND },
750 { ixDIDT_SQ_TUNING_CTRL0x0005, DIDT_SQ_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_SQ_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
751
752 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
753 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_SQ_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
754 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_SQ_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
755 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
756 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
757 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0010, GPU_CONFIGREG_DIDT_IND },
758 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_SQ_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0010, GPU_CONFIGREG_DIDT_IND },
759 { ixDIDT_SQ_CTRL00x0, DIDT_SQ_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_SQ_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
760
761 // DIDT_TD
762 //
763 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_TD_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x000a, GPU_CONFIGREG_DIDT_IND },
764 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_TD_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x0010, GPU_CONFIGREG_DIDT_IND },
765 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_TD_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0017, GPU_CONFIGREG_DIDT_IND },
766 { ixDIDT_TD_WEIGHT0_30x50, DIDT_TD_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_TD_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x002f, GPU_CONFIGREG_DIDT_IND },
767
768 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_TD_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0046, GPU_CONFIGREG_DIDT_IND },
769 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_TD_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x005d, GPU_CONFIGREG_DIDT_IND },
770 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_TD_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
771 { ixDIDT_TD_WEIGHT4_70x51, DIDT_TD_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_TD_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
772
773 { ixDIDT_TD_CTRL10x41, DIDT_TD_CTRL1__MIN_POWER_MASK0xffff, DIDT_TD_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
774 { ixDIDT_TD_CTRL10x41, DIDT_TD_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_TD_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
775
776 { ixDIDT_TD_CTRL_OCP0x43, DIDT_TD_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_TD_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
777 { ixDIDT_TD_CTRL_OCP0x43, DIDT_TD_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_TD_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0x00ff, GPU_CONFIGREG_DIDT_IND },
778
779 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3fff, GPU_CONFIGREG_DIDT_IND },
780 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_0_MASK0xc000, DIDT_TD_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
781 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x000f, GPU_CONFIGREG_DIDT_IND },
782 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_1_MASK0x4000000, DIDT_TD_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
783 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
784 { ixDIDT_TD_CTRL20x42, DIDT_TD_CTRL2__UNUSED_2_MASK0x80000000, DIDT_TD_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
785
786 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001L, DIDT_TD_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
787 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007eL, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
788 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_TD_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
789 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_TD_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d, 0x01aa, GPU_CONFIGREG_DIDT_IND },
790 { ixDIDT_TD_STALL_CTRL0x0044, DIDT_TD_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_TD_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
791
792 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_TD_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0000, GPU_CONFIGREG_DIDT_IND },
793 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x0dde, GPU_CONFIGREG_DIDT_IND },
794 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_TD_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x0dde, GPU_CONFIGREG_DIDT_IND },
795 { ixDIDT_TD_TUNING_CTRL0x0045, DIDT_TD_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_TD_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
796
797 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
798 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_TD_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
799 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_TD_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
800 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
801 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
802 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0009, GPU_CONFIGREG_DIDT_IND },
803 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_TD_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0009, GPU_CONFIGREG_DIDT_IND },
804 { ixDIDT_TD_CTRL00x40, DIDT_TD_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_TD_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
805
806 // DIDT_TCP
807 //
808 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT0_MASK0xff, DIDT_TCP_WEIGHT0_3__WEIGHT0__SHIFT0x0, 0x0004, GPU_CONFIGREG_DIDT_IND },
809 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT1_MASK0xff00, DIDT_TCP_WEIGHT0_3__WEIGHT1__SHIFT0x8, 0x0037, GPU_CONFIGREG_DIDT_IND },
810 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT2_MASK0xff0000, DIDT_TCP_WEIGHT0_3__WEIGHT2__SHIFT0x10, 0x0001, GPU_CONFIGREG_DIDT_IND },
811 { ixDIDT_TCP_WEIGHT0_30x70, DIDT_TCP_WEIGHT0_3__WEIGHT3_MASK0xff000000, DIDT_TCP_WEIGHT0_3__WEIGHT3__SHIFT0x18, 0x00ff, GPU_CONFIGREG_DIDT_IND },
812
813 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT4_MASK0xff, DIDT_TCP_WEIGHT4_7__WEIGHT4__SHIFT0x0, 0x0054, GPU_CONFIGREG_DIDT_IND },
814 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT5_MASK0xff00, DIDT_TCP_WEIGHT4_7__WEIGHT5__SHIFT0x8, 0x0000, GPU_CONFIGREG_DIDT_IND },
815 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT6_MASK0xff0000, DIDT_TCP_WEIGHT4_7__WEIGHT6__SHIFT0x10, 0x0000, GPU_CONFIGREG_DIDT_IND },
816 { ixDIDT_TCP_WEIGHT4_70x71, DIDT_TCP_WEIGHT4_7__WEIGHT7_MASK0xff000000, DIDT_TCP_WEIGHT4_7__WEIGHT7__SHIFT0x18, 0x0000, GPU_CONFIGREG_DIDT_IND },
817
818 { ixDIDT_TCP_CTRL10x61, DIDT_TCP_CTRL1__MIN_POWER_MASK0xffff, DIDT_TCP_CTRL1__MIN_POWER__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
819 { ixDIDT_TCP_CTRL10x61, DIDT_TCP_CTRL1__MAX_POWER_MASK0xffff0000, DIDT_TCP_CTRL1__MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
820
821 { ixDIDT_TCP_CTRL_OCP0x63, DIDT_TCP_CTRL_OCP__UNUSED_0_MASK0xffff, DIDT_TCP_CTRL_OCP__UNUSED_0__SHIFT0x0, 0x0000, GPU_CONFIGREG_DIDT_IND },
822 { ixDIDT_TCP_CTRL_OCP0x63, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER_MASK0xffff0000, DIDT_TCP_CTRL_OCP__OCP_MAX_POWER__SHIFT0x10, 0xffff, GPU_CONFIGREG_DIDT_IND },
823
824 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__MAX_POWER_DELTA_MASK0x3fff, DIDT_TCP_CTRL2__MAX_POWER_DELTA__SHIFT0x0, 0x3dde, GPU_CONFIGREG_DIDT_IND },
825 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_0_MASK0xc000, DIDT_TCP_CTRL2__UNUSED_0__SHIFT0xe, 0x0000, GPU_CONFIGREG_DIDT_IND },
826 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK0x3ff0000, DIDT_TCP_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT0x10, 0x0032, GPU_CONFIGREG_DIDT_IND },
827 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_1_MASK0x4000000, DIDT_TCP_CTRL2__UNUSED_1__SHIFT0x1a, 0x0000, GPU_CONFIGREG_DIDT_IND },
828 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK0x78000000, DIDT_TCP_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT0x1b, 0x0000, GPU_CONFIGREG_DIDT_IND },
829 { ixDIDT_TCP_CTRL20x62, DIDT_TCP_CTRL2__UNUSED_2_MASK0x80000000, DIDT_TCP_CTRL2__UNUSED_2__SHIFT0x1f, 0x0000, GPU_CONFIGREG_DIDT_IND },
830
831 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE_MASK0x00000001L, DIDT_TCP_STALL_CTRL__DIDT_STALL_CTRL_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
832 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI_MASK0x0000007eL, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_HI__SHIFT0x00000001, 0x0001, GPU_CONFIGREG_DIDT_IND },
833 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO_MASK0x00001f80L, DIDT_TCP_STALL_CTRL__DIDT_STALL_DELAY_LO__SHIFT0x00000007, 0x0001, GPU_CONFIGREG_DIDT_IND },
834 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD_MASK0x1fffe000L, DIDT_TCP_STALL_CTRL__DIDT_HI_POWER_THRESHOLD__SHIFT0x0000000d,0x01aa, GPU_CONFIGREG_DIDT_IND },
835 { ixDIDT_TCP_STALL_CTRL0x0064, DIDT_TCP_STALL_CTRL__UNUSED_0_MASK0xe0000000L, DIDT_TCP_STALL_CTRL__UNUSED_0__SHIFT0x0000001d, 0x0000, GPU_CONFIGREG_DIDT_IND },
836
837 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE_MASK0x00000001L, DIDT_TCP_TUNING_CTRL__DIDT_TUNING_ENABLE__SHIFT0x00000000, 0x0001, GPU_CONFIGREG_DIDT_IND },
838 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI_MASK0x00007ffeL, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_HI__SHIFT0x00000001, 0x3dde, GPU_CONFIGREG_DIDT_IND },
839 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO_MASK0x1fff8000L, DIDT_TCP_TUNING_CTRL__MAX_POWER_DELTA_LO__SHIFT0x0000000f, 0x3dde, GPU_CONFIGREG_DIDT_IND },
840 { ixDIDT_TCP_TUNING_CTRL0x0065, DIDT_TCP_TUNING_CTRL__UNUSED_0_MASK0xc0000000, DIDT_TCP_TUNING_CTRL__UNUSED_0__SHIFT0x0000001e, 0x0000, GPU_CONFIGREG_DIDT_IND },
841
842 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK0x1, DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT0x0, 0x0001, GPU_CONFIGREG_DIDT_IND },
843 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__USE_REF_CLOCK_MASK0x2, DIDT_TCP_CTRL0__USE_REF_CLOCK__SHIFT0x1, 0x0000, GPU_CONFIGREG_DIDT_IND },
844 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__PHASE_OFFSET_MASK0xc, DIDT_TCP_CTRL0__PHASE_OFFSET__SHIFT0x2, 0x0000, GPU_CONFIGREG_DIDT_IND },
845 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CTRL_RST_MASK0x10, DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT0x4, 0x0000, GPU_CONFIGREG_DIDT_IND },
846 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK0x20, DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT0x5, 0x0000, GPU_CONFIGREG_DIDT_IND },
847 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI_MASK0x00000fc0L, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_HI__SHIFT0x00000006, 0x0010, GPU_CONFIGREG_DIDT_IND },
848 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO_MASK0x0003f000L, DIDT_TCP_CTRL0__DIDT_MAX_STALLS_ALLOWED_LO__SHIFT0x0000000c, 0x0010, GPU_CONFIGREG_DIDT_IND },
849 { ixDIDT_TCP_CTRL00x60, DIDT_TCP_CTRL0__UNUSED_0_MASK0xfffc0000, DIDT_TCP_CTRL0__UNUSED_0__SHIFT0x12, 0x0000, GPU_CONFIGREG_DIDT_IND },
850
851 { 0xFFFFFFFF } // End of list
852};
853static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool_Bool enable)
854{
855 struct amdgpu_device *adev = hwmgr->adev;
856 uint32_t en = enable ? 1 : 0;
857 uint32_t block_en = 0;
858 int32_t result = 0;
859 uint32_t didt_block;
860
861 if ((hwmgr->chip_id == CHIP_POLARIS11) &&
862 (adev->pdev->subsystem_vendor != 0x106B))
863 didt_block = Polaris11_DIDTBlock_Info;
864 else
865 didt_block = DIDTBlock_Info;
866
867 block_en = PP_CAP(PHM_PlatformCaps_SQRamping)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_SQRamping)) ? en : 0;
868 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__DIDT,0x0,((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__DIDT,0x0)) & ~0x1) | (block_en) <<
0x0))
869 DIDT_SQ_CTRL0, DIDT_CTRL_EN, block_en)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__DIDT,0x0,((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__DIDT,0x0)) & ~0x1) | (block_en) <<
0x0));
870 didt_block &= ~SQ_Enable_MASK0x1;
871 didt_block |= block_en << SQ_Enable_SHIFT0;
872
873 block_en = PP_CAP(PHM_PlatformCaps_DBRamping)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_DBRamping)) ? en : 0;
874 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__DIDT,0x20,((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__DIDT,0x20)) & ~0x1) | (block_en) <<
0x0))
875 DIDT_DB_CTRL0, DIDT_CTRL_EN, block_en)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__DIDT,0x20,((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__DIDT,0x20)) & ~0x1) | (block_en) <<
0x0));
876 didt_block &= ~DB_Enable_MASK0x1000000;
877 didt_block |= block_en << DB_Enable_SHIFT24;
878
879 block_en = PP_CAP(PHM_PlatformCaps_TDRamping)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_TDRamping)) ? en : 0;
880 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__DIDT,0x40,((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__DIDT,0x40)) & ~0x1) | (block_en) <<
0x0))
881 DIDT_TD_CTRL0, DIDT_CTRL_EN, block_en)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__DIDT,0x40,((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__DIDT,0x40)) & ~0x1) | (block_en) <<
0x0));
882 didt_block &= ~TD_Enable_MASK0x10000;
883 didt_block |= block_en << TD_Enable_SHIFT16;
884
885 block_en = PP_CAP(PHM_PlatformCaps_TCPRamping)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_TCPRamping)) ? en : 0;
886 CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT,(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__DIDT,0x60,((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__DIDT,0x60)) & ~0x1) | (block_en) <<
0x0))
887 DIDT_TCP_CTRL0, DIDT_CTRL_EN, block_en)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__DIDT,0x60,((((struct cgs_device
*)hwmgr->device)->ops->read_ind_register(hwmgr->
device,CGS_IND_REG__DIDT,0x60)) & ~0x1) | (block_en) <<
0x0));
888 didt_block &= ~TCP_Enable_MASK0x100;
889 didt_block |= block_en << TCP_Enable_SHIFT8;
890
891 if (enable)
892 result = smum_send_msg_to_smc_with_parameter(hwmgr,
893 PPSMC_MSG_Didt_Block_Function((uint16_t) 0x301),
894 didt_block,
895 NULL((void *)0));
896
897 return result;
898}
899
900static int smu7_program_pt_config_registers(struct pp_hwmgr *hwmgr,
901 const struct gpu_pt_config_reg *cac_config_regs)
902{
903 const struct gpu_pt_config_reg *config_regs = cac_config_regs;
904 uint32_t cache = 0;
905 uint32_t data = 0;
906
907 PP_ASSERT_WITH_CODE((config_regs != NULL), "Invalid config register table.", return -EINVAL)do { if (!((config_regs != ((void *)0)))) { printk("\0014" "amdgpu: "
"%s\n", "Invalid config register table."); return -22; } } while
(0);
908
909 while (config_regs->offset != 0xFFFFFFFF) {
910 if (config_regs->type == GPU_CONFIGREG_CACHE)
911 cache |= ((config_regs->value << config_regs->shift) & config_regs->mask);
912 else {
913 switch (config_regs->type) {
914 case GPU_CONFIGREG_SMC_IND:
915 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset)(((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__SMC,config_regs->offset));
916 break;
917
918 case GPU_CONFIGREG_DIDT_IND:
919 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset)(((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG__DIDT,config_regs->offset));
920 break;
921
922 case GPU_CONFIGREG_GC_CAC_IND:
923 data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset)(((struct cgs_device *)hwmgr->device)->ops->read_ind_register
(hwmgr->device,CGS_IND_REG_GC_CAC,config_regs->offset));
924 break;
925
926 default:
927 data = cgs_read_register(hwmgr->device, config_regs->offset)(((struct cgs_device *)hwmgr->device)->ops->read_register
(hwmgr->device,config_regs->offset));
928 break;
929 }
930
931 data &= ~config_regs->mask;
932 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
933 data |= cache;
934
935 switch (config_regs->type) {
936 case GPU_CONFIGREG_SMC_IND:
937 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, config_regs->offset, data)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__SMC,config_regs->offset,data
));
938 break;
939
940 case GPU_CONFIGREG_DIDT_IND:
941 cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, config_regs->offset, data)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG__DIDT,config_regs->offset,data
));
942 break;
943
944 case GPU_CONFIGREG_GC_CAC_IND:
945 cgs_write_ind_register(hwmgr->device, CGS_IND_REG_GC_CAC, config_regs->offset, data)(((struct cgs_device *)hwmgr->device)->ops->write_ind_register
(hwmgr->device,CGS_IND_REG_GC_CAC,config_regs->offset,data
));
946 break;
947
948 default:
949 cgs_write_register(hwmgr->device, config_regs->offset, data)(((struct cgs_device *)hwmgr->device)->ops->write_register
(hwmgr->device,config_regs->offset,data));
950 break;
951 }
952 cache = 0;
953 }
954
955 config_regs++;
956 }
957
958 return 0;
959}
960
961int smu7_enable_didt_config(struct pp_hwmgr *hwmgr)
962{
963 int result;
964 uint32_t num_se = 0;
965 uint32_t count, value, value2;
966 struct amdgpu_device *adev = hwmgr->adev;
967 uint32_t efuse;
968
969 num_se = adev->gfx.config.max_shader_engines;
970
971 if (PP_CAP(PHM_PlatformCaps_SQRamping)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_SQRamping)) ||
972 PP_CAP(PHM_PlatformCaps_DBRamping)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_DBRamping)) ||
973 PP_CAP(PHM_PlatformCaps_TDRamping)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_TDRamping)) ||
974 PP_CAP(PHM_PlatformCaps_TCPRamping)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_TCPRamping))) {
975
976 amdgpu_gfx_rlc_enter_safe_mode(adev);
977 mutex_lock(&adev->grbm_idx_mutex)rw_enter_write(&adev->grbm_idx_mutex);
978 value = 0;
Value stored to 'value' is never read
979 value2 = cgs_read_register(hwmgr->device, mmGRBM_GFX_INDEX)(((struct cgs_device *)hwmgr->device)->ops->read_register
(hwmgr->device,0xc200));
980 for (count = 0; count < num_se; count++) {
981 value = SYS_GRBM_GFX_INDEX_DATA__INSTANCE_BROADCAST_WRITES_MASK0x40000000
982 | SYS_GRBM_GFX_INDEX_DATA__SH_BROADCAST_WRITES_MASK0x20000000
983 | (count << SYS_GRBM_GFX_INDEX_DATA__SE_INDEX__SHIFT0x10);
984 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value)(((struct cgs_device *)hwmgr->device)->ops->write_register
(hwmgr->device,0xc200,value));
985
986 if (hwmgr->chip_id == CHIP_POLARIS10) {
987 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris10);
988 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "DIDT Config failed."); goto error; } } while (0);
989 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris10);
990 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "DIDT Config failed."); goto error; } } while (0);
991 } else if (hwmgr->chip_id == CHIP_POLARIS11) {
992 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
993 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "DIDT Config failed."); goto error; } } while (0);
994
995 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision)(((adev->pdev->device == 0x67EF) && ((adev->
pdev->revision == 0xE0) || (adev->pdev->revision == 0xE5
))) || ((adev->pdev->device == 0x67FF) && ((adev
->pdev->revision == 0xCF) || (adev->pdev->revision
== 0xEF) || (adev->pdev->revision == 0xFF)))) ||
996 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)((adev->pdev->device == 0x67EF) && ((adev->pdev
->revision == 0xE2))))
997 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11_Kicker);
998 else
999 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris11);
1000 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "DIDT Config failed."); goto error; } } while (0);
1001 } else if (hwmgr->chip_id == CHIP_POLARIS12) {
1002 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_Polaris11);
1003 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "DIDT Config failed."); goto error; } } while (0);
1004 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_Polaris12);
1005 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "DIDT Config failed."); goto error; } } while (0);
1006 } else if (hwmgr->chip_id == CHIP_VEGAM) {
1007 result = smu7_program_pt_config_registers(hwmgr, GCCACConfig_VegaM);
1008 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "DIDT Config failed."); goto error; } } while (0);
1009 result = smu7_program_pt_config_registers(hwmgr, DIDTConfig_VegaM);
1010 PP_ASSERT_WITH_CODE((result == 0), "DIDT Config failed.", goto error)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "DIDT Config failed."); goto error; } } while (0);
1011 }
1012 }
1013 cgs_write_register(hwmgr->device, mmGRBM_GFX_INDEX, value2)(((struct cgs_device *)hwmgr->device)->ops->write_register
(hwmgr->device,0xc200,value2));
1014
1015 result = smu7_enable_didt(hwmgr, true1);
1016 PP_ASSERT_WITH_CODE((result == 0), "EnableDiDt failed.", goto error)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "EnableDiDt failed."); goto error; } } while (0);
1017
1018 if (hwmgr->chip_id == CHIP_POLARIS11) {
1019 result = smum_send_msg_to_smc(hwmgr,
1020 (uint16_t)(PPSMC_MSG_EnableDpmDidt((uint16_t) 0x309)),
1021 NULL((void *)0));
1022 PP_ASSERT_WITH_CODE((0 == result),do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable DPM DIDT."); goto error; } } while (0)
1023 "Failed to enable DPM DIDT.", goto error)do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable DPM DIDT."); goto error; } } while (0);
1024
1025 if (ASICID_IS_P21(adev->pdev->device, adev->pdev->revision)(((adev->pdev->device == 0x67EF) && ((adev->
pdev->revision == 0xE0) || (adev->pdev->revision == 0xE5
))) || ((adev->pdev->device == 0x67FF) && ((adev
->pdev->revision == 0xCF) || (adev->pdev->revision
== 0xEF) || (adev->pdev->revision == 0xFF)))) ||
1026 ASICID_IS_P31(adev->pdev->device, adev->pdev->revision)((adev->pdev->device == 0x67EF) && ((adev->pdev
->revision == 0xE2)))) {
1027 result = smum_send_msg_to_smc(hwmgr,
1028 (uint16_t)(PPSMC_MSG_EnableDpmMcBlackout((uint16_t) 0x30B)),
1029 NULL((void *)0));
1030 PP_ASSERT_WITH_CODE((0 == result),do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable workaround for CRC issue."); goto error; }
} while (0)
1031 "Failed to enable workaround for CRC issue.", goto error)do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable workaround for CRC issue."); goto error; }
} while (0);
1032 } else {
1033 atomctrl_read_efuse(hwmgr, 547, 547, &efuse);
1034 if (efuse == 1) {
1035 result = smum_send_msg_to_smc(hwmgr,
1036 (uint16_t)(PPSMC_MSG_EnableDpmMcBlackout((uint16_t) 0x30B)),
1037 NULL((void *)0));
1038 PP_ASSERT_WITH_CODE((0 == result),do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable workaround for CRC issue."); goto error; }
} while (0)
1039 "Failed to enable workaround for CRC issue.", goto error)do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable workaround for CRC issue."); goto error; }
} while (0);
1040 } else {
1041 result = smum_send_msg_to_smc(hwmgr,
1042 (uint16_t)(PPSMC_MSG_DisableDpmMcBlackout((uint16_t) 0x30C)),
1043 NULL((void *)0));
1044 PP_ASSERT_WITH_CODE((0 == result),do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable workaround for CRC issue."); goto error; }
} while (0)
1045 "Failed to enable workaround for CRC issue.", goto error)do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable workaround for CRC issue."); goto error; }
} while (0);
1046 }
1047 }
1048 }
1049
1050 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
1051 amdgpu_gfx_rlc_exit_safe_mode(adev);
1052 }
1053
1054 return 0;
1055error:
1056 mutex_unlock(&adev->grbm_idx_mutex)rw_exit_write(&adev->grbm_idx_mutex);
1057 amdgpu_gfx_rlc_exit_safe_mode(adev);
1058 return result;
1059}
1060
1061int smu7_disable_didt_config(struct pp_hwmgr *hwmgr)
1062{
1063 int result;
1064 struct amdgpu_device *adev = hwmgr->adev;
1065
1066 if (PP_CAP(PHM_PlatformCaps_SQRamping)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_SQRamping)) ||
1067 PP_CAP(PHM_PlatformCaps_DBRamping)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_DBRamping)) ||
1068 PP_CAP(PHM_PlatformCaps_TDRamping)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_TDRamping)) ||
1069 PP_CAP(PHM_PlatformCaps_TCPRamping)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_TCPRamping))) {
1070
1071 amdgpu_gfx_rlc_enter_safe_mode(adev);
1072
1073 result = smu7_enable_didt(hwmgr, false0);
1074 PP_ASSERT_WITH_CODE((result == 0),do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Post DIDT enable clock gating failed."); goto error; } } while
(0)
1075 "Post DIDT enable clock gating failed.",do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Post DIDT enable clock gating failed."); goto error; } } while
(0)
1076 goto error)do { if (!((result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Post DIDT enable clock gating failed."); goto error; } } while
(0);
1077 if (hwmgr->chip_id == CHIP_POLARIS11) {
1078 result = smum_send_msg_to_smc(hwmgr,
1079 (uint16_t)(PPSMC_MSG_DisableDpmDidt((uint16_t) 0x30A)),
1080 NULL((void *)0));
1081 PP_ASSERT_WITH_CODE((0 == result),do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable DPM DIDT."); goto error; } } while (0)
1082 "Failed to disable DPM DIDT.", goto error)do { if (!((0 == result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable DPM DIDT."); goto error; } } while (0);
1083 }
1084 amdgpu_gfx_rlc_exit_safe_mode(adev);
1085 }
1086
1087 return 0;
1088error:
1089 amdgpu_gfx_rlc_exit_safe_mode(adev);
1090 return result;
1091}
1092
1093int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr)
1094{
1095 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1096 int result = 0;
1097
1098 if (PP_CAP(PHM_PlatformCaps_CAC)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_CAC))) {
1099 int smc_result;
1100 smc_result = smum_send_msg_to_smc(hwmgr,
1101 (uint16_t)(PPSMC_MSG_EnableCac((uint16_t)0x53)),
1102 NULL((void *)0));
1103 PP_ASSERT_WITH_CODE((0 == smc_result),do { if (!((0 == smc_result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable CAC in SMC."); result = -1; } } while (0)
1104 "Failed to enable CAC in SMC.", result = -1)do { if (!((0 == smc_result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable CAC in SMC."); result = -1; } } while (0);
1105
1106 data->cac_enabled = (0 == smc_result) ? true1 : false0;
1107 }
1108 return result;
1109}
1110
1111int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr)
1112{
1113 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1114 int result = 0;
1115
1116 if (PP_CAP(PHM_PlatformCaps_CAC)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_CAC)) && data->cac_enabled) {
1117 int smc_result = smum_send_msg_to_smc(hwmgr,
1118 (uint16_t)(PPSMC_MSG_DisableCac((uint16_t)0x54)),
1119 NULL((void *)0));
1120 PP_ASSERT_WITH_CODE((smc_result == 0),do { if (!((smc_result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable CAC in SMC."); result = -1; } } while (0
)
1121 "Failed to disable CAC in SMC.", result = -1)do { if (!((smc_result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable CAC in SMC."); result = -1; } } while (0
);
1122
1123 data->cac_enabled = false0;
1124 }
1125 return result;
1126}
1127
1128int smu7_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
1129{
1130 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1131
1132 if (data->power_containment_features &
1133 POWERCONTAINMENT_FEATURE_PkgPwrLimit0x00000004)
1134 return smum_send_msg_to_smc_with_parameter(hwmgr,
1135 PPSMC_MSG_PkgPwrSetLimit((uint16_t) 0x187),
1136 n<<8,
1137 NULL((void *)0));
1138 return 0;
1139}
1140
1141static int smu7_set_overdriver_target_tdp(struct pp_hwmgr *hwmgr,
1142 uint32_t target_tdp)
1143{
1144 return smum_send_msg_to_smc_with_parameter(hwmgr,
1145 PPSMC_MSG_OverDriveSetTargetTdp((uint16_t) 0x188),
1146 target_tdp,
1147 NULL((void *)0));
1148}
1149
1150int smu7_enable_power_containment(struct pp_hwmgr *hwmgr)
1151{
1152 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1153 struct phm_ppt_v1_information *table_info =
1154 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1155 int smc_result;
1156 int result = 0;
1157 struct phm_cac_tdp_table *cac_table;
1158
1159 data->power_containment_features = 0;
1160 if (hwmgr->pp_table_version == PP_TABLE_V1)
1161 cac_table = table_info->cac_dtp_table;
1162 else
1163 cac_table = hwmgr->dyn_state.cac_dtp_table;
1164
1165 if (PP_CAP(PHM_PlatformCaps_PowerContainment)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_PowerContainment))) {
1166 if (data->enable_tdc_limit_feature) {
1167 smc_result = smum_send_msg_to_smc(hwmgr,
1168 (uint16_t)(PPSMC_MSG_TDCLimitEnable((uint16_t) 0x169)),
1169 NULL((void *)0));
1170 PP_ASSERT_WITH_CODE((0 == smc_result),do { if (!((0 == smc_result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable TDCLimit in SMC."); result = -1;; } } while
(0)
1171 "Failed to enable TDCLimit in SMC.", result = -1;)do { if (!((0 == smc_result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable TDCLimit in SMC."); result = -1;; } } while
(0);
1172 if (0 == smc_result)
1173 data->power_containment_features |=
1174 POWERCONTAINMENT_FEATURE_TDCLimit0x00000002;
1175 }
1176
1177 if (data->enable_pkg_pwr_tracking_feature) {
1178 smc_result = smum_send_msg_to_smc(hwmgr,
1179 (uint16_t)(PPSMC_MSG_PkgPwrLimitEnable((uint16_t) 0x185)),
1180 NULL((void *)0));
1181 PP_ASSERT_WITH_CODE((0 == smc_result),do { if (!((0 == smc_result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable PkgPwrTracking in SMC."); result = -1;; }
} while (0)
1182 "Failed to enable PkgPwrTracking in SMC.", result = -1;)do { if (!((0 == smc_result))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to enable PkgPwrTracking in SMC."); result = -1;; }
} while (0);
1183 if (0 == smc_result) {
1184 hwmgr->default_power_limit = hwmgr->power_limit =
1185 cac_table->usMaximumPowerDeliveryLimit;
1186 data->power_containment_features |=
1187 POWERCONTAINMENT_FEATURE_PkgPwrLimit0x00000004;
1188
1189 if (smu7_set_power_limit(hwmgr, hwmgr->power_limit))
1190 pr_err("Failed to set Default Power Limit in SMC!")printk("\0013" "amdgpu: " "Failed to set Default Power Limit in SMC!"
);
1191 }
1192 }
1193 }
1194 return result;
1195}
1196
1197int smu7_disable_power_containment(struct pp_hwmgr *hwmgr)
1198{
1199 struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
1200 int result = 0;
1201
1202 if (PP_CAP(PHM_PlatformCaps_PowerContainment)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_PowerContainment)) &&
1203 data->power_containment_features) {
1204 int smc_result;
1205
1206 if (data->power_containment_features &
1207 POWERCONTAINMENT_FEATURE_TDCLimit0x00000002) {
1208 smc_result = smum_send_msg_to_smc(hwmgr,
1209 (uint16_t)(PPSMC_MSG_TDCLimitDisable((uint16_t) 0x16a)),
1210 NULL((void *)0));
1211 PP_ASSERT_WITH_CODE((smc_result == 0),do { if (!((smc_result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable TDCLimit in SMC."); result = smc_result;
} } while (0)
1212 "Failed to disable TDCLimit in SMC.",do { if (!((smc_result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable TDCLimit in SMC."); result = smc_result;
} } while (0)
1213 result = smc_result)do { if (!((smc_result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable TDCLimit in SMC."); result = smc_result;
} } while (0);
1214 }
1215
1216 if (data->power_containment_features &
1217 POWERCONTAINMENT_FEATURE_DTE0x00000001) {
1218 smc_result = smum_send_msg_to_smc(hwmgr,
1219 (uint16_t)(PPSMC_MSG_DisableDTE((uint16_t)0x88)),
1220 NULL((void *)0));
1221 PP_ASSERT_WITH_CODE((smc_result == 0),do { if (!((smc_result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable DTE in SMC."); result = smc_result; } } while
(0)
1222 "Failed to disable DTE in SMC.",do { if (!((smc_result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable DTE in SMC."); result = smc_result; } } while
(0)
1223 result = smc_result)do { if (!((smc_result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable DTE in SMC."); result = smc_result; } } while
(0);
1224 }
1225
1226 if (data->power_containment_features &
1227 POWERCONTAINMENT_FEATURE_PkgPwrLimit0x00000004) {
1228 smc_result = smum_send_msg_to_smc(hwmgr,
1229 (uint16_t)(PPSMC_MSG_PkgPwrLimitDisable((uint16_t) 0x186)),
1230 NULL((void *)0));
1231 PP_ASSERT_WITH_CODE((smc_result == 0),do { if (!((smc_result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable PkgPwrTracking in SMC."); result = smc_result
; } } while (0)
1232 "Failed to disable PkgPwrTracking in SMC.",do { if (!((smc_result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable PkgPwrTracking in SMC."); result = smc_result
; } } while (0)
1233 result = smc_result)do { if (!((smc_result == 0))) { printk("\0014" "amdgpu: " "%s\n"
, "Failed to disable PkgPwrTracking in SMC."); result = smc_result
; } } while (0);
1234 }
1235 data->power_containment_features = 0;
1236 }
1237
1238 return result;
1239}
1240
1241int smu7_power_control_set_level(struct pp_hwmgr *hwmgr)
1242{
1243 struct phm_ppt_v1_information *table_info =
1244 (struct phm_ppt_v1_information *)(hwmgr->pptable);
1245 struct phm_cac_tdp_table *cac_table;
1246
1247 int adjust_percent, target_tdp;
1248 int result = 0;
1249
1250 if (hwmgr->pp_table_version == PP_TABLE_V1)
1251 cac_table = table_info->cac_dtp_table;
1252 else
1253 cac_table = hwmgr->dyn_state.cac_dtp_table;
1254 if (PP_CAP(PHM_PlatformCaps_PowerContainment)phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, (
PHM_PlatformCaps_PowerContainment))) {
1255 /* adjustment percentage has already been validated */
1256 adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
1257 hwmgr->platform_descriptor.TDPAdjustment :
1258 (-1 * hwmgr->platform_descriptor.TDPAdjustment);
1259
1260 if (hwmgr->chip_id > CHIP_TONGA)
1261 target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
1262 else
1263 target_tdp = ((100 + adjust_percent) * (int)(cac_table->usConfigurableTDP * 256)) / 100;
1264
1265 result = smu7_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
1266 }
1267
1268 return result;
1269}