/usr/src/sys/dev/pci/drm/display/drm_dp

Bug Summary

File:	dev/pci/drm/display/drm_dp_helper.c
Warning:	line 3883, column 10 Potential leak of memory pointed to by 'bl'

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name drm_dp_helper.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/display/drm_dp_helper.c

/usr/src/sys/dev/pci/drm/display/drm_dp_helper.c

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1/*
* Copyright © 2009 Keith Packard
*
* Permission to use, copy, modify, distribute, and sell this software and its
* documentation for any purpose is hereby granted without fee, provided that
* the above copyright notice appear in all copies and that both that copyright
* notice and this permission notice appear in supporting documentation, and
* that the name of the copyright holders not be used in advertising or
* publicity pertaining to distribution of the software without specific,
* written prior permission.  The copyright holders make no representations
* about the suitability of this software for any purpose.  It is provided "as
* is" without express or implied warranty.
*
* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
* OF THIS SOFTWARE.
*/

23#include <linux/backlight.h>
24#include <linux/delay.h>
25#include <linux/errno.h>
26#include <linux/i2c.h>
27#include <linux/init.h>
28#include <linux/kernel.h>
29#include <linux/module.h>
30#include <linux/sched.h>
31#include <linux/seq_file.h>
32#include <linux/string_helpers.h>
33#include <linux/dynamic_debug.h>

35#include <drm/display/drm_dp_helper.h>
36#include <drm/display/drm_dp_mst_helper.h>
37#include <drm/drm_edid.h>
38#include <drm/drm_print.h>
39#include <drm/drm_vblank.h>
40#include <drm/drm_panel.h>

42#include "drm_dp_helper_internal.h"

44DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
	"DRM_UT_CORE",
	"DRM_UT_DRIVER",
	"DRM_UT_KMS",
	"DRM_UT_PRIME",
	"DRM_UT_ATOMIC",
	"DRM_UT_VBL",
	"DRM_UT_STATE",
	"DRM_UT_LEASE",
	"DRM_UT_DP",
	"DRM_UT_DRMRES");

56struct dp_aux_backlight {
struct backlight_device *base;
struct drm_dp_aux *aux;
struct drm_edp_backlight_info info;
bool_Bool enabled;
61};

63/**
* DOC: dp helpers
*
* These functions contain some common logic and helpers at various abstraction
* levels to deal with Display Port sink devices and related things like DP aux
* channel transfers, EDID reading over DP aux channels, decoding certain DPCD
* blocks, ...
*/

72/* Helpers for DP link training */
73static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE6], int r)
74{
return link_status[r - DP_LANE0_1_STATUS0x202];
76}

78static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE6],
	     int lane)
80{
int i = DP_LANE0_1_STATUS0x202 + (lane >> 1);
int s = (lane & 1) * 4;
u8 l = dp_link_status(link_status, i);

return (l >> s) & 0xf;
86}

88bool_Bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE6],
	  int lane_count)
90{
u8 lane_align;
u8 lane_status;
int lane;

lane_align = dp_link_status(link_status,
		    DP_LANE_ALIGN_STATUS_UPDATED0x204);
if ((lane_align & DP_INTERLANE_ALIGN_DONE(1 << 0)) == 0)
return false0;
for (lane = 0; lane < lane_count; lane++) {
lane_status = dp_get_lane_status(link_status, lane);
if ((lane_status & DP_CHANNEL_EQ_BITS((1 << 0) | (1 << 1) | (1 << 2))) != DP_CHANNEL_EQ_BITS((1 << 0) | (1 << 1) | (1 << 2)))
	return false0;
}
return true1;
105}
106EXPORT_SYMBOL(drm_dp_channel_eq_ok);

108bool_Bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE6],
	      int lane_count)
110{
int lane;
u8 lane_status;

for (lane = 0; lane < lane_count; lane++) {
lane_status = dp_get_lane_status(link_status, lane);
if ((lane_status & DP_LANE_CR_DONE(1 << 0)) == 0)
	return false0;
}
return true1;
120}
121EXPORT_SYMBOL(drm_dp_clock_recovery_ok);

123u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE6],
		     int lane)
125{
int i = DP_ADJUST_REQUEST_LANE0_10x206 + (lane >> 1);
int s = ((lane & 1) ?
 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT4 :
 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT0);
u8 l = dp_link_status(link_status, i);

return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT0;
133}
134EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);

136u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE6],
			  int lane)
138{
int i = DP_ADJUST_REQUEST_LANE0_10x206 + (lane >> 1);
int s = ((lane & 1) ?
 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT6 :
 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT2);
u8 l = dp_link_status(link_status, i);

return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT3;
146}
147EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);

149/* DP 2.0 128b/132b */
150u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE6],
		   int lane)
152{
int i = DP_ADJUST_REQUEST_LANE0_10x206 + (lane >> 1);
int s = ((lane & 1) ?
 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT4 :
 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT0);
u8 l = dp_link_status(link_status, i);

return (l >> s) & 0xf;
160}
161EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset);

163/* DP 2.0 errata for 128b/132b */
164bool_Bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE6],
			  int lane_count)
166{
u8 lane_align, lane_status;
int lane;

lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED0x204);
if (!(lane_align & DP_INTERLANE_ALIGN_DONE(1 << 0)))
return false0;

for (lane = 0; lane < lane_count; lane++) {
lane_status = dp_get_lane_status(link_status, lane);
if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE(1 << 1)))
	return false0;
}
return true1;
180}
181EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done);

183/* DP 2.0 errata for 128b/132b */
184bool_Bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE6],
			int lane_count)
186{
u8 lane_status;
int lane;

for (lane = 0; lane < lane_count; lane++) {
lane_status = dp_get_lane_status(link_status, lane);
if (!(lane_status & DP_LANE_SYMBOL_LOCKED(1 << 2)))
	return false0;
}
return true1;
196}
197EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked);

199/* DP 2.0 errata for 128b/132b */
200bool_Bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE6])
201{
u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED0x204);

return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE(1 << 2);
205}
206EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done);

208/* DP 2.0 errata for 128b/132b */
209bool_Bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE6])
210{
u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED0x204);

return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE(1 << 3);
214}
215EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done);

217/* DP 2.0 errata for 128b/132b */
218bool_Bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE6])
219{
u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED0x204);

return status & DP_128B132B_LT_FAILED(1 << 4);
223}
224EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed);

226static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
227{
if (rd_interval > 4)
drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: invalid AUX interval 0x%02x (max 4)\n"
, aux->name, rd_interval)
	    aux->name, rd_interval)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: invalid AUX interval 0x%02x (max 4)\n"
, aux->name, rd_interval);

if (rd_interval == 0)
return 100;

return rd_interval * 4 * USEC_PER_MSEC1000L;
236}

238static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
239{
if (rd_interval > 4)
drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: invalid AUX interval 0x%02x (max 4)\n"
, aux->name, rd_interval)
	    aux->name, rd_interval)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: invalid AUX interval 0x%02x (max 4)\n"
, aux->name, rd_interval);

if (rd_interval == 0)
return 400;

return rd_interval * 4 * USEC_PER_MSEC1000L;
248}

250static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
251{
switch (rd_interval) {
default:
drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: invalid AUX interval 0x%02x\n"
, aux->name, rd_interval)
	    aux->name, rd_interval)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: invalid AUX interval 0x%02x\n"
, aux->name, rd_interval);
fallthroughdo {} while (0);
case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US0x00:
return 400;
case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS0x01:
return 4000;
case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS0x02:
return 8000;
case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS0x03:
return 12000;
case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS0x04:
return 16000;
case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS0x05:
return 32000;
case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS0x06:
return 64000;
}
272}

274/*
* The link training delays are different for:
*
*  - Clock recovery vs. channel equalization
*  - DPRX vs. LTTPR
*  - 128b/132b vs. 8b/10b
*  - DPCD rev 1.3 vs. later
*
* Get the correct delay in us, reading DPCD if necessary.
*/
284static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
	enum drm_dp_phy dp_phy, bool_Bool uhbr, bool_Bool cr)
286{
int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval);
unsigned int offset;
u8 rd_interval, mask;

if (dp_phy == DP_PHY_DPRX) {
if (uhbr) {
	if (cr)
		return 100;

	offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL0x2216;
	mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK0x7f;
	parse = __128b132b_channel_eq_delay_us;
} else {
	if (cr && dpcd[DP_DPCD_REV0x000] >= DP_DPCD_REV_140x14)
		return 100;

	offset = DP_TRAINING_AUX_RD_INTERVAL0x00e;
	mask = DP_TRAINING_AUX_RD_MASK0x7F;
	if (cr)
		parse = __8b10b_clock_recovery_delay_us;
	else
		parse = __8b10b_channel_eq_delay_us;
}
} else {
if (uhbr) {
	offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy)((0xf0010 + (0xf0060 - 0xf0010) * ((dp_phy) - DP_PHY_LTTPR1))
 - (0xf0010 + (0xf0060 - 0xf0010) * ((DP_PHY_LTTPR1) - DP_PHY_LTTPR1
)) + (0xf0022));
	mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK0x7f;
	parse = __128b132b_channel_eq_delay_us;
} else {
	if (cr)
		return 100;

	offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy)((0xf0010 + (0xf0060 - 0xf0010) * ((dp_phy) - DP_PHY_LTTPR1))
 - (0xf0010 + (0xf0060 - 0xf0010) * ((DP_PHY_LTTPR1) - DP_PHY_LTTPR1
)) + (0xf0020));
	mask = DP_TRAINING_AUX_RD_MASK0x7F;
	parse = __8b10b_channel_eq_delay_us;
}
}

if (offset < DP_RECEIVER_CAP_SIZE0xf) {
rd_interval = dpcd[offset];
} else {
if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) {
	drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: failed rd interval read\n"
, aux->name)
		    aux->name)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: failed rd interval read\n"
, aux->name);
	/* arbitrary default delay */
	return 400;
}
}

return parse(aux, rd_interval & mask);
337}

339int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
		     enum drm_dp_phy dp_phy, bool_Bool uhbr)
341{
return __read_delay(aux, dpcd, dp_phy, uhbr, true1);
343}
344EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay);

346int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
		 enum drm_dp_phy dp_phy, bool_Bool uhbr)
348{
return __read_delay(aux, dpcd, dp_phy, uhbr, false0);
350}
351EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);

353/* Per DP 2.0 Errata */
354int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux)
355{
int unit;
u8 val;

if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL0x2216, &val) != 1) {
drm_err(aux->drm_dev, "%s: failed rd interval read\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: failed rd interval read\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name)
	aux->name)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: failed rd interval read\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name);
/* default to max */
val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK0x7f;
}

unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT(1 << 7)) ? 1 : 2;
val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK0x7f;

return (val + 1) * unit * 1000;
370}
371EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval);

373void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
			    const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
375{
u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL0x00e] &
DP_TRAINING_AUX_RD_MASK0x7F;
int delay_us;

if (dpcd[DP_DPCD_REV0x000] >= DP_DPCD_REV_140x14)
delay_us = 100;
else
delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval);

usleep_range(delay_us, delay_us * 2);
386}
387EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);

389static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
				 u8 rd_interval)
391{
int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval);

usleep_range(delay_us, delay_us * 2);
395}

397void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
			const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
399{
__drm_dp_link_train_channel_eq_delay(aux,
			     dpcd[DP_TRAINING_AUX_RD_INTERVAL0x00e] &
			     DP_TRAINING_AUX_RD_MASK0x7F);
403}
404EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);

406/**
* drm_dp_phy_name() - Get the name of the given DP PHY
* @dp_phy: The DP PHY identifier
*
* Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or
* "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always
* non-NULL and valid.
*
* Returns: Name of the DP PHY.
*/
416const char *drm_dp_phy_name(enum drm_dp_phy dp_phy)
417{
static const char * const phy_names[] = {
[DP_PHY_DPRX] = "DPRX",
[DP_PHY_LTTPR1] = "LTTPR 1",
[DP_PHY_LTTPR2] = "LTTPR 2",
[DP_PHY_LTTPR3] = "LTTPR 3",
[DP_PHY_LTTPR4] = "LTTPR 4",
[DP_PHY_LTTPR5] = "LTTPR 5",
[DP_PHY_LTTPR6] = "LTTPR 6",
[DP_PHY_LTTPR7] = "LTTPR 7",
[DP_PHY_LTTPR8] = "LTTPR 8",
};

if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names)(sizeof((phy_names)) / sizeof((phy_names)[0])) ||
   WARN_ON(!phy_names[dp_phy])({ int __ret = !!(!phy_names[dp_phy]); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!phy_names[dp_phy]", "/usr/src/sys/dev/pci/drm/display/drm_dp_helper.c"
, 431); __builtin_expect(!!(__ret), 0); }))
return "<INVALID DP PHY>";

return phy_names[dp_phy];
435}
436EXPORT_SYMBOL(drm_dp_phy_name);

438void drm_dp_lttpr_link_train_clock_recovery_delay(void)
439{
usleep_range(100, 200);
441}
442EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);

444static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE3], int r)
445{
return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER10xf0020];
447}

449void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
			      const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE3])
451{
u8 interval = dp_lttpr_phy_cap(phy_cap,
		       DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER10xf0020) &
      DP_TRAINING_AUX_RD_MASK0x7F;

__drm_dp_link_train_channel_eq_delay(aux, interval);
457}
458EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);

460u8 drm_dp_link_rate_to_bw_code(int link_rate)
461{
switch (link_rate) {
case 1000000:
return DP_LINK_BW_100x01;
case 1350000:
return DP_LINK_BW_13_50x04;
case 2000000:
return DP_LINK_BW_200x02;
default:
/* Spec says link_bw = link_rate / 0.27Gbps */
return link_rate / 27000;
}
473}
474EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);

476int drm_dp_bw_code_to_link_rate(u8 link_bw)
477{
switch (link_bw) {
case DP_LINK_BW_100x01:
return 1000000;
case DP_LINK_BW_13_50x04:
return 1350000;
case DP_LINK_BW_200x02:
return 2000000;
default:
/* Spec says link_rate = link_bw * 0.27Gbps */
return link_bw * 27000;
}
489}
490EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);

492#define AUX_RETRY_INTERVAL500 500 /* us */

494static inline void
495drm_dp_dump_access(const struct drm_dp_aux *aux,
   u8 request, uint offset, void *buffer, int ret)
497{
const char *arrow = request == DP_AUX_NATIVE_READ0x9 ? "->" : "<-";

if (ret > 0)
drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_DP, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n"
, aux->name, offset, arrow, ret, (((ret)<(20))?(ret):(20
)), buffer)
	   aux->name, offset, arrow, ret, min(ret, 20), buffer)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_DP, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n"
, aux->name, offset, arrow, ret, (((ret)<(20))?(ret):(20
)), buffer);
else
drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_DP, "%s: 0x%05x AUX %s (ret=%3d)\n"
, aux->name, offset, arrow, ret)
	   aux->name, offset, arrow, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_DP, "%s: 0x%05x AUX %s (ret=%3d)\n"
, aux->name, offset, arrow, ret);
506}

508/**
* DOC: dp helpers
*
* The DisplayPort AUX channel is an abstraction to allow generic, driver-
* independent access to AUX functionality. Drivers can take advantage of
* this by filling in the fields of the drm_dp_aux structure.
*
* Transactions are described using a hardware-independent drm_dp_aux_msg
* structure, which is passed into a driver's .transfer() implementation.
* Both native and I2C-over-AUX transactions are supported.
*/

520static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
	      unsigned int offset, void *buffer, size_t size)
522{
struct drm_dp_aux_msg msg;
unsigned int retry, native_reply;
int err = 0, ret = 0;

memset(&msg, 0, sizeof(msg))__builtin_memset((&msg), (0), (sizeof(msg)));
msg.address = offset;
msg.request = request;
msg.buffer = buffer;
msg.size = size;

mutex_lock(&aux->hw_mutex)rw_enter_write(&aux->hw_mutex);

/*
* The specification doesn't give any recommendation on how often to
* retry native transactions. We used to retry 7 times like for
* aux i2c transactions but real world devices this wasn't
* sufficient, bump to 32 which makes Dell 4k monitors happier.
*/
for (retry = 0; retry < 32; retry++) {
if (ret != 0 && ret != -ETIMEDOUT60) {
	usleep_range(AUX_RETRY_INTERVAL500,
		     AUX_RETRY_INTERVAL500 + 100);
}

ret = aux->transfer(aux, &msg);
if (ret >= 0) {
	native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK(0x3 << 0);
	if (native_reply == DP_AUX_NATIVE_REPLY_ACK(0x0 << 0)) {
		if (ret == size)
			goto unlock;

		ret = -EPROTO95;
	} else
		ret = -EIO5;
}

/*
 * We want the error we return to be the error we received on
 * the first transaction, since we may get a different error the
 * next time we retry
 */
if (!err)
	err = ret;
}

drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Too many retries, giving up. First error: %d\n"
, aux->name, err)
    aux->name, err)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Too many retries, giving up. First error: %d\n"
, aux->name, err);
ret = err;

572unlock:
mutex_unlock(&aux->hw_mutex)rw_exit_write(&aux->hw_mutex);
return ret;
575}

577/**
* drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access
* @aux: DisplayPort AUX channel (SST)
* @offset: address of the register to probe
*
* Probe the provided DPCD address by reading 1 byte from it. The function can
* be used to trigger some side-effect the read access has, like waking up the
* sink, without the need for the read-out value.
*
* Returns 0 if the read access suceeded, or a negative error code on failure.
*/
588int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset)
589{
u8 buffer;
int ret;

ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ0x9, offset, &buffer, 1);
WARN_ON(ret == 0)({ int __ret = !!(ret == 0); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "ret == 0", "/usr/src/sys/dev/pci/drm/display/drm_dp_helper.c"
, 594); __builtin_expect(!!(__ret), 0); });

drm_dp_dump_access(aux, DP_AUX_NATIVE_READ0x9, offset, &buffer, ret);

return ret < 0 ? ret : 0;
599}
600EXPORT_SYMBOL(drm_dp_dpcd_probe);

602/**
* drm_dp_dpcd_read() - read a series of bytes from the DPCD
* @aux: DisplayPort AUX channel (SST or MST)
* @offset: address of the (first) register to read
* @buffer: buffer to store the register values
* @size: number of bytes in @buffer
*
* Returns the number of bytes transferred on success, or a negative error
* code on failure. -EIO is returned if the request was NAKed by the sink or
* if the retry count was exceeded. If not all bytes were transferred, this
* function returns -EPROTO. Errors from the underlying AUX channel transfer
* function, with the exception of -EBUSY (which causes the transaction to
* be retried), are propagated to the caller.
*/
616ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
	 void *buffer, size_t size)
618{
int ret;

/*
* HP ZR24w corrupts the first DPCD access after entering power save
* mode. Eg. on a read, the entire buffer will be filled with the same
* byte. Do a throw away read to avoid corrupting anything we care
* about. Afterwards things will work correctly until the monitor
* gets woken up and subsequently re-enters power save mode.
*
* The user pressing any button on the monitor is enough to wake it
* up, so there is no particularly good place to do the workaround.
* We just have to do it before any DPCD access and hope that the
* monitor doesn't power down exactly after the throw away read.
*/
if (!aux->is_remote) {
ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV0x000);
if (ret < 0)
	return ret;
}

if (aux->is_remote)
ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
else
ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ0x9, offset,
			 buffer, size);

drm_dp_dump_access(aux, DP_AUX_NATIVE_READ0x9, offset, buffer, ret);
return ret;
647}
648EXPORT_SYMBOL(drm_dp_dpcd_read);

650/**
* drm_dp_dpcd_write() - write a series of bytes to the DPCD
* @aux: DisplayPort AUX channel (SST or MST)
* @offset: address of the (first) register to write
* @buffer: buffer containing the values to write
* @size: number of bytes in @buffer
*
* Returns the number of bytes transferred on success, or a negative error
* code on failure. -EIO is returned if the request was NAKed by the sink or
* if the retry count was exceeded. If not all bytes were transferred, this
* function returns -EPROTO. Errors from the underlying AUX channel transfer
* function, with the exception of -EBUSY (which causes the transaction to
* be retried), are propagated to the caller.
*/
664ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
	  void *buffer, size_t size)
666{
int ret;

if (aux->is_remote)
ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
else
ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE0x8, offset,
			 buffer, size);

drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE0x8, offset, buffer, ret);
return ret;
677}
678EXPORT_SYMBOL(drm_dp_dpcd_write);

680/**
* drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
* @aux: DisplayPort AUX channel
* @status: buffer to store the link status in (must be at least 6 bytes)
*
* Returns the number of bytes transferred on success or a negative error
* code on failure.
*/
688int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
		 u8 status[DP_LINK_STATUS_SIZE6])
690{
return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS0x202, status,
		DP_LINK_STATUS_SIZE6);
693}
694EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);

696/**
* drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
* @aux: DisplayPort AUX channel
* @dp_phy: the DP PHY to get the link status for
* @link_status: buffer to return the status in
*
* Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
* layout of the returned @link_status matches the DPCD register layout of the
* DPRX PHY link status.
*
* Returns 0 if the information was read successfully or a negative error code
* on failure.
*/
709int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
		     enum drm_dp_phy dp_phy,
		     u8 link_status[DP_LINK_STATUS_SIZE6])
712{
int ret;

if (dp_phy == DP_PHY_DPRX) {
ret = drm_dp_dpcd_read(aux,
		       DP_LANE0_1_STATUS0x202,
		       link_status,
		       DP_LINK_STATUS_SIZE6);

if (ret < 0)
	return ret;

WARN_ON(ret != DP_LINK_STATUS_SIZE)({ int __ret = !!(ret != 6); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "ret != 6", "/usr/src/sys/dev/pci/drm/display/drm_dp_helper.c"
, 724); __builtin_expect(!!(__ret), 0); });

return 0;
}

ret = drm_dp_dpcd_read(aux,
	       DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy)((0xf0010 + (0xf0060 - 0xf0010) * ((dp_phy) - DP_PHY_LTTPR1))
 - (0xf0010 + (0xf0060 - 0xf0010) * ((DP_PHY_LTTPR1) - DP_PHY_LTTPR1
)) + (0xf0030)),
	       link_status,
	       DP_LINK_STATUS_SIZE6 - 1);

if (ret < 0)
return ret;

WARN_ON(ret != DP_LINK_STATUS_SIZE - 1)({ int __ret = !!(ret != 6 - 1); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "ret != 6 - 1", "/usr/src/sys/dev/pci/drm/display/drm_dp_helper.c"
, 737); __builtin_expect(!!(__ret), 0); });

/* Convert the LTTPR to the sink PHY link status layout */
memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],__builtin_memmove((&link_status[0x205 - 0x202 + 1]), (&
link_status[0x205 - 0x202]), (6 - (0x205 - 0x202) - 1))
&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],__builtin_memmove((&link_status[0x205 - 0x202 + 1]), (&
link_status[0x205 - 0x202]), (6 - (0x205 - 0x202) - 1))
DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1)__builtin_memmove((&link_status[0x205 - 0x202 + 1]), (&
link_status[0x205 - 0x202]), (6 - (0x205 - 0x202) - 1));
link_status[DP_SINK_STATUS0x205 - DP_LANE0_1_STATUS0x202] = 0;

return 0;
746}
747EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);

749static bool_Bool is_edid_digital_input_dp(const struct edid *edid)
750{
return edid && edid->revision >= 4 &&
edid->input & DRM_EDID_INPUT_DIGITAL(1 << 7) &&
(edid->input & DRM_EDID_DIGITAL_TYPE_MASK(7 << 0)) == DRM_EDID_DIGITAL_TYPE_DP(5 << 0);
754}

756/**
* drm_dp_downstream_is_type() - is the downstream facing port of certain type?
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
* @type: port type to be checked. Can be:
* 	  %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
* 	  %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
*	  %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
*
* Caveat: Only works with DPCD 1.1+ port caps.
*
* Returns: whether the downstream facing port matches the type.
*/
769bool_Bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
	       const u8 port_cap[4], u8 type)
771{
return drm_dp_is_branch(dpcd) &&
dpcd[DP_DPCD_REV0x000] >= 0x11 &&
(port_cap[0] & DP_DS_PORT_TYPE_MASK(7 << 0)) == type;
775}
776EXPORT_SYMBOL(drm_dp_downstream_is_type);

778/**
* drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
* @edid: EDID
*
* Returns: whether the downstream facing port is TMDS (HDMI/DVI).
*/
786bool_Bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
	       const u8 port_cap[4],
	       const struct edid *edid)
789{
if (dpcd[DP_DPCD_REV0x000] < 0x11) {
switch (dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DWN_STRM_PORT_TYPE_MASK0x06) {
case DP_DWN_STRM_PORT_TYPE_TMDS(2 << 1):
	return true1;
default:
	return false0;
}
}

switch (port_cap[0] & DP_DS_PORT_TYPE_MASK(7 << 0)) {
case DP_DS_PORT_TYPE_DP_DUALMODE5:
if (is_edid_digital_input_dp(edid))
	return false0;
fallthroughdo {} while (0);
case DP_DS_PORT_TYPE_DVI2:
case DP_DS_PORT_TYPE_HDMI3:
return true1;
default:
return false0;
}
810}
811EXPORT_SYMBOL(drm_dp_downstream_is_tmds);

813/**
* drm_dp_send_real_edid_checksum() - send back real edid checksum value
* @aux: DisplayPort AUX channel
* @real_edid_checksum: real edid checksum for the last block
*
* Returns:
* True on success
*/
821bool_Bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
		    u8 real_edid_checksum)
823{
u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;

if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR0x201,
	     &auto_test_req, 1) < 1) {
drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: DPCD failed read at register 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, 0x201)
	aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: DPCD failed read at register 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, 0x201);
return false0;
}
auto_test_req &= DP_AUTOMATED_TEST_REQUEST(1 << 1);

if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST0x218, &link_edid_read, 1) < 1) {
drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: DPCD failed read at register 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, 0x218)
	aux->name, DP_TEST_REQUEST)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: DPCD failed read at register 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, 0x218);
return false0;
}
link_edid_read &= DP_TEST_LINK_EDID_READ(1 << 2);

if (!auto_test_req || !link_edid_read) {
drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Source DUT does not support TEST_EDID_READ\n"
, aux->name)
	    aux->name)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Source DUT does not support TEST_EDID_READ\n"
, aux->name);
return false0;
}

if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR0x201,
	      &auto_test_req, 1) < 1) {
drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: DPCD failed write at register 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, 0x201)
	aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: DPCD failed write at register 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, 0x201);
return false0;
}

/* send back checksum for the last edid extension block data */
if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM0x261,
	      &real_edid_checksum, 1) < 1) {
drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: DPCD failed write at register 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, 0x261)
	aux->name, DP_TEST_EDID_CHECKSUM)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: DPCD failed write at register 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, 0x261);
return false0;
}

test_resp |= DP_TEST_EDID_CHECKSUM_WRITE(1 << 2);
if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE0x260, &test_resp, 1) < 1) {
drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: DPCD failed write at register 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, 0x260)
	aux->name, DP_TEST_RESPONSE)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: DPCD failed write at register 0x%x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, 0x260);
return false0;
}

return true1;
870}
871EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);

873static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
874{
u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT0x007] & DP_PORT_COUNT_MASK0x0f;

if (dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DETAILED_CAP_INFO_AVAILABLE(1 << 4) && port_count > 4)
port_count = 4;

return port_count;
881}

883static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
			  u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
885{
u8 dpcd_ext[DP_RECEIVER_CAP_SIZE0xf];
int ret;

/*
* Prior to DP1.3 the bit represented by
* DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
* If it is set DP_DPCD_REV at 0000h could be at a value less than
* the true capability of the panel. The only way to check is to
* then compare 0000h and 2200h.
*/
if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL0x00e] &
     DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT(1 << 7)))
return 0;

ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV0x2200, &dpcd_ext,
	       sizeof(dpcd_ext));
if (ret < 0)
return ret;
if (ret != sizeof(dpcd_ext))
return -EIO5;

if (dpcd[DP_DPCD_REV0x000] > dpcd_ext[DP_DPCD_REV0x000]) {
drm_dbg_kms(aux->drm_dev,__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n"
, aux->name, dpcd[0x000], dpcd_ext[0x000])
	    "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n"
, aux->name, dpcd[0x000], dpcd_ext[0x000])
	    aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV])__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n"
, aux->name, dpcd[0x000], dpcd_ext[0x000]);
return 0;
}

if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))__builtin_memcmp((dpcd), (dpcd_ext), (sizeof(dpcd_ext))))
return 0;

drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Base DPCD: %*ph\n",
 aux->name, 0xf, dpcd);

memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext))__builtin_memcpy((dpcd), (dpcd_ext), (sizeof(dpcd_ext)));

return 0;
922}

924/**
* drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
* available
* @aux: DisplayPort AUX channel
* @dpcd: Buffer to store the resulting DPCD in
*
* Attempts to read the base DPCD caps for @aux. Additionally, this function
* checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if
* present.
*
* Returns: %0 if the DPCD was read successfully, negative error code
* otherwise.
*/
937int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
	  u8 dpcd[DP_RECEIVER_CAP_SIZE0xf])
939{
int ret;

ret = drm_dp_dpcd_read(aux, DP_DPCD_REV0x000, dpcd, DP_RECEIVER_CAP_SIZE0xf);
if (ret < 0)
return ret;
if (ret != DP_RECEIVER_CAP_SIZE0xf || dpcd[DP_DPCD_REV0x000] == 0)
return -EIO5;

ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
if (ret < 0)
return ret;

drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: DPCD: %*ph\n", aux->
name, 0xf, dpcd);

return ret;
955}
956EXPORT_SYMBOL(drm_dp_read_dpcd_caps);

958/**
* drm_dp_read_downstream_info() - read DPCD downstream port info if available
* @aux: DisplayPort AUX channel
* @dpcd: A cached copy of the port's DPCD
* @downstream_ports: buffer to store the downstream port info in
*
* See also:
* drm_dp_downstream_max_clock()
* drm_dp_downstream_max_bpc()
*
* Returns: 0 if either the downstream port info was read successfully or
* there was no downstream info to read, or a negative error code otherwise.
*/
971int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
		const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
		u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS0x10])
974{
int ret;
u8 len;

memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS)__builtin_memset((downstream_ports), (0), (0x10));

/* No downstream info to read */
if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV0x000] == DP_DPCD_REV_100x10)
return 0;

/* Some branches advertise having 0 downstream ports, despite also advertising they have a
* downstream port present. The DP spec isn't clear on if this is allowed or not, but since
* some branches do it we need to handle it regardless.
*/
len = drm_dp_downstream_port_count(dpcd);
if (!len)
return 0;

if (dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DETAILED_CAP_INFO_AVAILABLE(1 << 4))
len *= 4;

ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_00x80, downstream_ports, len);
if (ret < 0)
return ret;
if (ret != len)
return -EIO5;

drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: DPCD DFP: %*ph\n", aux
->name, len, downstream_ports);

return 0;
1004}
1005EXPORT_SYMBOL(drm_dp_read_downstream_info);

1007/**
* drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
*
* Returns: Downstream facing port max dot clock in kHz on success,
* or 0 if max clock not defined
*/
1015int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
		   const u8 port_cap[4])
1017{
if (!drm_dp_is_branch(dpcd))
return 0;

if (dpcd[DP_DPCD_REV0x000] < 0x11)
return 0;

switch (port_cap[0] & DP_DS_PORT_TYPE_MASK(7 << 0)) {
case DP_DS_PORT_TYPE_VGA1:
if ((dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DETAILED_CAP_INFO_AVAILABLE(1 << 4)) == 0)
	return 0;
return port_cap[1] * 8000;
default:
return 0;
}
1032}
1033EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);

1035/**
* drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
* @edid: EDID
*
* Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,
* or 0 if max TMDS clock not defined
*/
1044int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
		     const u8 port_cap[4],
		     const struct edid *edid)
1047{
if (!drm_dp_is_branch(dpcd))
return 0;

if (dpcd[DP_DPCD_REV0x000] < 0x11) {
switch (dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DWN_STRM_PORT_TYPE_MASK0x06) {
case DP_DWN_STRM_PORT_TYPE_TMDS(2 << 1):
	return 165000;
default:
	return 0;
}
}

switch (port_cap[0] & DP_DS_PORT_TYPE_MASK(7 << 0)) {
case DP_DS_PORT_TYPE_DP_DUALMODE5:
if (is_edid_digital_input_dp(edid))
	return 0;
/*
 * It's left up to the driver to check the
 * DP dual mode adapter's max TMDS clock.
 *
 * Unfortunately it looks like branch devices
 * may not fordward that the DP dual mode i2c
 * access so we just usually get i2c nak :(
 */
fallthroughdo {} while (0);
case DP_DS_PORT_TYPE_HDMI3:
 /*
  * We should perhaps assume 165 MHz when detailed cap
  * info is not available. But looks like many typical
  * branch devices fall into that category and so we'd
  * probably end up with users complaining that they can't
  * get high resolution modes with their favorite dongle.
  *
  * So let's limit to 300 MHz instead since DPCD 1.4
  * HDMI 2.0 DFPs are required to have the detailed cap
  * info. So it's more likely we're dealing with a HDMI 1.4
  * compatible* device here.
  */
if ((dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DETAILED_CAP_INFO_AVAILABLE(1 << 4)) == 0)
	return 300000;
return port_cap[1] * 2500;
case DP_DS_PORT_TYPE_DVI2:
if ((dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DETAILED_CAP_INFO_AVAILABLE(1 << 4)) == 0)
	return 165000;
/* FIXME what to do about DVI dual link? */
return port_cap[1] * 2500;
default:
return 0;
}
1097}
1098EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);

1100/**
* drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
* @edid: EDID
*
* Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,
* or 0 if max TMDS clock not defined
*/
1109int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
		     const u8 port_cap[4],
		     const struct edid *edid)
1112{
if (!drm_dp_is_branch(dpcd))
return 0;

if (dpcd[DP_DPCD_REV0x000] < 0x11) {
switch (dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DWN_STRM_PORT_TYPE_MASK0x06) {
case DP_DWN_STRM_PORT_TYPE_TMDS(2 << 1):
	return 25000;
default:
	return 0;
}
}

switch (port_cap[0] & DP_DS_PORT_TYPE_MASK(7 << 0)) {
case DP_DS_PORT_TYPE_DP_DUALMODE5:
if (is_edid_digital_input_dp(edid))
	return 0;
fallthroughdo {} while (0);
case DP_DS_PORT_TYPE_DVI2:
case DP_DS_PORT_TYPE_HDMI3:
/*
 * Unclear whether the protocol converter could
 * utilize pixel replication. Assume it won't.
 */
return 25000;
default:
return 0;
}
1140}
1141EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);

1143/**
* drm_dp_downstream_max_bpc() - extract downstream facing port max
*                               bits per component
* @dpcd: DisplayPort configuration data
* @port_cap: downstream facing port capabilities
* @edid: EDID
*
* Returns: Max bpc on success or 0 if max bpc not defined
*/
1152int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
	      const u8 port_cap[4],
	      const struct edid *edid)
1155{
if (!drm_dp_is_branch(dpcd))
return 0;

if (dpcd[DP_DPCD_REV0x000] < 0x11) {
switch (dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DWN_STRM_PORT_TYPE_MASK0x06) {
case DP_DWN_STRM_PORT_TYPE_DP(0 << 1):
	return 0;
default:
	return 8;
}
}

switch (port_cap[0] & DP_DS_PORT_TYPE_MASK(7 << 0)) {
case DP_DS_PORT_TYPE_DP0:
return 0;
case DP_DS_PORT_TYPE_DP_DUALMODE5:
if (is_edid_digital_input_dp(edid))
	return 0;
fallthroughdo {} while (0);
case DP_DS_PORT_TYPE_HDMI3:
case DP_DS_PORT_TYPE_DVI2:
case DP_DS_PORT_TYPE_VGA1:
if ((dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DETAILED_CAP_INFO_AVAILABLE(1 << 4)) == 0)
	return 8;

switch (port_cap[2] & DP_DS_MAX_BPC_MASK(3 << 0)) {
case DP_DS_8BPC0:
	return 8;
case DP_DS_10BPC1:
	return 10;
case DP_DS_12BPC2:
	return 12;
case DP_DS_16BPC3:
	return 16;
default:
	return 8;
}
break;
default:
return 8;
}
1197}
1198EXPORT_SYMBOL(drm_dp_downstream_max_bpc);

1200/**
* drm_dp_downstream_420_passthrough() - determine downstream facing port
*                                       YCbCr 4:2:0 pass-through capability
* @dpcd: DisplayPort configuration data
* @port_cap: downstream facing port capabilities
*
* Returns: whether the downstream facing port can pass through YCbCr 4:2:0
*/
1208bool_Bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
		       const u8 port_cap[4])
1210{
if (!drm_dp_is_branch(dpcd))
return false0;

if (dpcd[DP_DPCD_REV0x000] < 0x13)
return false0;

switch (port_cap[0] & DP_DS_PORT_TYPE_MASK(7 << 0)) {
case DP_DS_PORT_TYPE_DP0:
return true1;
case DP_DS_PORT_TYPE_HDMI3:
if ((dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DETAILED_CAP_INFO_AVAILABLE(1 << 4)) == 0)
	return false0;

return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH(1 << 2);
default:
return false0;
}
1228}
1229EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);

1231/**
* drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
*                                             YCbCr 4:4:4->4:2:0 conversion capability
* @dpcd: DisplayPort configuration data
* @port_cap: downstream facing port capabilities
*
* Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0
*/
1239bool_Bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
			     const u8 port_cap[4])
1241{
if (!drm_dp_is_branch(dpcd))
return false0;

if (dpcd[DP_DPCD_REV0x000] < 0x13)
return false0;

switch (port_cap[0] & DP_DS_PORT_TYPE_MASK(7 << 0)) {
case DP_DS_PORT_TYPE_HDMI3:
if ((dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DETAILED_CAP_INFO_AVAILABLE(1 << 4)) == 0)
	return false0;

return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV(1 << 4);
default:
return false0;
}
1257}
1258EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);

1260/**
* drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
*                                               RGB->YCbCr conversion capability
* @dpcd: DisplayPort configuration data
* @port_cap: downstream facing port capabilities
* @color_spc: Colorspace for which conversion cap is sought
*
* Returns: whether the downstream facing port can convert RGB->YCbCr for a given
* colorspace.
*/
1270bool_Bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
			       const u8 port_cap[4],
			       u8 color_spc)
1273{
if (!drm_dp_is_branch(dpcd))
return false0;

if (dpcd[DP_DPCD_REV0x000] < 0x13)
return false0;

switch (port_cap[0] & DP_DS_PORT_TYPE_MASK(7 << 0)) {
case DP_DS_PORT_TYPE_HDMI3:
if ((dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DETAILED_CAP_INFO_AVAILABLE(1 << 4)) == 0)
	return false0;

return port_cap[3] & color_spc;
default:
return false0;
}
1289}
1290EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion);

1292/**
* drm_dp_downstream_mode() - return a mode for downstream facing port
* @dev: DRM device
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
*
* Provides a suitable mode for downstream facing ports without EDID.
*
* Returns: A new drm_display_mode on success or NULL on failure
*/
1302struct drm_display_mode *
1303drm_dp_downstream_mode(struct drm_device *dev,
       const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
       const u8 port_cap[4])

1307{
u8 vic;

if (!drm_dp_is_branch(dpcd))
return NULL((void *)0);

if (dpcd[DP_DPCD_REV0x000] < 0x11)
return NULL((void *)0);

switch (port_cap[0] & DP_DS_PORT_TYPE_MASK(7 << 0)) {
case DP_DS_PORT_TYPE_NON_EDID4:
switch (port_cap[0] & DP_DS_NON_EDID_MASK(0xf << 4)) {
case DP_DS_NON_EDID_720x480i_60(1 << 4):
	vic = 6;
	break;
case DP_DS_NON_EDID_720x480i_50(2 << 4):
	vic = 21;
	break;
case DP_DS_NON_EDID_1920x1080i_60(3 << 4):
	vic = 5;
	break;
case DP_DS_NON_EDID_1920x1080i_50(4 << 4):
	vic = 20;
	break;
case DP_DS_NON_EDID_1280x720_60(5 << 4):
	vic = 4;
	break;
case DP_DS_NON_EDID_1280x720_50(7 << 4):
	vic = 19;
	break;
default:
	return NULL((void *)0);
}
return drm_display_mode_from_cea_vic(dev, vic);
default:
return NULL((void *)0);
}
1344}
1345EXPORT_SYMBOL(drm_dp_downstream_mode);

1347/**
* drm_dp_downstream_id() - identify branch device
* @aux: DisplayPort AUX channel
* @id: DisplayPort branch device id
*
* Returns branch device id on success or NULL on failure
*/
1354int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
1355{
return drm_dp_dpcd_read(aux, DP_BRANCH_ID0x503, id, 6);
1357}
1358EXPORT_SYMBOL(drm_dp_downstream_id);

1360/**
* drm_dp_downstream_debug() - debug DP branch devices
* @m: pointer for debugfs file
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
* @edid: EDID
* @aux: DisplayPort AUX channel
*
*/
1369void drm_dp_downstream_debug(struct seq_file *m,
	     const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
	     const u8 port_cap[4],
	     const struct edid *edid,
	     struct drm_dp_aux *aux)
1374{
bool_Bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] &
		 DP_DETAILED_CAP_INFO_AVAILABLE(1 << 4);
int clk;
int bpc;
char id[7];
int len;
uint8_t rev[2];
int type = port_cap[0] & DP_DS_PORT_TYPE_MASK(7 << 0);
bool_Bool branch_device = drm_dp_is_branch(dpcd);

seq_printf(m, "\tDP branch device present: %s\n",
   str_yes_no(branch_device));

if (!branch_device)
return;

switch (type) {
case DP_DS_PORT_TYPE_DP0:
seq_puts(m, "\t\tType: DisplayPort\n");
break;
case DP_DS_PORT_TYPE_VGA1:
seq_puts(m, "\t\tType: VGA\n");
break;
case DP_DS_PORT_TYPE_DVI2:
seq_puts(m, "\t\tType: DVI\n");
break;
case DP_DS_PORT_TYPE_HDMI3:
seq_puts(m, "\t\tType: HDMI\n");
break;
case DP_DS_PORT_TYPE_NON_EDID4:
seq_puts(m, "\t\tType: others without EDID support\n");
break;
case DP_DS_PORT_TYPE_DP_DUALMODE5:
seq_puts(m, "\t\tType: DP++\n");
break;
case DP_DS_PORT_TYPE_WIRELESS6:
seq_puts(m, "\t\tType: Wireless\n");
break;
default:
seq_puts(m, "\t\tType: N/A\n");
}

memset(id, 0, sizeof(id))__builtin_memset((id), (0), (sizeof(id)));
drm_dp_downstream_id(aux, id);
seq_printf(m, "\t\tID: %s\n", id);

len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV0x509, &rev[0], 1);
if (len > 0)
seq_printf(m, "\t\tHW: %d.%d\n",
	   (rev[0] & 0xf0) >> 4, rev[0] & 0xf);

len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV0x50A, rev, 2);
if (len > 0)
seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);

if (detailed_cap_info) {
clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
if (clk > 0)
	seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);

clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, edid);
if (clk > 0)
	seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);

clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, edid);
if (clk > 0)
	seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);

bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, edid);

if (bpc > 0)
	seq_printf(m, "\t\tMax bpc: %d\n", bpc);
}
1448}
1449EXPORT_SYMBOL(drm_dp_downstream_debug);

1451/**
* drm_dp_subconnector_type() - get DP branch device type
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
*/
1456enum drm_mode_subconnector
1457drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
	 const u8 port_cap[4])
1459{
int type;
if (!drm_dp_is_branch(dpcd))
return DRM_MODE_SUBCONNECTOR_Native;
/* DP 1.0 approach */
if (dpcd[DP_DPCD_REV0x000] == DP_DPCD_REV_100x10) {
type = dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] &
       DP_DWN_STRM_PORT_TYPE_MASK0x06;

switch (type) {
case DP_DWN_STRM_PORT_TYPE_TMDS(2 << 1):
	/* Can be HDMI or DVI-D, DVI-D is a safer option */
	return DRM_MODE_SUBCONNECTOR_DVID;
case DP_DWN_STRM_PORT_TYPE_ANALOG(1 << 1):
	/* Can be VGA or DVI-A, VGA is more popular */
	return DRM_MODE_SUBCONNECTOR_VGA;
case DP_DWN_STRM_PORT_TYPE_DP(0 << 1):
	return DRM_MODE_SUBCONNECTOR_DisplayPort;
case DP_DWN_STRM_PORT_TYPE_OTHER(3 << 1):
default:
	return DRM_MODE_SUBCONNECTOR_Unknown;
}
}
type = port_cap[0] & DP_DS_PORT_TYPE_MASK(7 << 0);

switch (type) {
case DP_DS_PORT_TYPE_DP0:
case DP_DS_PORT_TYPE_DP_DUALMODE5:
return DRM_MODE_SUBCONNECTOR_DisplayPort;
case DP_DS_PORT_TYPE_VGA1:
return DRM_MODE_SUBCONNECTOR_VGA;
case DP_DS_PORT_TYPE_DVI2:
return DRM_MODE_SUBCONNECTOR_DVID;
case DP_DS_PORT_TYPE_HDMI3:
return DRM_MODE_SUBCONNECTOR_HDMIA;
case DP_DS_PORT_TYPE_WIRELESS6:
return DRM_MODE_SUBCONNECTOR_Wireless;
case DP_DS_PORT_TYPE_NON_EDID4:
default:
return DRM_MODE_SUBCONNECTOR_Unknown;
}
1500}
1501EXPORT_SYMBOL(drm_dp_subconnector_type);

1503/**
* drm_dp_set_subconnector_property - set subconnector for DP connector
* @connector: connector to set property on
* @status: connector status
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
*
* Called by a driver on every detect event.
*/
1512void drm_dp_set_subconnector_property(struct drm_connector *connector,
		      enum drm_connector_status status,
		      const u8 *dpcd,
		      const u8 port_cap[4])
1516{
enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;

if (status == connector_status_connected)
subconnector = drm_dp_subconnector_type(dpcd, port_cap);
drm_object_property_set_value(&connector->base,
	connector->dev->mode_config.dp_subconnector_property,
	subconnector);
1524}
1525EXPORT_SYMBOL(drm_dp_set_subconnector_property);

1527/**
* drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
* count
* @connector: The DRM connector to check
* @dpcd: A cached copy of the connector's DPCD RX capabilities
* @desc: A cached copy of the connector's DP descriptor
*
* See also: drm_dp_read_sink_count()
*
* Returns: %True if the (e)DP connector has a valid sink count that should
* be probed, %false otherwise.
*/
1539bool_Bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
		const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
		const struct drm_dp_desc *desc)
1542{
/* Some eDP panels don't set a valid value for the sink count */
return connector->connector_type != DRM_MODE_CONNECTOR_eDP14 &&
dpcd[DP_DPCD_REV0x000] >= DP_DPCD_REV_110x11 &&
dpcd[DP_DOWNSTREAMPORT_PRESENT0x005] & DP_DWN_STRM_PORT_PRESENT(1 << 0) &&
!drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT);
1548}
1549EXPORT_SYMBOL(drm_dp_read_sink_count_cap);

1551/**
* drm_dp_read_sink_count() - Retrieve the sink count for a given sink
* @aux: The DP AUX channel to use
*
* See also: drm_dp_read_sink_count_cap()
*
* Returns: The current sink count reported by @aux, or a negative error code
* otherwise.
*/
1560int drm_dp_read_sink_count(struct drm_dp_aux *aux)
1561{
u8 count;
int ret;

ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT0x200, &count);
if (ret < 0)
return ret;
if (ret != 1)
return -EIO5;

return DP_GET_SINK_COUNT(count)((((count) & 0x80) >> 1) | ((count) & 0x3f));
1572}
1573EXPORT_SYMBOL(drm_dp_read_sink_count);

1575/*
* I2C-over-AUX implementation
*/

1579static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
1580{
return I2C_FUNC_I2C0 | I2C_FUNC_SMBUS_EMUL0 |
      I2C_FUNC_SMBUS_READ_BLOCK_DATA0 |
      I2C_FUNC_SMBUS_BLOCK_PROC_CALL0 |
      I2C_FUNC_10BIT_ADDR0;
1585}

1587static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
1588{
/*
* In case of i2c defer or short i2c ack reply to a write,
* we need to switch to WRITE_STATUS_UPDATE to drain the
* rest of the message
*/
if ((msg->request & ~DP_AUX_I2C_MOT0x4) == DP_AUX_I2C_WRITE0x0) {
msg->request &= DP_AUX_I2C_MOT0x4;
msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE0x2;
}
1598}

1600#define AUX_PRECHARGE_LEN10 10 /* 10 to 16 */
1601#define AUX_SYNC_LEN(16 + 4) (16 + 4) /* preamble + AUX_SYNC_END */
1602#define AUX_STOP_LEN4 4
1603#define AUX_CMD_LEN4 4
1604#define AUX_ADDRESS_LEN20 20
1605#define AUX_REPLY_PAD_LEN4 4
1606#define AUX_LENGTH_LEN8 8

1608/*
* Calculate the duration of the AUX request/reply in usec. Gives the
* "best" case estimate, ie. successful while as short as possible.
*/
1612static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
1613{
int len = AUX_PRECHARGE_LEN10 + AUX_SYNC_LEN(16 + 4) + AUX_STOP_LEN4 +
AUX_CMD_LEN4 + AUX_ADDRESS_LEN20 + AUX_LENGTH_LEN8;

if ((msg->request & DP_AUX_I2C_READ0x1) == 0)
len += msg->size * 8;

return len;
1621}

1623static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
1624{
int len = AUX_PRECHARGE_LEN10 + AUX_SYNC_LEN(16 + 4) + AUX_STOP_LEN4 +
AUX_CMD_LEN4 + AUX_REPLY_PAD_LEN4;

/*
* For read we expect what was asked. For writes there will
* be 0 or 1 data bytes. Assume 0 for the "best" case.
*/
if (msg->request & DP_AUX_I2C_READ0x1)
len += msg->size * 8;

return len;
1636}

1638#define I2C_START_LEN1 1
1639#define I2C_STOP_LEN1 1
1640#define I2C_ADDR_LEN9 9 /* ADDRESS + R/W + ACK/NACK */
1641#define I2C_DATA_LEN9 9 /* DATA + ACK/NACK */

1643/*
* Calculate the length of the i2c transfer in usec, assuming
* the i2c bus speed is as specified. Gives the "worst"
* case estimate, ie. successful while as long as possible.
* Doesn't account the "MOT" bit, and instead assumes each
* message includes a START, ADDRESS and STOP. Neither does it
* account for additional random variables such as clock stretching.
*/
1651static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
		   int i2c_speed_khz)
1653{
/* AUX bitrate is 1MHz, i2c bitrate as specified */
return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +((((1 + 9 + msg->size * 9 + 1) * 1000) + ((i2c_speed_khz) -
 1)) / (i2c_speed_khz))
	     msg->size * I2C_DATA_LEN +((((1 + 9 + msg->size * 9 + 1) * 1000) + ((i2c_speed_khz) -
 1)) / (i2c_speed_khz))
	     I2C_STOP_LEN) * 1000, i2c_speed_khz)((((1 + 9 + msg->size * 9 + 1) * 1000) + ((i2c_speed_khz) -
 1)) / (i2c_speed_khz));
1658}

1660/*
* Determine how many retries should be attempted to successfully transfer
* the specified message, based on the estimated durations of the
* i2c and AUX transfers.
*/
1665static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
	      int i2c_speed_khz)
1667{
int aux_time_us = drm_dp_aux_req_duration(msg) +
drm_dp_aux_reply_duration(msg);
int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);

return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL)(((i2c_time_us) + ((aux_time_us + 500) - 1)) / (aux_time_us +
 500));
1673}

1675/*
* FIXME currently assumes 10 kHz as some real world devices seem
* to require it. We should query/set the speed via DPCD if supported.
*/
1679static int dp_aux_i2c_speed_khz __read_mostly = 10;
1680module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
1681MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");

1684/*
* Transfer a single I2C-over-AUX message and handle various error conditions,
* retrying the transaction as appropriate.  It is assumed that the
* &drm_dp_aux.transfer function does not modify anything in the msg other than the
* reply field.
*
* Returns bytes transferred on success, or a negative error code on failure.
*/
1692static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1693{
unsigned int retry, defer_i2c;
int ret;
/*
* DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
* is required to retry at least seven times upon receiving AUX_DEFER
* before giving up the AUX transaction.
*
* We also try to account for the i2c bus speed.
*/
int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz))(((7)>(drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)))
?(7):(drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)));

for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
ret = aux->transfer(aux, msg);
if (ret < 0) {
	if (ret == -EBUSY16)
		continue;

	/*
	 * While timeouts can be errors, they're usually normal
	 * behavior (for instance, when a driver tries to
	 * communicate with a non-existent DisplayPort device).
	 * Avoid spamming the kernel log with timeout errors.
	 */
	if (ret == -ETIMEDOUT60)
		drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n",({ static struct ratelimit_state rs_; const struct drm_device
 *drm_ = (aux->drm_dev); if (drm_debug_enabled_raw(DRM_UT_KMS
) && __ratelimit(&rs_)) drm_dev_printk(drm_ ? drm_
->dev : ((void *)0), "\0017", "%s: transaction timed out\n"
, aux->name); })
					aux->name)({ static struct ratelimit_state rs_; const struct drm_device
 *drm_ = (aux->drm_dev); if (drm_debug_enabled_raw(DRM_UT_KMS
) && __ratelimit(&rs_)) drm_dev_printk(drm_ ? drm_
->dev : ((void *)0), "\0017", "%s: transaction timed out\n"
, aux->name); });
	else
		drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: transaction failed: %d\n"
, aux->name, ret)
			    aux->name, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: transaction failed: %d\n"
, aux->name, ret);
	return ret;
}


switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK(0x3 << 0)) {
case DP_AUX_NATIVE_REPLY_ACK(0x0 << 0):
	/*
	 * For I2C-over-AUX transactions this isn't enough, we
	 * need to check for the I2C ACK reply.
	 */
	break;

case DP_AUX_NATIVE_REPLY_NACK(0x1 << 0):
	drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: native nack (result=%d, size=%zu)\n"
, aux->name, ret, msg->size)
		    aux->name, ret, msg->size)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: native nack (result=%d, size=%zu)\n"
, aux->name, ret, msg->size);
	return -EREMOTEIO5;

case DP_AUX_NATIVE_REPLY_DEFER(0x2 << 0):
	drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: native defer\n", aux
->name);
	/*
	 * We could check for I2C bit rate capabilities and if
	 * available adjust this interval. We could also be
	 * more careful with DP-to-legacy adapters where a
	 * long legacy cable may force very low I2C bit rates.
	 *
	 * For now just defer for long enough to hopefully be
	 * safe for all use-cases.
	 */
	usleep_range(AUX_RETRY_INTERVAL500, AUX_RETRY_INTERVAL500 + 100);
	continue;

default:
	drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: invalid native reply %#04x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, msg->reply)
		aux->name, msg->reply)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: invalid native reply %#04x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, msg->reply);
	return -EREMOTEIO5;
}

switch (msg->reply & DP_AUX_I2C_REPLY_MASK(0x3 << 2)) {
case DP_AUX_I2C_REPLY_ACK(0x0 << 2):
	/*
	 * Both native ACK and I2C ACK replies received. We
	 * can assume the transfer was successful.
	 */
	if (ret != msg->size)
		drm_dp_i2c_msg_write_status_update(msg);
	return ret;

case DP_AUX_I2C_REPLY_NACK(0x1 << 2):
	drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: I2C nack (result=%d, size=%zu)\n"
, aux->name, ret, msg->size)
		    aux->name, ret, msg->size)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: I2C nack (result=%d, size=%zu)\n"
, aux->name, ret, msg->size);
	aux->i2c_nack_count++;
	return -EREMOTEIO5;

case DP_AUX_I2C_REPLY_DEFER(0x2 << 2):
	drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: I2C defer\n", aux->
name);
	/* DP Compliance Test 4.2.2.5 Requirement:
	 * Must have at least 7 retries for I2C defers on the
	 * transaction to pass this test
	 */
	aux->i2c_defer_count++;
	if (defer_i2c < 7)
		defer_i2c++;
	usleep_range(AUX_RETRY_INTERVAL500, AUX_RETRY_INTERVAL500 + 100);
	drm_dp_i2c_msg_write_status_update(msg);

	continue;

default:
	drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: invalid I2C reply %#04x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, msg->reply)
		aux->name, msg->reply)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: invalid I2C reply %#04x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, msg->reply);
	return -EREMOTEIO5;
}
}

drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Too many retries, giving up\n"
, aux->name);
return -EREMOTEIO5;
1799}

1801static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
		       const struct i2c_msg *i2c_msg)
1803{
msg->request = (i2c_msg->flags & I2C_M_RD0x0001) ?
DP_AUX_I2C_READ0x1 : DP_AUX_I2C_WRITE0x0;
if (!(i2c_msg->flags & I2C_M_STOP0x0004))
msg->request |= DP_AUX_I2C_MOT0x4;
1808}

1810/*
* Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
*
* Returns an error code on failure, or a recommended transfer size on success.
*/
1815static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
1816{
int err, ret = orig_msg->size;
struct drm_dp_aux_msg msg = *orig_msg;

while (msg.size > 0) {
err = drm_dp_i2c_do_msg(aux, &msg);
if (err <= 0)
	return err == 0 ? -EPROTO95 : err;

if (err < msg.size && err < ret) {
	drm_dbg_kms(aux->drm_dev,__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Partial I2C reply: requested %zu bytes got %d bytes\n"
, aux->name, msg.size, err)
		    "%s: Partial I2C reply: requested %zu bytes got %d bytes\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Partial I2C reply: requested %zu bytes got %d bytes\n"
, aux->name, msg.size, err)
		    aux->name, msg.size, err)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Partial I2C reply: requested %zu bytes got %d bytes\n"
, aux->name, msg.size, err);
	ret = err;
}

msg.size -= err;
msg.buffer += err;
}

return ret;
1837}

1839/*
* Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
* packets to be as large as possible. If not, the I2C transactions never
* succeed. Hence the default is maximum.
*/
1844static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES16;
1845module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
1846MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");

1849static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
	   int num)
1851{
struct drm_dp_aux *aux = adapter->algo_data;
unsigned int i, j;
unsigned transfer_size;
struct drm_dp_aux_msg msg;
int err = 0;

dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES)({ __typeof(dp_aux_i2c_transfer_size) __min_a = (({ __typeof(
dp_aux_i2c_transfer_size) __max_a = (dp_aux_i2c_transfer_size
); __typeof(dp_aux_i2c_transfer_size) __max_b = (1); __max_a >
 __max_b ? __max_a : __max_b; })); __typeof(dp_aux_i2c_transfer_size
) __min_b = (16); __min_a < __min_b ? __min_a : __min_b; }
);

memset(&msg, 0, sizeof(msg))__builtin_memset((&msg), (0), (sizeof(msg)));

for (i = 0; i < num; i++) {
msg.address = msgs[i].addr;
drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
/* Send a bare address packet to start the transaction.
 * Zero sized messages specify an address only (bare
 * address) transaction.
 */
msg.buffer = NULL((void *)0);
msg.size = 0;
err = drm_dp_i2c_do_msg(aux, &msg);

/*
 * Reset msg.request in case in case it got
 * changed into a WRITE_STATUS_UPDATE.
 */
drm_dp_i2c_msg_set_request(&msg, &msgs[i]);

if (err < 0)
	break;
/* We want each transaction to be as large as possible, but
 * we'll go to smaller sizes if the hardware gives us a
 * short reply.
 */
transfer_size = dp_aux_i2c_transfer_size;
for (j = 0; j < msgs[i].len; j += msg.size) {
	msg.buffer = msgs[i].buf + j;
	msg.size = min(transfer_size, msgs[i].len - j)(((transfer_size)<(msgs[i].len - j))?(transfer_size):(msgs
[i].len - j));

	err = drm_dp_i2c_drain_msg(aux, &msg);

	/*
	 * Reset msg.request in case in case it got
	 * changed into a WRITE_STATUS_UPDATE.
	 */
	drm_dp_i2c_msg_set_request(&msg, &msgs[i]);

	if (err < 0)
		break;
	transfer_size = err;
}
if (err < 0)
	break;
}
if (err >= 0)
err = num;
/* Send a bare address packet to close out the transaction.
* Zero sized messages specify an address only (bare
* address) transaction.
*/
msg.request &= ~DP_AUX_I2C_MOT0x4;
msg.buffer = NULL((void *)0);
msg.size = 0;
(void)drm_dp_i2c_do_msg(aux, &msg);

return err;
1917}

1919static const struct i2c_algorithm drm_dp_i2c_algo = {
.functionality = drm_dp_i2c_functionality,
.master_xfer = drm_dp_i2c_xfer,
1922};

1924static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
1925{
return container_of(i2c, struct drm_dp_aux, ddc)({ const __typeof( ((struct drm_dp_aux *)0)->ddc ) *__mptr
 = (i2c); (struct drm_dp_aux *)( (char *)__mptr - __builtin_offsetof
(struct drm_dp_aux, ddc) );});
1927}

1929static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
1930{
mutex_lock(&i2c_to_aux(i2c)->hw_mutex)rw_enter_write(&i2c_to_aux(i2c)->hw_mutex);
1932}

1934static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
1935{
return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex)(rw_enter(&i2c_to_aux(i2c)->hw_mutex, 0x0001UL | 0x0040UL
) == 0);
1937}

1939static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
1940{
mutex_unlock(&i2c_to_aux(i2c)->hw_mutex)rw_exit_write(&i2c_to_aux(i2c)->hw_mutex);
1942}

1944static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
.lock_bus = lock_bus,
.trylock_bus = trylock_bus,
.unlock_bus = unlock_bus,
1948};

1950static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
1951{
u8 buf, count;
int ret;

ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK0x270, &buf);
if (ret < 0)
return ret;

WARN_ON(!(buf & DP_TEST_SINK_START))({ int __ret = !!(!(buf & (1 << 0))); if (__ret) printf
("WARNING %s failed at %s:%d\n", "!(buf & (1 << 0))"
, "/usr/src/sys/dev/pci/drm/display/drm_dp_helper.c", 1959); __builtin_expect
(!!(__ret), 0); });

ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC0x246, &buf);
if (ret < 0)
return ret;

count = buf & DP_TEST_COUNT_MASK0xf;
if (count == aux->crc_count)
return -EAGAIN35; /* No CRC yet */

aux->crc_count = count;

/*
* At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
* per component (RGB or CrYCb).
*/
ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR0x240, crc, 6);
if (ret < 0)
return ret;

return 0;
1980}

1982static void drm_dp_aux_crc_work(struct work_struct *work)
1983{
struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,({ const __typeof( ((struct drm_dp_aux *)0)->crc_work ) *__mptr
 = (work); (struct drm_dp_aux *)( (char *)__mptr - __builtin_offsetof
(struct drm_dp_aux, crc_work) );})
			      crc_work)({ const __typeof( ((struct drm_dp_aux *)0)->crc_work ) *__mptr
 = (work); (struct drm_dp_aux *)( (char *)__mptr - __builtin_offsetof
(struct drm_dp_aux, crc_work) );});
struct drm_crtc *crtc;
u8 crc_bytes[6];
uint32_t crcs[3];
int ret;

if (WARN_ON(!aux->crtc)({ int __ret = !!(!aux->crtc); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "!aux->crtc", "/usr/src/sys/dev/pci/drm/display/drm_dp_helper.c"
, 1991); __builtin_expect(!!(__ret), 0); }))
return;

crtc = aux->crtc;
while (crtc->crc.opened) {
drm_crtc_wait_one_vblank(crtc);
if (!crtc->crc.opened)
	break;

ret = drm_dp_aux_get_crc(aux, crc_bytes);
if (ret == -EAGAIN35) {
	usleep_range(1000, 2000);
	ret = drm_dp_aux_get_crc(aux, crc_bytes);
}

if (ret == -EAGAIN35) {
	drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Get CRC failed after retrying: %d\n"
, aux->name, ret)
		    aux->name, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Get CRC failed after retrying: %d\n"
, aux->name, ret);
	continue;
} else if (ret) {
	drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to get a CRC: %d\n"
, aux->name, ret);
	continue;
}

crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
drm_crtc_add_crc_entry(crtc, false0, 0, crcs);
}
2020}

2022/**
* drm_dp_remote_aux_init() - minimally initialise a remote aux channel
* @aux: DisplayPort AUX channel
*
* Used for remote aux channel in general. Merely initialize the crc work
* struct.
*/
2029void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
2030{
INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2032}
2033EXPORT_SYMBOL(drm_dp_remote_aux_init);

2035/**
* drm_dp_aux_init() - minimally initialise an aux channel
* @aux: DisplayPort AUX channel
*
* If you need to use the drm_dp_aux's i2c adapter prior to registering it with
* the outside world, call drm_dp_aux_init() first. For drivers which are
* grandparents to their AUX adapters (e.g. the AUX adapter is parented by a
* &drm_connector), you must still call drm_dp_aux_register() once the connector
* has been registered to allow userspace access to the auxiliary DP channel.
* Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as
* early as possible so that the &drm_device that corresponds to the AUX adapter
* may be mentioned in debugging output from the DRM DP helpers.
*
* For devices which use a separate platform device for their AUX adapters, this
* may be called as early as required by the driver.
*
*/
2052void drm_dp_aux_init(struct drm_dp_aux *aux)
2053{
/*
* witness does not understand mutex_lock_nest_lock()
* order reversal in i915 with this lock
*/
rw_init_flags(&aux->hw_mutex, "drmdp", RWL_NOWITNESS)_rw_init_flags(&aux->hw_mutex, "drmdp", 0x02, ((void *
)0));
rw_init(&aux->cec.lock, "drmcec")_rw_init_flags(&aux->cec.lock, "drmcec", 0, ((void *)0
));
INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);

aux->ddc.algo = &drm_dp_i2c_algo;
aux->ddc.algo_data = aux;
aux->ddc.retries = 3;

aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
2067}
2068EXPORT_SYMBOL(drm_dp_aux_init);

2070/**
* drm_dp_aux_register() - initialise and register aux channel
* @aux: DisplayPort AUX channel
*
* Automatically calls drm_dp_aux_init() if this hasn't been done yet. This
* should only be called once the parent of @aux, &drm_dp_aux.dev, is
* initialized. For devices which are grandparents of their AUX channels,
* &drm_dp_aux.dev will typically be the &drm_connector &device which
* corresponds to @aux. For these devices, it's advised to call
* drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to
* call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister.
* Functions which don't follow this will likely Oops when
* %CONFIG_DRM_DP_AUX_CHARDEV is enabled.
*
* For devices where the AUX channel is a device that exists independently of
* the &drm_device that uses it, such as SoCs and bridge devices, it is
* recommended to call drm_dp_aux_register() after a &drm_device has been
* assigned to &drm_dp_aux.drm_dev, and likewise to call
* drm_dp_aux_unregister() once the &drm_device should no longer be associated
* with the AUX channel (e.g. on bridge detach).
*
* Drivers which need to use the aux channel before either of the two points
* mentioned above need to call drm_dp_aux_init() in order to use the AUX
* channel before registration.
*
* Returns 0 on success or a negative error code on failure.
*/
2097int drm_dp_aux_register(struct drm_dp_aux *aux)
2098{
int ret;

WARN_ON_ONCE(!aux->drm_dev)({ static int __warned; int __ret = !!(!aux->drm_dev); if (
__ret && !__warned) { printf("WARNING %s failed at %s:%d\n"
, "!aux->drm_dev", "/usr/src/sys/dev/pci/drm/display/drm_dp_helper.c"
, 2101); __warned = 1; } __builtin_expect(!!(__ret), 0); });

if (!aux->ddc.algo)
drm_dp_aux_init(aux);

2106#ifdef __linux__
aux->ddc.class = I2C_CLASS_DDC;
aux->ddc.owner = THIS_MODULE((void *)0);
aux->ddc.dev.parent = aux->dev;
2110#endif

strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev)"",
sizeof(aux->ddc.name));

ret = drm_dp_aux_register_devnode(aux);
if (ret)
return ret;

ret = i2c_add_adapter(&aux->ddc);
if (ret) {
drm_dp_aux_unregister_devnode(aux);
return ret;
}

return 0;
2126}
2127EXPORT_SYMBOL(drm_dp_aux_register);

2129/**
* drm_dp_aux_unregister() - unregister an AUX adapter
* @aux: DisplayPort AUX channel
*/
2133void drm_dp_aux_unregister(struct drm_dp_aux *aux)
2134{
drm_dp_aux_unregister_devnode(aux);
i2c_del_adapter(&aux->ddc);
2137}
2138EXPORT_SYMBOL(drm_dp_aux_unregister);

2140#define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT1] = (x)

2142/**
* drm_dp_psr_setup_time() - PSR setup in time usec
* @psr_cap: PSR capabilities from DPCD
*
* Returns:
* PSR setup time for the panel in microseconds,  negative
* error code on failure.
*/
2150int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE2])
2151{
static const u16 psr_setup_time_us[] = {
PSR_SETUP_TIME(330),
PSR_SETUP_TIME(275),
PSR_SETUP_TIME(220),
PSR_SETUP_TIME(165),
PSR_SETUP_TIME(110),
PSR_SETUP_TIME(55),
PSR_SETUP_TIME(0),
};
int i;

i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK(7 << 1)) >> DP_PSR_SETUP_TIME_SHIFT1;
if (i >= ARRAY_SIZE(psr_setup_time_us)(sizeof((psr_setup_time_us)) / sizeof((psr_setup_time_us)[0])
))
return -EINVAL22;

return psr_setup_time_us[i];
2168}
2169EXPORT_SYMBOL(drm_dp_psr_setup_time);

2171#undef PSR_SETUP_TIME

2173/**
* drm_dp_start_crc() - start capture of frame CRCs
* @aux: DisplayPort AUX channel
* @crtc: CRTC displaying the frames whose CRCs are to be captured
*
* Returns 0 on success or a negative error code on failure.
*/
2180int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
2181{
u8 buf;
int ret;

ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK0x270, &buf);
if (ret < 0)
return ret;

ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK0x270, buf | DP_TEST_SINK_START(1 << 0));
if (ret < 0)
return ret;

aux->crc_count = 0;
aux->crtc = crtc;
schedule_work(&aux->crc_work);

return 0;
2198}
2199EXPORT_SYMBOL(drm_dp_start_crc);

2201/**
* drm_dp_stop_crc() - stop capture of frame CRCs
* @aux: DisplayPort AUX channel
*
* Returns 0 on success or a negative error code on failure.
*/
2207int drm_dp_stop_crc(struct drm_dp_aux *aux)
2208{
u8 buf;
int ret;

ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK0x270, &buf);
if (ret < 0)
return ret;

ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK0x270, buf & ~DP_TEST_SINK_START(1 << 0));
if (ret < 0)
return ret;

flush_work(&aux->crc_work);
aux->crtc = NULL((void *)0);

return 0;
2224}
2225EXPORT_SYMBOL(drm_dp_stop_crc);

2227struct dpcd_quirk {
u8 oui[3];
u8 device_id[6];
bool_Bool is_branch;
u32 quirks;
2232};

2234#define OUI(first, second, third) { (first), (second), (third) }
2235#define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
{ (first), (second), (third), (fourth), (fifth), (sixth) }

2238#define DEVICE_ID_ANY	DEVICE_ID(0, 0, 0, 0, 0, 0)

2240static const struct dpcd_quirk dpcd_quirk_list[] = {
/* Analogix 7737 needs reduced M and N at HBR2 link rates */
{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true1, BIT(DP_DPCD_QUIRK_CONSTANT_N)(1UL << (DP_DPCD_QUIRK_CONSTANT_N)) },
/* LG LP140WF6-SPM1 eDP panel */
{ OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false0, BIT(DP_DPCD_QUIRK_CONSTANT_N)(1UL << (DP_DPCD_QUIRK_CONSTANT_N)) },
/* Apple panels need some additional handling to support PSR */
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false0, BIT(DP_DPCD_QUIRK_NO_PSR)(1UL << (DP_DPCD_QUIRK_NO_PSR)) },
/* CH7511 seems to leave SINK_COUNT zeroed */
{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false0, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT)(1UL << (DP_DPCD_QUIRK_NO_SINK_COUNT)) },
/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true1, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD)(1UL << (DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD)) },
/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false0, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)(1UL << (DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) },
2253};

2255#undef OUI

2257/*
* Get a bit mask of DPCD quirks for the sink/branch device identified by
* ident. The quirk data is shared but it's up to the drivers to act on the
* data.
*
* For now, only the OUI (first three bytes) is used, but this may be extended
* to device identification string and hardware/firmware revisions later.
*/
2265static u32
2266drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool_Bool is_branch)
2267{
const struct dpcd_quirk *quirk;
u32 quirks = 0;
int i;
u8 any_device[] = DEVICE_ID_ANY;

for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list)(sizeof((dpcd_quirk_list)) / sizeof((dpcd_quirk_list)[0])); i++) {
quirk = &dpcd_quirk_list[i];

if (quirk->is_branch != is_branch)
	continue;

if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui))__builtin_memcmp((quirk->oui), (ident->oui), (sizeof(ident
->oui))) != 0)
	continue;

if (memcmp(quirk->device_id, any_device, sizeof(any_device))__builtin_memcmp((quirk->device_id), (any_device), (sizeof
(any_device))) != 0 &&
    memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id))__builtin_memcmp((quirk->device_id), (ident->device_id)
, (sizeof(ident->device_id))) != 0)
	continue;

quirks |= quirk->quirks;
}

return quirks;
2290}

2292#undef DEVICE_ID_ANY
2293#undef DEVICE_ID

2295/**
* drm_dp_read_desc - read sink/branch descriptor from DPCD
* @aux: DisplayPort AUX channel
* @desc: Device descriptor to fill from DPCD
* @is_branch: true for branch devices, false for sink devices
*
* Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
* identification.
*
* Returns 0 on success or a negative error code on failure.
*/
2306int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
     bool_Bool is_branch)
2308{
struct drm_dp_dpcd_ident *ident = &desc->ident;
unsigned int offset = is_branch ? DP_BRANCH_OUI0x500 : DP_SINK_OUI0x400;
int ret, dev_id_len;

ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
if (ret < 0)
return ret;

desc->quirks = drm_dp_get_quirks(ident, is_branch);

dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));

drm_dbg_kms(aux->drm_dev,__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n"
, aux->name, is_branch ? "branch" : "sink", (int)sizeof(ident
->oui), ident->oui, dev_id_len, ident->device_id, ident
->hw_rev >> 4, ident->hw_rev & 0xf, ident->
sw_major_rev, ident->sw_minor_rev, desc->quirks)
    "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n"
, aux->name, is_branch ? "branch" : "sink", (int)sizeof(ident
->oui), ident->oui, dev_id_len, ident->device_id, ident
->hw_rev >> 4, ident->hw_rev & 0xf, ident->
sw_major_rev, ident->sw_minor_rev, desc->quirks)
    aux->name, is_branch ? "branch" : "sink",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n"
, aux->name, is_branch ? "branch" : "sink", (int)sizeof(ident
->oui), ident->oui, dev_id_len, ident->device_id, ident
->hw_rev >> 4, ident->hw_rev & 0xf, ident->
sw_major_rev, ident->sw_minor_rev, desc->quirks)
    (int)sizeof(ident->oui), ident->oui, dev_id_len,__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n"
, aux->name, is_branch ? "branch" : "sink", (int)sizeof(ident
->oui), ident->oui, dev_id_len, ident->device_id, ident
->hw_rev >> 4, ident->hw_rev & 0xf, ident->
sw_major_rev, ident->sw_minor_rev, desc->quirks)
    ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf,__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n"
, aux->name, is_branch ? "branch" : "sink", (int)sizeof(ident
->oui), ident->oui, dev_id_len, ident->device_id, ident
->hw_rev >> 4, ident->hw_rev & 0xf, ident->
sw_major_rev, ident->sw_minor_rev, desc->quirks)
    ident->sw_major_rev, ident->sw_minor_rev, desc->quirks)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n"
, aux->name, is_branch ? "branch" : "sink", (int)sizeof(ident
->oui), ident->oui, dev_id_len, ident->device_id, ident
->hw_rev >> 4, ident->hw_rev & 0xf, ident->
sw_major_rev, ident->sw_minor_rev, desc->quirks);

return 0;
2329}
2330EXPORT_SYMBOL(drm_dp_read_desc);

2332/**
* drm_dp_dsc_sink_max_slice_count() - Get the max slice count
* supported by the DSC sink.
* @dsc_dpcd: DSC capabilities from DPCD
* @is_edp: true if its eDP, false for DP
*
* Read the slice capabilities DPCD register from DSC sink to get
* the maximum slice count supported. This is used to populate
* the DSC parameters in the &struct drm_dsc_config by the driver.
* Driver creates an infoframe using these parameters to populate
* &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
* infoframe using the helper function drm_dsc_pps_infoframe_pack()
*
* Returns:
* Maximum slice count supported by DSC sink or 0 its invalid
*/
2348u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE0x10],
		   bool_Bool is_edp)
2350{
u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_10x064 - DP_DSC_SUPPORT0x060];

if (is_edp) {
/* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK(1 << 3))
	return 4;
if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK(1 << 1))
	return 2;
if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK(1 << 0))
	return 1;
} else {
/* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_20x06D - DP_DSC_SUPPORT0x060];

if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK(1 << 2))
	return 24;
if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK(1 << 1))
	return 20;
if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK(1 << 0))
	return 16;
if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK(1 << 7))
	return 12;
if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK(1 << 6))
	return 10;
if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK(1 << 5))
	return 8;
if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK(1 << 4))
	return 6;
if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK(1 << 3))
	return 4;
if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK(1 << 1))
	return 2;
if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK(1 << 0))
	return 1;
}

return 0;
2388}
2389EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);

2391/**
* drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
* @dsc_dpcd: DSC capabilities from DPCD
*
* Read the DSC DPCD register to parse the line buffer depth in bits which is
* number of bits of precision within the decoder line buffer supported by
* the DSC sink. This is used to populate the DSC parameters in the
* &struct drm_dsc_config by the driver.
* Driver creates an infoframe using these parameters to populate
* &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
* infoframe using the helper function drm_dsc_pps_infoframe_pack()
*
* Returns:
* Line buffer depth supported by DSC panel or 0 its invalid
*/
2406u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE0x10])
2407{
u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH0x065 - DP_DSC_SUPPORT0x060];

switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK(0xf << 0)) {
case DP_DSC_LINE_BUF_BIT_DEPTH_90x0:
return 9;
case DP_DSC_LINE_BUF_BIT_DEPTH_100x1:
return 10;
case DP_DSC_LINE_BUF_BIT_DEPTH_110x2:
return 11;
case DP_DSC_LINE_BUF_BIT_DEPTH_120x3:
return 12;
case DP_DSC_LINE_BUF_BIT_DEPTH_130x4:
return 13;
case DP_DSC_LINE_BUF_BIT_DEPTH_140x5:
return 14;
case DP_DSC_LINE_BUF_BIT_DEPTH_150x6:
return 15;
case DP_DSC_LINE_BUF_BIT_DEPTH_160x7:
return 16;
case DP_DSC_LINE_BUF_BIT_DEPTH_80x8:
return 8;
}

return 0;
2432}
2433EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);

2435/**
* drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
* values supported by the DSC sink.
* @dsc_dpcd: DSC capabilities from DPCD
* @dsc_bpc: An array to be filled by this helper with supported
*           input bpcs.
*
* Read the DSC DPCD from the sink device to parse the supported bits per
* component values. This is used to populate the DSC parameters
* in the &struct drm_dsc_config by the driver.
* Driver creates an infoframe using these parameters to populate
* &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
* infoframe using the helper function drm_dsc_pps_infoframe_pack()
*
* Returns:
* Number of input BPC values parsed from the DPCD
*/
2452int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE0x10],
			 u8 dsc_bpc[3])
2454{
int num_bpc = 0;
u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP0x06A - DP_DSC_SUPPORT0x060];

if (color_depth & DP_DSC_12_BPC(1 << 3))
dsc_bpc[num_bpc++] = 12;
if (color_depth & DP_DSC_10_BPC(1 << 2))
dsc_bpc[num_bpc++] = 10;
if (color_depth & DP_DSC_8_BPC(1 << 1))
dsc_bpc[num_bpc++] = 8;

return num_bpc;
2466}
2467EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);

2469static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
		  const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf], int address,
		  u8 *buf, int buf_size)
2472{
/*
* At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
* corrupted values when reading from the 0xF0000- range with a block
* size bigger than 1.
*/
int block_size = dpcd[DP_DPCD_REV0x000] < 0x14 ? 1 : buf_size;
int offset;
int ret;

for (offset = 0; offset < buf_size; offset += block_size) {
ret = drm_dp_dpcd_read(aux,
		       address + offset,
		       &buf[offset], block_size);
if (ret < 0)
	return ret;

WARN_ON(ret != block_size)({ int __ret = !!(ret != block_size); if (__ret) printf("WARNING %s failed at %s:%d\n"
, "ret != block_size", "/usr/src/sys/dev/pci/drm/display/drm_dp_helper.c"
, 2489); __builtin_expect(!!(__ret), 0); });
}

return 0;
2493}

2495/**
* drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
* @aux: DisplayPort AUX channel
* @dpcd: DisplayPort configuration data
* @caps: buffer to return the capability info in
*
* Read capabilities common to all LTTPRs.
*
* Returns 0 on success or a negative error code on failure.
*/
2505int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
		  const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
		  u8 caps[DP_LTTPR_COMMON_CAP_SIZE8])
2508{
return drm_dp_read_lttpr_regs(aux, dpcd,
		      DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV0xf0000,
		      caps, DP_LTTPR_COMMON_CAP_SIZE8);
2512}
2513EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);

2515/**
* drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
* @aux: DisplayPort AUX channel
* @dpcd: DisplayPort configuration data
* @dp_phy: LTTPR PHY to read the capabilities for
* @caps: buffer to return the capability info in
*
* Read the capabilities for the given LTTPR PHY.
*
* Returns 0 on success or a negative error code on failure.
*/
2526int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
	       const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
	       enum drm_dp_phy dp_phy,
	       u8 caps[DP_LTTPR_PHY_CAP_SIZE3])
2530{
return drm_dp_read_lttpr_regs(aux, dpcd,
		      DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy)((0xf0010 + (0xf0060 - 0xf0010) * ((dp_phy) - DP_PHY_LTTPR1))
 - (0xf0010 + (0xf0060 - 0xf0010) * ((DP_PHY_LTTPR1) - DP_PHY_LTTPR1
)) + (0xf0020)),
		      caps, DP_LTTPR_PHY_CAP_SIZE3);
2534}
2535EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);

2537static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE8], int r)
2538{
return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV0xf0000];
2540}

2542/**
* drm_dp_lttpr_count - get the number of detected LTTPRs
* @caps: LTTPR common capabilities
*
* Get the number of detected LTTPRs from the LTTPR common capabilities info.
*
* Returns:
*   -ERANGE if more than supported number (8) of LTTPRs are detected
*   -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
*   otherwise the number of detected LTTPRs
*/
2553int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE8])
2554{
u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT0xf0002);

switch (hweight8(count)) {
case 0:
return 0;
case 1:
return 8 - ilog2(count)((sizeof(count) <= 4) ? (fls(count) - 1) : (flsl(count) - 1
));
case 8:
return -ERANGE34;
default:
return -EINVAL22;
}
2567}
2568EXPORT_SYMBOL(drm_dp_lttpr_count);

2570/**
* drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
* @caps: LTTPR common capabilities
*
* Returns the maximum link rate supported by all detected LTTPRs.
*/
2576int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE8])
2577{
u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER0xf0001);

return drm_dp_bw_code_to_link_rate(rate);
2581}
2582EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);

2584/**
* drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
* @caps: LTTPR common capabilities
*
* Returns the maximum lane count supported by all detected LTTPRs.
*/
2590int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE8])
2591{
u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER0xf0004);

return max_lanes & DP_MAX_LANE_COUNT_MASK0x1f;
2595}
2596EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);

2598/**
* drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
* @caps: LTTPR PHY capabilities
*
* Returns true if the @caps for an LTTPR TX PHY indicate support for
* voltage swing level 3.
*/
2605bool_Bool
2606drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE3])
2607{
u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER10xf0021);

return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED(1UL << (0));
2611}
2612EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);

2614/**
* drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
* @caps: LTTPR PHY capabilities
*
* Returns true if the @caps for an LTTPR TX PHY indicate support for
* pre-emphasis level 3.
*/
2621bool_Bool
2622drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE3])
2623{
u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER10xf0021);

return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED(1UL << (1));
2627}
2628EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);

2630/**
* drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
* @aux: DisplayPort AUX channel
* @data: DP phy compliance test parameters.
*
* Returns 0 on success or a negative error code on failure.
*/
2637int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
		struct drm_dp_phy_test_params *data)
2639{
int err;
u8 rate, lanes;

err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE0x219, &rate);
if (err < 0)
return err;
data->link_rate = drm_dp_bw_code_to_link_rate(rate);

err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT0x220, &lanes);
if (err < 0)
return err;
data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK0x1f;

if (lanes & DP_ENHANCED_FRAME_CAP(1 << 7))
data->enhanced_frame_cap = true1;

err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN0x248, &data->phy_pattern);
if (err < 0)
return err;

switch (data->phy_pattern) {
case DP_PHY_TEST_PATTERN_80BIT_CUSTOM0x4:
err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_00x250,
		       &data->custom80, sizeof(data->custom80));
if (err < 0)
	return err;

break;
case DP_PHY_TEST_PATTERN_CP25200x5:
err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET0x24A,
		       &data->hbr2_reset,
		       sizeof(data->hbr2_reset));
if (err < 0)
	return err;
}

return 0;
2677}
2678EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);

2680/**
* drm_dp_set_phy_test_pattern() - set the pattern to the sink.
* @aux: DisplayPort AUX channel
* @data: DP phy compliance test parameters.
* @dp_rev: DP revision to use for compliance testing
*
* Returns 0 on success or a negative error code on failure.
*/
2688int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
		struct drm_dp_phy_test_params *data, u8 dp_rev)
2690{
int err, i;
u8 test_pattern;

test_pattern = data->phy_pattern;
if (dp_rev < 0x12) {
test_pattern = (test_pattern << 2) &
	       DP_LINK_QUAL_PATTERN_11_MASK(3 << 2);
err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET0x102,
			 test_pattern);
if (err < 0)
	return err;
} else {
for (i = 0; i < data->num_lanes; i++) {
	err = drm_dp_dpcd_writeb(aux,
				 DP_LINK_QUAL_LANE0_SET0x10b + i,
				 test_pattern);
	if (err < 0)
		return err;
}
}

return 0;
2713}
2714EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);

2716static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
2717{
if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
return "Invalid";

switch (pixelformat) {
case DP_PIXELFORMAT_RGB:
return "RGB";
case DP_PIXELFORMAT_YUV444:
return "YUV444";
case DP_PIXELFORMAT_YUV422:
return "YUV422";
case DP_PIXELFORMAT_YUV420:
return "YUV420";
case DP_PIXELFORMAT_Y_ONLY:
return "Y_ONLY";
case DP_PIXELFORMAT_RAW:
return "RAW";
default:
return "Reserved";
}
2737}

2739static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
			   enum dp_colorimetry colorimetry)
2741{
if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
return "Invalid";

switch (colorimetry) {
case DP_COLORIMETRY_DEFAULT:
switch (pixelformat) {
case DP_PIXELFORMAT_RGB:
	return "sRGB";
case DP_PIXELFORMAT_YUV444:
case DP_PIXELFORMAT_YUV422:
case DP_PIXELFORMAT_YUV420:
	return "BT.601";
case DP_PIXELFORMAT_Y_ONLY:
	return "DICOM PS3.14";
case DP_PIXELFORMAT_RAW:
	return "Custom Color Profile";
default:
	return "Reserved";
}
case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
switch (pixelformat) {
case DP_PIXELFORMAT_RGB:
	return "Wide Fixed";
case DP_PIXELFORMAT_YUV444:
case DP_PIXELFORMAT_YUV422:
case DP_PIXELFORMAT_YUV420:
	return "BT.709";
default:
	return "Reserved";
}
case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
switch (pixelformat) {
case DP_PIXELFORMAT_RGB:
	return "Wide Float";
case DP_PIXELFORMAT_YUV444:
case DP_PIXELFORMAT_YUV422:
case DP_PIXELFORMAT_YUV420:
	return "xvYCC 601";
default:
	return "Reserved";
}
case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
switch (pixelformat) {
case DP_PIXELFORMAT_RGB:
	return "OpRGB";
case DP_PIXELFORMAT_YUV444:
case DP_PIXELFORMAT_YUV422:
case DP_PIXELFORMAT_YUV420:
	return "xvYCC 709";
default:
	return "Reserved";
}
case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
switch (pixelformat) {
case DP_PIXELFORMAT_RGB:
	return "DCI-P3";
case DP_PIXELFORMAT_YUV444:
case DP_PIXELFORMAT_YUV422:
case DP_PIXELFORMAT_YUV420:
	return "sYCC 601";
default:
	return "Reserved";
}
case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
switch (pixelformat) {
case DP_PIXELFORMAT_RGB:
	return "Custom Profile";
case DP_PIXELFORMAT_YUV444:
case DP_PIXELFORMAT_YUV422:
case DP_PIXELFORMAT_YUV420:
	return "OpYCC 601";
default:
	return "Reserved";
}
case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
switch (pixelformat) {
case DP_PIXELFORMAT_RGB:
	return "BT.2020 RGB";
case DP_PIXELFORMAT_YUV444:
case DP_PIXELFORMAT_YUV422:
case DP_PIXELFORMAT_YUV420:
	return "BT.2020 CYCC";
default:
	return "Reserved";
}
case DP_COLORIMETRY_BT2020_YCC:
switch (pixelformat) {
case DP_PIXELFORMAT_YUV444:
case DP_PIXELFORMAT_YUV422:
case DP_PIXELFORMAT_YUV420:
	return "BT.2020 YCC";
default:
	return "Reserved";
}
default:
return "Invalid";
}
2839}

2841static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
2842{
switch (dynamic_range) {
case DP_DYNAMIC_RANGE_VESA:
return "VESA range";
case DP_DYNAMIC_RANGE_CTA:
return "CTA range";
default:
return "Invalid";
}
2851}

2853static const char *dp_content_type_get_name(enum dp_content_type content_type)
2854{
switch (content_type) {
case DP_CONTENT_TYPE_NOT_DEFINED:
return "Not defined";
case DP_CONTENT_TYPE_GRAPHICS:
return "Graphics";
case DP_CONTENT_TYPE_PHOTO:
return "Photo";
case DP_CONTENT_TYPE_VIDEO:
return "Video";
case DP_CONTENT_TYPE_GAME:
return "Game";
default:
return "Reserved";
}
2869}

2871void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
	const struct drm_dp_vsc_sdp *vsc)
2873{
2874#define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)printf("drm:pid%d:%s *PRINTK* " fmt, ({struct cpu_info *__ci;
 asm volatile("movq %%gs:%P1,%0" : "=r" (__ci) :"n" (__builtin_offsetof
(struct cpu_info, ci_self))); __ci;})->ci_curproc->p_p->
ps_pid, __func__ , ##__VA_ARGS__)
DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
   vsc->revision, vsc->length);
DP_SDP_LOG("    pixelformat: %s\n",
   dp_pixelformat_get_name(vsc->pixelformat));
DP_SDP_LOG("    colorimetry: %s\n",
   dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
DP_SDP_LOG("    bpc: %u\n", vsc->bpc);
DP_SDP_LOG("    dynamic range: %s\n",
   dp_dynamic_range_get_name(vsc->dynamic_range));
DP_SDP_LOG("    content type: %s\n",
   dp_content_type_get_name(vsc->content_type));
2886#undef DP_SDP_LOG
2887}
2888EXPORT_SYMBOL(drm_dp_vsc_sdp_log);

2890/**
* drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
* @dpcd: DisplayPort configuration data
* @port_cap: port capabilities
*
* Returns maximum frl bandwidth supported by PCON in GBPS,
* returns 0 if not supported.
*/
2898int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE0xf],
	       const u8 port_cap[4])
2900{
int bw;
u8 buf;

buf = port_cap[2];
bw = buf & DP_PCON_MAX_FRL_BW(7 << 2);

switch (bw) {
case DP_PCON_MAX_9GBPS(1 << 2):
return 9;
case DP_PCON_MAX_18GBPS(2 << 2):
return 18;
case DP_PCON_MAX_24GBPS(3 << 2):
return 24;
case DP_PCON_MAX_32GBPS(4 << 2):
return 32;
case DP_PCON_MAX_40GBPS(5 << 2):
return 40;
case DP_PCON_MAX_48GBPS(6 << 2):
return 48;
case DP_PCON_MAX_0GBPS(0 << 2):
default:
return 0;
}

return 0;
2926}
2927EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);

2929/**
* drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
* @aux: DisplayPort AUX channel
* @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY.
*
* Returns 0 if success, else returns negative error code.
*/
2936int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool_Bool enable_frl_ready_hpd)
2937{
int ret;
u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE(1 << 3) |
 DP_PCON_ENABLE_LINK_FRL_MODE(1 << 5);

if (enable_frl_ready_hpd)
buf |= DP_PCON_ENABLE_HPD_READY(1 << 6);

ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_10x305A, buf);

return ret;
2948}
2949EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);

2951/**
* drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
* @aux: DisplayPort AUX channel
*
* Returns true if success, else returns false.
*/
2957bool_Bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
2958{
int ret;
u8 buf;

ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS0x303B, &buf);
if (ret < 0)
return false0;

if (buf & DP_PCON_FRL_READY(1 << 1))
return true1;

return false0;
2970}
2971EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);

2973/**
* drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
* @aux: DisplayPort AUX channel
* @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
* @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
* In Concurrent Mode, the FRL link bring up can be done along with
* DP Link training. In Sequential mode, the FRL link bring up is done prior to
* the DP Link training.
*
* Returns 0 if success, else returns negative error code.
*/

2985int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
		u8 frl_mode)
2987{
int ret;
u8 buf;

ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_10x305A, &buf);
if (ret < 0)
return ret;

if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK(1 << 4))
buf |= DP_PCON_ENABLE_CONCURRENT_LINK(1 << 4);
else
buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK(1 << 4);

switch (max_frl_gbps) {
case 9:
buf |=  DP_PCON_ENABLE_MAX_BW_9GBPS1;
break;
case 18:
buf |=  DP_PCON_ENABLE_MAX_BW_18GBPS2;
break;
case 24:
buf |=  DP_PCON_ENABLE_MAX_BW_24GBPS3;
break;
case 32:
buf |=  DP_PCON_ENABLE_MAX_BW_32GBPS4;
break;
case 40:
buf |=  DP_PCON_ENABLE_MAX_BW_40GBPS5;
break;
case 48:
buf |=  DP_PCON_ENABLE_MAX_BW_48GBPS6;
break;
case 0:
buf |=  DP_PCON_ENABLE_MAX_BW_0GBPS0;
break;
default:
return -EINVAL22;
}

ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_10x305A, buf);
if (ret < 0)
return ret;

return 0;
3031}
3032EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);

3034/**
* drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
* @aux: DisplayPort AUX channel
* @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
* @frl_type : FRL training type, can be Extended, or Normal.
* In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
* starting from min, and stops when link training is successful. In Extended
* FRL training, all frl bw selected in the mask are trained by the PCON.
*
* Returns 0 if success, else returns negative error code.
*/
3045int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
		u8 frl_type)
3047{
int ret;
u8 buf = max_frl_mask;

if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED(1 << 6))
buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED(1 << 6);
else
buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED(1 << 6);

ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_20x305B, buf);
if (ret < 0)
return ret;

return 0;
3061}
3062EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);

3064/**
* drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
* @aux: DisplayPort AUX channel
*
* Returns 0 if success, else returns negative error code.
*/
3070int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux)
3071{
int ret;

ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_10x305A, 0x0);
if (ret < 0)
return ret;

return 0;
3079}
3080EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);

3082/**
* drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
* @aux: DisplayPort AUX channel
*
* Returns 0 if success, else returns negative error code.
*/
3088int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
3089{
int ret;
u8 buf = 0;

ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_10x305A, &buf);
if (ret < 0)
return ret;
if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE(1 << 3))) {
drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: PCON in Autonomous mode, can't enable FRL\n"
, aux->name)
	    aux->name)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: PCON in Autonomous mode, can't enable FRL\n"
, aux->name);
return -EINVAL22;
}
buf |= DP_PCON_ENABLE_HDMI_LINK(1 << 7);
ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_10x305A, buf);
if (ret < 0)
return ret;

return 0;
3107}
3108EXPORT_SYMBOL(drm_dp_pcon_frl_enable);

3110/**
* drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
* @aux: DisplayPort AUX channel
*
* Returns true if link is active else returns false.
*/
3116bool_Bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
3117{
u8 buf;
int ret;

ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS0x303B, &buf);
if (ret < 0)
return false0;

return buf & DP_PCON_HDMI_TX_LINK_ACTIVE(1 << 0);
3126}
3127EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);

3129/**
* drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
* @aux: DisplayPort AUX channel
* @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
* Valid only if the MODE returned is FRL. For Normal Link training mode
* only 1 of the bits will be set, but in case of Extended mode, more than
* one bits can be set.
*
* Returns the link mode : TMDS or FRL on success, else returns negative error
* code.
*/
3140int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
3141{
u8 buf;
int mode;
int ret;

ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS0x3036, &buf);
if (ret < 0)
return ret;

mode = buf & DP_PCON_HDMI_LINK_MODE(1 << 0);

if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL1 == mode)
*frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW(0x3F << 1)) >> 1;

return mode;
3156}
3157EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);

3159/**
* drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
* during link failure between PCON and HDMI sink
* @aux: DisplayPort AUX channel
* @connector: DRM connector
* code.
**/

3167void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
			   struct drm_connector *connector)
3169{
u8 buf, error_count;
int i, num_error;
struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;

for (i = 0; i < hdmi->max_lanes; i++) {
if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN00x3037 + i, &buf) < 0)
	return;

error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK(0x7 << 0);
switch (error_count) {
case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS(1 << 2):
	num_error = 100;
	break;
case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS(1 << 1):
	num_error = 10;
	break;
case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS(1 << 0):
	num_error = 3;
	break;
default:
	num_error = 0;
}

drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: More than %d errors since the last read for lane %d"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, num_error, i)
	aux->name, num_error, i)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: More than %d errors since the last read for lane %d"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, num_error, i);
}
3196}
3197EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);

3199/*
* drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
* @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
*
* Returns true is PCON encoder is DSC 1.2 else returns false.
*/
3205bool_Bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE0xD])
3206{
u8 buf;
u8 major_v, minor_v;

buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION0x093 - DP_PCON_DSC_ENCODER0x092];
major_v = (buf & DP_PCON_DSC_MAJOR_MASK(0xF << 0)) >> DP_PCON_DSC_MAJOR_SHIFT0;
minor_v = (buf & DP_PCON_DSC_MINOR_MASK(0xF << 4)) >> DP_PCON_DSC_MINOR_SHIFT4;

if (major_v == 1 && minor_v == 2)
return true1;

return false0;
3218}
3219EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);

3221/*
* drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
* @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
*
* Returns maximum no. of slices supported by the PCON DSC Encoder.
*/
3227int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE0xD])
3228{
u8 slice_cap1, slice_cap2;

slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_10x096 - DP_PCON_DSC_ENCODER0x092];
slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_20x09C - DP_PCON_DSC_ENCODER0x092];

if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC(0x1 << 2))
return 24;
if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC(0x1 << 1))
return 20;
if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC(0x1 << 0))
return 16;
if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC(0x1 << 7))
return 12;
if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC(0x1 << 6))
return 10;
if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC(0x1 << 5))
return 8;
if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC(0x1 << 4))
return 6;
if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC(0x1 << 3))
return 4;
if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC(0x1 << 1))
return 2;
if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC(0x1 << 0))
return 1;

return 0;
3256}
3257EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);

3259/*
* drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
* @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
*
* Returns maximum width of the slices in pixel width i.e. no. of pixels x 320.
*/
3265int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE0xD])
3266{
u8 buf;

buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH0x09B - DP_PCON_DSC_ENCODER0x092];

return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER320;
3272}
3273EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);

3275/*
* drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
* @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
*
* Returns the bpp precision supported by the PCON encoder.
*/
3281int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE0xD])
3282{
u8 buf;

buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR0x09E - DP_PCON_DSC_ENCODER0x092];

switch (buf & DP_PCON_DSC_BPP_INCR_MASK(0x7 << 0)) {
case DP_PCON_DSC_ONE_16TH_BPP0:
return 16;
case DP_PCON_DSC_ONE_8TH_BPP1:
return 8;
case DP_PCON_DSC_ONE_4TH_BPP2:
return 4;
case DP_PCON_DSC_ONE_HALF_BPP3:
return 2;
case DP_PCON_DSC_ONE_BPP4:
return 1;
}

return 0;
3301}
3302EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr);

3304static
3305int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
3306{
u8 buf;
int ret;

ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_20x3052, &buf);
if (ret < 0)
return ret;

buf |= DP_PCON_ENABLE_DSC_ENCODER(1 << 1);

if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER2) {
buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK(0x3 << 2);
buf |= pps_buf_config << 2;
}

ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_20x3052, buf);
if (ret < 0)
return ret;

return 0;
3326}

3328/**
* drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
* for DSC1.2 between PCON & HDMI2.1 sink
* @aux: DisplayPort AUX channel
*
* Returns 0 on success, else returns negative error code.
*/
3335int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
3336{
int ret;

ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED0);
if (ret < 0)
return ret;

return 0;
3344}
3345EXPORT_SYMBOL(drm_dp_pcon_pps_default);

3347/**
* drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
* HDMI sink
* @aux: DisplayPort AUX channel
* @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
*
* Returns 0 on success, else returns negative error code.
*/
3355int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
3356{
int ret;

ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE0x3100, &pps_buf, 128);
if (ret < 0)
return ret;

ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER2);
if (ret < 0)
return ret;

return 0;
3368}
3369EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);

3371/*
* drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
* override registers
* @aux: DisplayPort AUX channel
* @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
* bits_per_pixel.
*
* Returns 0 on success, else returns negative error code.
*/
3380int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
3381{
int ret;

ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT0x3180, &pps_param[0], 2);
if (ret < 0)
return ret;
ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH0x3182, &pps_param[2], 2);
if (ret < 0)
return ret;
ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP0x3184, &pps_param[4], 2);
if (ret < 0)
return ret;

ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER2);
if (ret < 0)
return ret;

return 0;
3399}
3400EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);

3402/*
* drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
* @aux: displayPort AUX channel
* @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
*
* Returns 0 on success, else returns negative error code.
*/
3409int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
3410{
int ret;
u8 buf;

ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_20x3052, &buf);
if (ret < 0)
return ret;

if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK(7 << 4))
buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK(7 << 4));
else
buf &= ~DP_CONVERSION_RGB_YCBCR_MASK(7 << 4);

ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_20x3052, buf);
if (ret < 0)
return ret;

return 0;
3428}
3429EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);

3431/**
* drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
* @aux: The DP AUX channel to use
* @bl: Backlight capability info from drm_edp_backlight_init()
* @level: The brightness level to set
*
* Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
* already have been enabled by the driver by calling drm_edp_backlight_enable().
*
* Returns: %0 on success, negative error code on failure
*/
3442int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
		u16 level)
3444{
int ret;
u8 buf[2] = { 0 };

/* The panel uses the PWM for controlling brightness levels */
if (!bl->aux_set)
return 0;

if (bl->lsb_reg_used) {
buf[0] = (level & 0xff00) >> 8;
buf[1] = (level & 0x00ff);
} else {
buf[0] = level;
}

ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB0x722, buf, sizeof(buf));
if (ret != sizeof(buf)) {
drm_err(aux->drm_dev,printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: Failed to write aux backlight level: %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, ret)
	"%s: Failed to write aux backlight level: %d\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: Failed to write aux backlight level: %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, ret)
	aux->name, ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: Failed to write aux backlight level: %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, ret);
return ret < 0 ? ret : -EIO5;
}

return 0;
3468}
3469EXPORT_SYMBOL(drm_edp_backlight_set_level);

3471static int
3472drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
	     bool_Bool enable)
3474{
int ret;
u8 buf;

/* This panel uses the EDP_BL_PWR GPIO for enablement */
if (!bl->aux_enable)
return 0;

ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER0x720, &buf);
if (ret != 1) {
drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: Failed to read eDP display control register: %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, ret)
	aux->name, ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: Failed to read eDP display control register: %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, ret);
return ret < 0 ? ret : -EIO5;
}
if (enable)
buf |= DP_EDP_BACKLIGHT_ENABLE(1 << 0);
else
buf &= ~DP_EDP_BACKLIGHT_ENABLE(1 << 0);

ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER0x720, buf);
if (ret != 1) {
drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: Failed to write eDP display control register: %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, ret)
	aux->name, ret)printf("drm:pid%d:%s *ERROR* " "[drm] " "*ERROR* " "%s: Failed to write eDP display control register: %d\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
 (__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
 __ci;})->ci_curproc->p_p->ps_pid, __func__ , aux->
name, ret);
return ret < 0 ? ret : -EIO5;
}

return 0;
3501}

3503/**
* drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
* @aux: The DP AUX channel to use
* @bl: Backlight capability info from drm_edp_backlight_init()
* @level: The initial backlight level to set via AUX, if there is one
*
* This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
* restoring any important backlight state such as the given backlight level, the brightness byte
* count, backlight frequency, etc.
*
* Note that certain panels do not support being enabled or disabled via DPCD, but instead require
* that the driver handle enabling/disabling the panel through implementation-specific means using
* the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
* this function becomes a no-op, and the driver is expected to handle powering the panel on using
* the EDP_BL_PWR GPIO.
*
* Returns: %0 on success, negative error code on failure.
*/
3521int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
	     const u16 level)
3523{
int ret;
u8 dpcd_buf;

if (bl->aux_set)
dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD(2 << 0);
else
dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM(0 << 0);

if (bl->pwmgen_bit_count) {
ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT0x724, bl->pwmgen_bit_count);
if (ret != 1)
	drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to write aux pwmgen bit count: %d\n"
, aux->name, ret)
		    aux->name, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to write aux pwmgen bit count: %d\n"
, aux->name, ret);
}

if (bl->pwm_freq_pre_divider) {
ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET0x728, bl->pwm_freq_pre_divider);
if (ret != 1)
	drm_dbg_kms(aux->drm_dev,__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to write aux backlight frequency: %d\n"
, aux->name, ret)
		    "%s: Failed to write aux backlight frequency: %d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to write aux backlight frequency: %d\n"
, aux->name, ret)
		    aux->name, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to write aux backlight frequency: %d\n"
, aux->name, ret);
else
	dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE(1 << 3);
}

ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER0x721, dpcd_buf);
if (ret != 1) {
drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to write aux backlight mode: %d\n"
, aux->name, ret)
	    aux->name, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to write aux backlight mode: %d\n"
, aux->name, ret);
return ret < 0 ? ret : -EIO5;
}

ret = drm_edp_backlight_set_level(aux, bl, level);
if (ret < 0)
return ret;
ret = drm_edp_backlight_set_enable(aux, bl, true1);
if (ret < 0)
return ret;

return 0;
3564}
3565EXPORT_SYMBOL(drm_edp_backlight_enable);

3567/**
* drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
* @aux: The DP AUX channel to use
* @bl: Backlight capability info from drm_edp_backlight_init()
*
* This function handles disabling DPCD backlight controls on a panel over AUX.
*
* Note that certain panels do not support being enabled or disabled via DPCD, but instead require
* that the driver handle enabling/disabling the panel through implementation-specific means using
* the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
* this function becomes a no-op, and the driver is expected to handle powering the panel off using
* the EDP_BL_PWR GPIO.
*
* Returns: %0 on success or no-op, negative error code on failure.
*/
3582int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
3583{
int ret;

ret = drm_edp_backlight_set_enable(aux, bl, false0);
if (ret < 0)
return ret;

return 0;
3591}
3592EXPORT_SYMBOL(drm_edp_backlight_disable);

3594static inline int
3595drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
	    u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE3])
3597{
int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
int ret;
u8 pn, pn_min, pn_max;

if (!bl->aux_set)
return 0;

ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT0x724, &pn);
if (ret != 1) {
drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to read pwmgen bit count cap: %d\n"
, aux->name, ret)
	    aux->name, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to read pwmgen bit count cap: %d\n"
, aux->name, ret);
return -ENODEV19;
}

pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK(0x1f << 0);
bl->max = (1 << pn) - 1;
if (!driver_pwm_freq_hz)
return 0;

/*
* Set PWM Frequency divider to match desired frequency provided by the driver.
* The PWM Frequency is calculated as 27Mhz / (F x P).
* - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
*             EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
* - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
*             EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
*/

/* Find desired value of (F x P)
* Note that, if F x P is out of supported range, the maximum value or minimum value will
* applied automatically. So no need to check that.
*/
fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz)(((1000 * 27000) + ((driver_pwm_freq_hz) / 2)) / (driver_pwm_freq_hz
));

/* Use highest possible value of Pn for more granularity of brightness adjustment while
* satisfying the conditions below.
* - Pn is in the range of Pn_min and Pn_max
* - F is in the range of 1 and 255
* - FxP is within 25% of desired value.
*   Note: 25% is arbitrary value and may need some tweak.
*/
ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN0x725, &pn_min);
if (ret != 1) {
drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to read pwmgen bit count cap min: %d\n"
, aux->name, ret)
	    aux->name, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to read pwmgen bit count cap min: %d\n"
, aux->name, ret);
return 0;
}
ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX0x726, &pn_max);
if (ret != 1) {
drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to read pwmgen bit count cap max: %d\n"
, aux->name, ret)
	    aux->name, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to read pwmgen bit count cap max: %d\n"
, aux->name, ret);
return 0;
}
pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK(0x1f << 0);
pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK(0x1f << 0);

/* Ensure frequency is within 25% of desired value */
fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4)(((fxp * 3) + ((4) / 2)) / (4));
fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4)(((fxp * 5) + ((4) / 2)) / (4));
if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
drm_dbg_kms(aux->drm_dev,__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Driver defined backlight frequency (%d) out of range\n"
, aux->name, driver_pwm_freq_hz)
	    "%s: Driver defined backlight frequency (%d) out of range\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Driver defined backlight frequency (%d) out of range\n"
, aux->name, driver_pwm_freq_hz)
	    aux->name, driver_pwm_freq_hz)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Driver defined backlight frequency (%d) out of range\n"
, aux->name, driver_pwm_freq_hz);
return 0;
}

for (pn = pn_max; pn >= pn_min; pn--) {
f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255)({ __typeof((((fxp) + ((1 << pn) / 2)) / (1 << pn
))) __min_a = (({ __typeof((((fxp) + ((1 << pn) / 2)) /
 (1 << pn))) __max_a = ((((fxp) + ((1 << pn) / 2)
) / (1 << pn))); __typeof((((fxp) + ((1 << pn) / 2
)) / (1 << pn))) __max_b = (1); __max_a > __max_b ? __max_a
 : __max_b; })); __typeof((((fxp) + ((1 << pn) / 2)) / (
<< pn))) __min_b = (255); __min_a < __min_b ? __min_a
 : __min_b; });
fxp_actual = f << pn;
if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
	break;
}

ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT0x724, pn);
if (ret != 1) {
drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to write aux pwmgen bit count: %d\n"
, aux->name, ret)
	    aux->name, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to write aux pwmgen bit count: %d\n"
, aux->name, ret);
return 0;
}
bl->pwmgen_bit_count = pn;
bl->max = (1 << pn) - 1;

if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP(1 << 5)) {
bl->pwm_freq_pre_divider = f;
drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Using backlight frequency from driver (%dHz)\n"
, aux->name, driver_pwm_freq_hz)
	    aux->name, driver_pwm_freq_hz)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Using backlight frequency from driver (%dHz)\n"
, aux->name, driver_pwm_freq_hz);
}

return 0;
3687}

3689static inline int
3690drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
	      u8 *current_mode)
3692{
int ret;
u8 buf[2];
u8 mode_reg;

ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER0x721, &mode_reg);
if (ret != 1) {
drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to read backlight mode: %d\n"
, aux->name, ret)
	    aux->name, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to read backlight mode: %d\n"
, aux->name, ret);
return ret < 0 ? ret : -EIO5;
}

*current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK(3 << 0));
if (!bl->aux_set)
return 0;

if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD(2 << 0)) {
int size = 1 + bl->lsb_reg_used;

ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB0x722, buf, size);
if (ret != size) {
	drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to read backlight level: %d\n"
, aux->name, ret)
		    aux->name, ret)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Failed to read backlight level: %d\n"
, aux->name, ret);
	return ret < 0 ? ret : -EIO5;
}

if (bl->lsb_reg_used)
	return (buf[0] << 8) | buf[1];
else
	return buf[0];
}

/*
* If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
* the driver should assume max brightness
*/
return bl->max;
3729}

3731/**
* drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
* interface.
* @aux: The DP aux device to use for probing
* @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
* @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
* @edp_dpcd: A cached copy of the eDP DPCD
* @current_level: Where to store the probed brightness level, if any
* @current_mode: Where to store the currently set backlight control mode
*
* Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
* along with also probing the current and maximum supported brightness levels.
*
* If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
* default frequency from the panel is used.
*
* Returns: %0 on success, negative error code on failure.
*/
3749int
3750drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
       u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE3],
       u16 *current_level, u8 *current_mode)
3753{
int ret;

if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP(1 << 2))
bl->aux_enable = true1;
if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP(1 << 1))
bl->aux_set = true1;
if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT(1 << 2))
bl->lsb_reg_used = true1;

/* Sanity check caps */
if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP(1 << 0))) {
drm_dbg_kms(aux->drm_dev,__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Panel supports neither AUX or PWM brightness control? Aborting\n"
, aux->name)
	    "%s: Panel supports neither AUX or PWM brightness control? Aborting\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Panel supports neither AUX or PWM brightness control? Aborting\n"
, aux->name)
	    aux->name)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Panel supports neither AUX or PWM brightness control? Aborting\n"
, aux->name);
return -EINVAL22;
}

ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
if (ret < 0)
return ret;

ret = drm_edp_backlight_probe_state(aux, bl, current_mode);
if (ret < 0)
return ret;
*current_level = ret;

drm_dbg_kms(aux->drm_dev,__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n"
, aux->name, bl->aux_set, bl->aux_enable, *current_mode
)
    "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n"
, aux->name, bl->aux_set, bl->aux_enable, *current_mode
)
    aux->name, bl->aux_set, bl->aux_enable, *current_mode)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n"
, aux->name, bl->aux_set, bl->aux_enable, *current_mode
);
if (bl->aux_set) {
drm_dbg_kms(aux->drm_dev,__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n"
, aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider
, bl->lsb_reg_used)
	    "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n",__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n"
, aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider
, bl->lsb_reg_used)
	    aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider,__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n"
, aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider
, bl->lsb_reg_used)
	    bl->lsb_reg_used)__drm_dev_dbg(((void *)0), (aux->drm_dev) ? (aux->drm_dev
)->dev : ((void *)0), DRM_UT_KMS, "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n"
, aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider
, bl->lsb_reg_used);
}

return 0;
3791}
3792EXPORT_SYMBOL(drm_edp_backlight_init);

3794#if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE)1 || \
(IS_MODULE(CONFIG_DRM_KMS_HELPER)0 && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)0)

3797static int dp_aux_backlight_update_status(struct backlight_device *bd)
3798{
STUB()do { printf("%s: stub\n", __func__); } while(0);
return -ENOSYS78;
3801#ifdef notyet
struct dp_aux_backlight *bl = bl_get_data(bd);
u16 brightness = backlight_get_brightness(bd);
int ret = 0;

if (!backlight_is_blank(bd)) {
if (!bl->enabled) {
	drm_edp_backlight_enable(bl->aux, &bl->info, brightness);
	bl->enabled = true1;
	return 0;
}
ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness);
} else {
if (bl->enabled) {
	drm_edp_backlight_disable(bl->aux, &bl->info);
	bl->enabled = false0;
}
}

return ret;
3821#endif
3822}

3824static const struct backlight_ops dp_aux_bl_ops = {
.update_status = dp_aux_backlight_update_status,
3826};

3828/**
* drm_panel_dp_aux_backlight - create and use DP AUX backlight
* @panel: DRM panel
* @aux: The DP AUX channel to use
*
* Use this function to create and handle backlight if your panel
* supports backlight control over DP AUX channel using DPCD
* registers as per VESA's standard backlight control interface.
*
* When the panel is enabled backlight will be enabled after a
* successful call to &drm_panel_funcs.enable()
*
* When the panel is disabled backlight will be disabled before the
* call to &drm_panel_funcs.disable().
*
* A typical implementation for a panel driver supporting backlight
* control over DP AUX will call this function at probe time.
* Backlight will then be handled transparently without requiring
* any intervention from the driver.
*
* drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init().
*
* Return: 0 on success or a negative error code on failure.
*/
3852int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
3853{
struct dp_aux_backlight *bl;
struct backlight_properties props = { 0 };
u16 current_level;
u8 current_mode;
u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE3];
int ret;

if (!panel || !panel->dev || !aux)
1
Assuming 'panel' is non-null→
2
←
Assuming field 'dev' is non-null→
3
←
Assuming 'aux' is non-null→
4
←
Taking false branch→
return -EINVAL22;

ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV0x700, edp_dpcd,
	       EDP_DISPLAY_CTL_CAP_SIZE3);
if (ret < 0)
5
←
Assuming 'ret' is >= 0→
6
←
Taking false branch→
return ret;

if (!drm_edp_backlight_supported(edp_dpcd)) {
7
←
Taking false branch→
DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n")drm_dev_printk(panel->dev, "\0016", "DP AUX backlight is not supported\n"
);
return 0;
}

bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL)kzalloc(sizeof(*bl), (0x0001 | 0x0004));
8
←
Calling 'kzalloc'→
10
←
Returned allocated memory→
if (!bl)
11
←
Assuming 'bl' is non-null→
12
←
Taking false branch→
return -ENOMEM12;

bl->aux = aux;

ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd,
		     &current_level, &current_mode);
if (ret12.1
'ret' is < 0
1
'ret' is < 0
 < 0)
13
←
Taking true branch→
return ret;
14
←
Potential leak of memory pointed to by 'bl'

props.type = BACKLIGHT_RAW0;
props.brightness = current_level;
props.max_brightness = bl->info.max;

bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight",
				  panel->dev, bl,
				  &dp_aux_bl_ops, &props);
if (IS_ERR(bl->base))
return PTR_ERR(bl->base);

backlight_disable(bl->base);

panel->backlight = bl->base;

return 0;
3900}
3901EXPORT_SYMBOL(drm_panel_dp_aux_backlight);

3903#endif

←

/usr/src/sys/dev/pci/drm/include/linux/slab.h

1/* Public domain. */
2 
3#ifndef _LINUX_SLAB_H
4#define _LINUX_SLAB_H
5 
6#include <sys/types.h>
7#include <sys/malloc.h>
8 
9#include <linux/types.h>
10#include <linux/workqueue.h>
11#include <linux/gfp.h>
12 
13#include <linux/processor.h>	/* for CACHELINESIZE */
14 
15#define ARCH_KMALLOC_MINALIGN64 CACHELINESIZE64
16 
17#define ZERO_SIZE_PTR((void *)0) NULL((void *)0)
18 
19static inline void *
20kmalloc(size_t size, int flags)
21{
22	return malloc(size, M_DRM145, flags);
23}
24 
25static inline void *
26kmalloc_array(size_t n, size_t size, int flags)
27{
28	if (n != 0 && SIZE_MAX0xffffffffffffffffUL / n < size)
29		return NULL((void *)0);
30	return malloc(n * size, M_DRM145, flags);
31}
32 
33static inline void *
34kcalloc(size_t n, size_t size, int flags)
35{
36	if (n != 0 && SIZE_MAX0xffffffffffffffffUL / n < size)
37		return NULL((void *)0);
38	return malloc(n * size, M_DRM145, flags | M_ZERO0x0008);
39}
40 
41static inline void *
42kzalloc(size_t size, int flags)
43{
44	return malloc(size, M_DRM145, flags | M_ZERO0x0008);
9
←
Memory is allocated→
45}
46 
47static inline void
48kfree(const void *objp)
49{
50	free((void *)objp, M_DRM145, 0);
51}
52 
53#endif