Bug Summary

File:dev/pci/drm/amd/amdgpu/vcn_v2_5.c
Warning:line 1343, column 4
Value stored to 'r' is never read

Annotated Source Code

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clang -cc1 -cc1 -triple amd64-unknown-openbsd7.4 -analyze -disable-free -clear-ast-before-backend -disable-llvm-verifier -discard-value-names -main-file-name vcn_v2_5.c -analyzer-checker=core -analyzer-checker=apiModeling -analyzer-checker=unix -analyzer-checker=deadcode -analyzer-checker=security.insecureAPI.UncheckedReturn -analyzer-checker=security.insecureAPI.getpw -analyzer-checker=security.insecureAPI.gets -analyzer-checker=security.insecureAPI.mktemp -analyzer-checker=security.insecureAPI.mkstemp -analyzer-checker=security.insecureAPI.vfork -analyzer-checker=nullability.NullPassedToNonnull -analyzer-checker=nullability.NullReturnedFromNonnull -analyzer-output plist -w -setup-static-analyzer -mrelocation-model static -mframe-pointer=all -relaxed-aliasing -ffp-contract=on -fno-rounding-math -mconstructor-aliases -ffreestanding -mcmodel=kernel -target-cpu x86-64 -target-feature +retpoline-indirect-calls -target-feature +retpoline-indirect-branches -target-feature -sse2 -target-feature -sse -target-feature -3dnow -target-feature -mmx -target-feature +save-args -target-feature +retpoline-external-thunk -disable-red-zone -no-implicit-float -tune-cpu generic -debugger-tuning=gdb -fcoverage-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -nostdsysteminc -nobuiltininc -resource-dir /usr/local/llvm16/lib/clang/16 -I /usr/src/sys -I /usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -I /usr/src/sys/arch -I /usr/src/sys/dev/pci/drm/include -I /usr/src/sys/dev/pci/drm/include/uapi -I /usr/src/sys/dev/pci/drm/amd/include/asic_reg -I /usr/src/sys/dev/pci/drm/amd/include -I /usr/src/sys/dev/pci/drm/amd/amdgpu -I /usr/src/sys/dev/pci/drm/amd/display -I /usr/src/sys/dev/pci/drm/amd/display/include -I /usr/src/sys/dev/pci/drm/amd/display/dc -I /usr/src/sys/dev/pci/drm/amd/display/amdgpu_dm -I /usr/src/sys/dev/pci/drm/amd/pm/inc -I /usr/src/sys/dev/pci/drm/amd/pm/legacy-dpm -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu11 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu12 -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/smu13 -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/inc -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr -I /usr/src/sys/dev/pci/drm/amd/pm/powerplay/smumgr -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc -I /usr/src/sys/dev/pci/drm/amd/pm/swsmu/inc/pmfw_if -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc -I /usr/src/sys/dev/pci/drm/amd/display/dc/inc/hw -I /usr/src/sys/dev/pci/drm/amd/display/dc/clk_mgr -I /usr/src/sys/dev/pci/drm/amd/display/modules/inc -I /usr/src/sys/dev/pci/drm/amd/display/modules/hdcp -I /usr/src/sys/dev/pci/drm/amd/display/dmub/inc -I /usr/src/sys/dev/pci/drm/i915 -D DDB -D DIAGNOSTIC -D KTRACE -D ACCOUNTING -D KMEMSTATS -D PTRACE -D POOL_DEBUG -D CRYPTO -D SYSVMSG -D SYSVSEM -D SYSVSHM -D UVM_SWAP_ENCRYPT -D FFS -D FFS2 -D FFS_SOFTUPDATES -D UFS_DIRHASH -D QUOTA -D EXT2FS -D MFS -D NFSCLIENT -D NFSSERVER -D CD9660 -D UDF -D MSDOSFS -D FIFO -D FUSE -D SOCKET_SPLICE -D TCP_ECN -D TCP_SIGNATURE -D INET6 -D IPSEC -D PPP_BSDCOMP -D PPP_DEFLATE -D PIPEX -D MROUTING -D MPLS -D BOOT_CONFIG -D USER_PCICONF -D APERTURE -D MTRR -D NTFS -D SUSPEND -D HIBERNATE -D PCIVERBOSE -D USBVERBOSE -D WSDISPLAY_COMPAT_USL -D WSDISPLAY_COMPAT_RAWKBD -D WSDISPLAY_DEFAULTSCREENS=6 -D X86EMU -D ONEWIREVERBOSE -D MULTIPROCESSOR -D MAXUSERS=80 -D _KERNEL -O2 -Wno-pointer-sign -Wno-address-of-packed-member -Wno-constant-conversion -Wno-unused-but-set-variable -Wno-gnu-folding-constant -fdebug-compilation-dir=/usr/src/sys/arch/amd64/compile/GENERIC.MP/obj -ferror-limit 19 -fwrapv -D_RET_PROTECTOR -ret-protector -fcf-protection=branch -fgnuc-version=4.2.1 -vectorize-loops -vectorize-slp -fno-builtin-malloc -fno-builtin-calloc -fno-builtin-realloc -fno-builtin-valloc -fno-builtin-free -fno-builtin-strdup -fno-builtin-strndup -analyzer-output=html -faddrsig -o /home/ben/Projects/scan/2024-01-11-110808-61670-1 -x c /usr/src/sys/dev/pci/drm/amd/amdgpu/vcn_v2_5.c
1/*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <linux/firmware.h>
25#include <drm/drm_drv.h>
26
27#include "amdgpu.h"
28#include "amdgpu_vcn.h"
29#include "amdgpu_pm.h"
30#include "soc15.h"
31#include "soc15d.h"
32#include "vcn_v2_0.h"
33#include "mmsch_v1_0.h"
34#include "vcn_v2_5.h"
35
36#include "vcn/vcn_2_5_offset.h"
37#include "vcn/vcn_2_5_sh_mask.h"
38#include "ivsrcid/vcn/irqsrcs_vcn_2_0.h"
39
40#define VCN_VID_SOC_ADDRESS_2_00x1fa00 0x1fa00
41#define VCN1_VID_SOC_ADDRESS_3_00x48200 0x48200
42
43#define mmUVD_CONTEXT_ID_INTERNAL_OFFSET0x27 0x27
44#define mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET0x0f 0x0f
45#define mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET0x10 0x10
46#define mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET0x11 0x11
47#define mmUVD_NO_OP_INTERNAL_OFFSET0x29 0x29
48#define mmUVD_GP_SCRATCH8_INTERNAL_OFFSET0x66 0x66
49#define mmUVD_SCRATCH9_INTERNAL_OFFSET0xc01d 0xc01d
50
51#define mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET0x431 0x431
52#define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET0x3b4 0x3b4
53#define mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET0x3b5 0x3b5
54#define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET0x25c 0x25c
55
56#define VCN25_MAX_HW_INSTANCES_ARCTURUS2 2
57
58static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev);
59static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev);
60static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev);
61static int vcn_v2_5_set_powergating_state(void *handle,
62 enum amd_powergating_state state);
63static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
64 int inst_idx, struct dpg_pause_state *new_state);
65static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
66static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev);
67
68static int amdgpu_ih_clientid_vcns[] = {
69 SOC15_IH_CLIENTID_VCN,
70 SOC15_IH_CLIENTID_VCN1
71};
72
73/**
74 * vcn_v2_5_early_init - set function pointers
75 *
76 * @handle: amdgpu_device pointer
77 *
78 * Set ring and irq function pointers
79 */
80static int vcn_v2_5_early_init(void *handle)
81{
82 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
83
84 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
85 adev->vcn.num_vcn_inst = 2;
86 adev->vcn.harvest_config = 0;
87 adev->vcn.num_enc_rings = 1;
88 } else {
89 u32 harvest;
90 int i;
91
92 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
93 harvest = RREG32_SOC15(VCN, i, mmCC_UVD_HARVESTING)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x0007, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x0007), 0));
94 if (harvest & CC_UVD_HARVESTING__UVD_DISABLE_MASK0x00000002L)
95 adev->vcn.harvest_config |= 1 << i;
96 }
97 if (adev->vcn.harvest_config == (AMDGPU_VCN_HARVEST_VCN0(1 << 0) |
98 AMDGPU_VCN_HARVEST_VCN1(1 << 1)))
99 /* both instances are harvested, disable the block */
100 return -ENOENT2;
101
102 adev->vcn.num_enc_rings = 2;
103 }
104
105 vcn_v2_5_set_dec_ring_funcs(adev);
106 vcn_v2_5_set_enc_ring_funcs(adev);
107 vcn_v2_5_set_irq_funcs(adev);
108 vcn_v2_5_set_ras_funcs(adev);
109
110 return 0;
111}
112
113/**
114 * vcn_v2_5_sw_init - sw init for VCN block
115 *
116 * @handle: amdgpu_device pointer
117 *
118 * Load firmware and sw initialization
119 */
120static int vcn_v2_5_sw_init(void *handle)
121{
122 struct amdgpu_ring *ring;
123 int i, j, r;
124 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
125
126 for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
127 if (adev->vcn.harvest_config & (1 << j))
128 continue;
129 /* VCN DEC TRAP */
130 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
131 VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT124, &adev->vcn.inst[j].irq);
132 if (r)
133 return r;
134
135 /* VCN ENC TRAP */
136 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
137 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
138 i + VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE119, &adev->vcn.inst[j].irq);
139 if (r)
140 return r;
141 }
142
143 /* VCN POISON TRAP */
144 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_vcns[j],
145 VCN_2_6__SRCID_UVD_POISON160, &adev->vcn.inst[j].irq);
146 if (r)
147 return r;
148 }
149
150 r = amdgpu_vcn_sw_init(adev);
151 if (r)
152 return r;
153
154 amdgpu_vcn_setup_ucode(adev);
155
156 r = amdgpu_vcn_resume(adev);
157 if (r)
158 return r;
159
160 for (j = 0; j < adev->vcn.num_vcn_inst; j++) {
161 volatile struct amdgpu_fw_shared *fw_shared;
162
163 if (adev->vcn.harvest_config & (1 << j))
164 continue;
165 adev->vcn.internal.context_id = mmUVD_CONTEXT_ID_INTERNAL_OFFSET0x27;
166 adev->vcn.internal.ib_vmid = mmUVD_LMI_RBC_IB_VMID_INTERNAL_OFFSET0x431;
167 adev->vcn.internal.ib_bar_low = mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET0x3b4;
168 adev->vcn.internal.ib_bar_high = mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH_INTERNAL_OFFSET0x3b5;
169 adev->vcn.internal.ib_size = mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET0x25c;
170 adev->vcn.internal.gp_scratch8 = mmUVD_GP_SCRATCH8_INTERNAL_OFFSET0x66;
171
172 adev->vcn.internal.scratch9 = mmUVD_SCRATCH9_INTERNAL_OFFSET0xc01d;
173 adev->vcn.inst[j].external.scratch9 = SOC15_REG_OFFSET(VCN, j, mmUVD_SCRATCH9)(adev->reg_offset[VCN_HWIP][j][1] + 0x001d);
174 adev->vcn.internal.data0 = mmUVD_GPCOM_VCPU_DATA0_INTERNAL_OFFSET0x10;
175 adev->vcn.inst[j].external.data0 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA0)(adev->reg_offset[VCN_HWIP][j][1] + 0x0090);
176 adev->vcn.internal.data1 = mmUVD_GPCOM_VCPU_DATA1_INTERNAL_OFFSET0x11;
177 adev->vcn.inst[j].external.data1 = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_DATA1)(adev->reg_offset[VCN_HWIP][j][1] + 0x0091);
178 adev->vcn.internal.cmd = mmUVD_GPCOM_VCPU_CMD_INTERNAL_OFFSET0x0f;
179 adev->vcn.inst[j].external.cmd = SOC15_REG_OFFSET(VCN, j, mmUVD_GPCOM_VCPU_CMD)(adev->reg_offset[VCN_HWIP][j][1] + 0x008f);
180 adev->vcn.internal.nop = mmUVD_NO_OP_INTERNAL_OFFSET0x29;
181 adev->vcn.inst[j].external.nop = SOC15_REG_OFFSET(VCN, j, mmUVD_NO_OP)(adev->reg_offset[VCN_HWIP][j][1] + 0x00a9);
182
183 ring = &adev->vcn.inst[j].ring_dec;
184 ring->use_doorbell = true1;
185
186 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
187 (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) ? 2*j : 8*j);
188 snprintf(ring->name, sizeof(ring->name), "vcn_dec_%d", j);
189 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst[j].irq,
190 0, AMDGPU_RING_PRIO_DEFAULT, NULL((void *)0));
191 if (r)
192 return r;
193
194 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
195 enum amdgpu_ring_priority_level hw_prio = amdgpu_vcn_get_enc_ring_prio(i);
196
197 ring = &adev->vcn.inst[j].ring_enc[i];
198 ring->use_doorbell = true1;
199
200 ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) +
201 (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)) ? (1 + i + 2*j) : (2 + i + 8*j));
202
203 snprintf(ring->name, sizeof(ring->name), "vcn_enc_%d.%d", j, i);
204 r = amdgpu_ring_init(adev, ring, 512,
205 &adev->vcn.inst[j].irq, 0,
206 hw_prio, NULL((void *)0));
207 if (r)
208 return r;
209 }
210
211 fw_shared = adev->vcn.inst[j].fw_shared.cpu_addr;
212 fw_shared->present_flag_0 = cpu_to_le32(AMDGPU_VCN_MULTI_QUEUE_FLAG)((__uint32_t)((1 << 8)));
213
214 if (amdgpu_vcnfw_log)
215 amdgpu_vcn_fwlog_init(&adev->vcn.inst[i]);
216 }
217
218 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
219 r = amdgpu_virt_alloc_mm_table(adev);
220 if (r)
221 return r;
222 }
223
224 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15))
225 adev->vcn.pause_dpg_mode = vcn_v2_5_pause_dpg_mode;
226
227 return 0;
228}
229
230/**
231 * vcn_v2_5_sw_fini - sw fini for VCN block
232 *
233 * @handle: amdgpu_device pointer
234 *
235 * VCN suspend and free up sw allocation
236 */
237static int vcn_v2_5_sw_fini(void *handle)
238{
239 int i, r, idx;
240 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
241 volatile struct amdgpu_fw_shared *fw_shared;
242
243 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
244 for (i = 0; i < adev->vcn.num_vcn_inst; i++) {
245 if (adev->vcn.harvest_config & (1 << i))
246 continue;
247 fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
248 fw_shared->present_flag_0 = 0;
249 }
250 drm_dev_exit(idx);
251 }
252
253
254 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
255 amdgpu_virt_free_mm_table(adev);
256
257 r = amdgpu_vcn_suspend(adev);
258 if (r)
259 return r;
260
261 r = amdgpu_vcn_sw_fini(adev);
262
263 return r;
264}
265
266/**
267 * vcn_v2_5_hw_init - start and test VCN block
268 *
269 * @handle: amdgpu_device pointer
270 *
271 * Initialize the hardware, boot up the VCPU and do some testing
272 */
273static int vcn_v2_5_hw_init(void *handle)
274{
275 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
276 struct amdgpu_ring *ring;
277 int i, j, r = 0;
278
279 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
280 r = vcn_v2_5_sriov_start(adev);
281
282 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
283 if (adev->vcn.harvest_config & (1 << j))
284 continue;
285
286 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2))) {
287 adev->vcn.inst[j].ring_enc[0].sched.ready = true1;
288 adev->vcn.inst[j].ring_enc[1].sched.ready = false0;
289 adev->vcn.inst[j].ring_enc[2].sched.ready = false0;
290 adev->vcn.inst[j].ring_dec.sched.ready = true1;
291 } else {
292
293 ring = &adev->vcn.inst[j].ring_dec;
294
295 adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
296 ring->doorbell_index, j);
297
298 r = amdgpu_ring_test_helper(ring);
299 if (r)
300 goto done;
301
302 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
303 ring = &adev->vcn.inst[j].ring_enc[i];
304 r = amdgpu_ring_test_helper(ring);
305 if (r)
306 goto done;
307 }
308 }
309 }
310
311done:
312 if (!r)
313 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",printk("\0016" "[" "drm" "] " "VCN decode and encode initialized successfully(under %s).\n"
, (adev->pg_flags & (1 << 15))?"DPG Mode":"SPG Mode"
)
314 (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode")printk("\0016" "[" "drm" "] " "VCN decode and encode initialized successfully(under %s).\n"
, (adev->pg_flags & (1 << 15))?"DPG Mode":"SPG Mode"
);
315
316 return r;
317}
318
319/**
320 * vcn_v2_5_hw_fini - stop the hardware block
321 *
322 * @handle: amdgpu_device pointer
323 *
324 * Stop the VCN block, mark ring as not ready any more
325 */
326static int vcn_v2_5_hw_fini(void *handle)
327{
328 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
329 int i;
330
331 cancel_delayed_work_sync(&adev->vcn.idle_work);
332
333 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
334 if (adev->vcn.harvest_config & (1 << i))
335 continue;
336
337 if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15)) ||
338 (adev->vcn.cur_state != AMD_PG_STATE_GATE &&
339 RREG32_SOC15(VCN, i, mmUVD_STATUS)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x0080, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x0080), 0))))
340 vcn_v2_5_set_powergating_state(adev, AMD_PG_STATE_GATE);
341 }
342
343 return 0;
344}
345
346/**
347 * vcn_v2_5_suspend - suspend VCN block
348 *
349 * @handle: amdgpu_device pointer
350 *
351 * HW fini and suspend VCN block
352 */
353static int vcn_v2_5_suspend(void *handle)
354{
355 int r;
356 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
357
358 r = vcn_v2_5_hw_fini(adev);
359 if (r)
360 return r;
361
362 r = amdgpu_vcn_suspend(adev);
363
364 return r;
365}
366
367/**
368 * vcn_v2_5_resume - resume VCN block
369 *
370 * @handle: amdgpu_device pointer
371 *
372 * Resume firmware and hw init VCN block
373 */
374static int vcn_v2_5_resume(void *handle)
375{
376 int r;
377 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
378
379 r = amdgpu_vcn_resume(adev);
380 if (r)
381 return r;
382
383 r = vcn_v2_5_hw_init(adev);
384
385 return r;
386}
387
388/**
389 * vcn_v2_5_mc_resume - memory controller programming
390 *
391 * @adev: amdgpu_device pointer
392 *
393 * Let the VCN memory controller know it's offsets
394 */
395static void vcn_v2_5_mc_resume(struct amdgpu_device *adev)
396{
397 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4)(((adev->vcn.fw->size + 4) + (4096 - 1)) & ~(4096 -
1));
398 uint32_t offset;
399 int i;
400
401 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
402 if (adev->vcn.harvest_config & (1 << i))
403 continue;
404 /* cache window 0: fw */
405 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
406 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x043c), (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
i].tmr_mc_addr_lo), 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x043c)), ((adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)), 0))
407 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x043c), (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
i].tmr_mc_addr_lo), 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x043c)), ((adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)), 0));
408 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x043d), (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
i].tmr_mc_addr_hi), 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x043d)), ((adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)), 0))
409 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x043d), (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
i].tmr_mc_addr_hi), 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x043d)), ((adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)), 0));
410 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0140), 0, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0140)), (0), 0));
411 offset = 0;
412 } else {
413 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x043c), ((u32)(adev->vcn.inst[i].gpu_addr)), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
i][1] + 0x043c)), (((u32)(adev->vcn.inst[i].gpu_addr))), 0
))
414 lower_32_bits(adev->vcn.inst[i].gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x043c), ((u32)(adev->vcn.inst[i].gpu_addr)), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
i][1] + 0x043c)), (((u32)(adev->vcn.inst[i].gpu_addr))), 0
));
415 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x043d), ((u32)(((adev->vcn.inst[i].gpu_addr) >>
16) >> 16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x043d)), (((u32)(((adev
->vcn.inst[i].gpu_addr) >> 16) >> 16))), 0))
416 upper_32_bits(adev->vcn.inst[i].gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x043d), ((u32)(((adev->vcn.inst[i].gpu_addr) >>
16) >> 16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x043d)), (((u32)(((adev
->vcn.inst[i].gpu_addr) >> 16) >> 16))), 0));
417 offset = size;
418 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET0,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0140), 256 >> 3, 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0140)), (256
>> 3), 0))
419 AMDGPU_UVD_FIRMWARE_OFFSET >> 3)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0140), 256 >> 3, 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0140)), (256
>> 3), 0));
420 }
421 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE0, size)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0141), size, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x0141)), (size), 0));
422
423 /* cache window 1: stack */
424 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0468), ((u32)(adev->vcn.inst[i].gpu_addr + offset)
), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0468)), (((u32)(adev->vcn.inst[i].gpu_addr
+ offset))), 0))
425 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0468), ((u32)(adev->vcn.inst[i].gpu_addr + offset)
), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0468)), (((u32)(adev->vcn.inst[i].gpu_addr
+ offset))), 0));
426 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0469), ((u32)(((adev->vcn.inst[i].gpu_addr + offset
) >> 16) >> 16)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0469)), (((u32
)(((adev->vcn.inst[i].gpu_addr + offset) >> 16) >>
16))), 0))
427 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0469), ((u32)(((adev->vcn.inst[i].gpu_addr + offset
) >> 16) >> 16)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0469)), (((u32
)(((adev->vcn.inst[i].gpu_addr + offset) >> 16) >>
16))), 0));
428 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET1, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0142), 0, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0142)), (0), 0));
429 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0143), (128*1024), 0, VCN_HWIP) : amdgpu_device_wreg(
adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0143)), ((128
*1024)), 0));
430
431 /* cache window 2: context */
432 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x046c), ((u32)(adev->vcn.inst[i].gpu_addr + offset +
(128*1024))), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046c)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset + (128*1024)))), 0))
433 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x046c), ((u32)(adev->vcn.inst[i].gpu_addr + offset +
(128*1024))), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046c)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset + (128*1024)))), 0));
434 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x046d), ((u32)(((adev->vcn.inst[i].gpu_addr + offset
+ (128*1024)) >> 16) >> 16)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x046d)), (((u32
)(((adev->vcn.inst[i].gpu_addr + offset + (128*1024)) >>
16) >> 16))), 0))
435 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x046d), ((u32)(((adev->vcn.inst[i].gpu_addr + offset
+ (128*1024)) >> 16) >> 16)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x046d)), (((u32
)(((adev->vcn.inst[i].gpu_addr + offset + (128*1024)) >>
16) >> 16))), 0));
436 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_OFFSET2, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0144), 0, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0144)), (0), 0));
437 WREG32_SOC15(VCN, i, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0145), (512*1024), 0, VCN_HWIP) : amdgpu_device_wreg(
adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0145)), ((512
*1024)), 0));
438
439 /* non-cache window */
440 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0438), ((u32)(adev->vcn.inst[i].fw_shared.gpu_addr
)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0438)), (((u32)(adev->vcn.inst[i].fw_shared
.gpu_addr))), 0))
441 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0438), ((u32)(adev->vcn.inst[i].fw_shared.gpu_addr
)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0438)), (((u32)(adev->vcn.inst[i].fw_shared
.gpu_addr))), 0));
442 WREG32_SOC15(VCN, i, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0439), ((u32)(((adev->vcn.inst[i].fw_shared.gpu_addr
) >> 16) >> 16)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0439)), (((u32
)(((adev->vcn.inst[i].fw_shared.gpu_addr) >> 16) >>
16))), 0))
443 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0439), ((u32)(((adev->vcn.inst[i].fw_shared.gpu_addr
) >> 16) >> 16)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0439)), (((u32
)(((adev->vcn.inst[i].fw_shared.gpu_addr) >> 16) >>
16))), 0));
444 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0152), 0, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0152)), (0), 0));
445 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_SIZE0,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0153), (((sizeof(struct amdgpu_fw_shared)) + (4096 - 1
)) & ~(4096 - 1)), 0, VCN_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0153)), ((((sizeof
(struct amdgpu_fw_shared)) + (4096 - 1)) & ~(4096 - 1))),
0))
446 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0153), (((sizeof(struct amdgpu_fw_shared)) + (4096 - 1
)) & ~(4096 - 1)), 0, VCN_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0153)), ((((sizeof
(struct amdgpu_fw_shared)) + (4096 - 1)) & ~(4096 - 1))),
0));
447 }
448}
449
450static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool_Bool indirect)
451{
452 uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4)(((adev->vcn.fw->size + 4) + (4096 - 1)) & ~(4096 -
1));
453 uint32_t offset;
454
455 /* cache window 0: fw */
456 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
457 if (!indirect) {
458 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN
+ inst_idx].tmr_mc_addr_lo)), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo); } } while
(0)
459 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN
+ inst_idx].tmr_mc_addr_lo)), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo); } } while
(0)
460 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN
+ inst_idx].tmr_mc_addr_lo)), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo); } } while
(0);
461 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN
+ inst_idx].tmr_mc_addr_hi)), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi); } } while
(0)
462 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN
+ inst_idx].tmr_mc_addr_hi)), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi); } } while
(0)
463 (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), ((adev->firmware.ucode[AMDGPU_UCODE_ID_VCN
+ inst_idx].tmr_mc_addr_hi)), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi); } } while
(0);
464 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
465 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
466 } else {
467 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
468 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
469 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
470 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
471 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
472 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
473 }
474 offset = 0;
475 } else {
476 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(adev
->vcn.inst[inst_idx].gpu_addr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)
), (((u32)(adev->vcn.inst[inst_idx].gpu_addr))), 0)); ((((
adev)->virt.caps & (1 << 2)) && adev->
gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr)); } } while (0)
477 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(adev
->vcn.inst[inst_idx].gpu_addr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)
), (((u32)(adev->vcn.inst[inst_idx].gpu_addr))), 0)); ((((
adev)->virt.caps & (1 << 2)) && adev->
gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr)); } } while (0)
478 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(adev
->vcn.inst[inst_idx].gpu_addr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)
), (((u32)(adev->vcn.inst[inst_idx].gpu_addr))), 0)); ((((
adev)->virt.caps & (1 << 2)) && adev->
gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043c
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr)); } } while (0);
479 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(((adev
->vcn.inst[inst_idx].gpu_addr) >> 16) >> 16)),
0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr) >> 16) >> 16))), 0)); ((((adev
)->virt.caps & (1 << 2)) && adev->gfx
.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr) >> 16) >> 16)); } } while
(0)
480 VCN, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(((adev
->vcn.inst[inst_idx].gpu_addr) >> 16) >> 16)),
0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr) >> 16) >> 16))), 0)); ((((adev
)->virt.caps & (1 << 2)) && adev->gfx
.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr) >> 16) >> 16)); } } while
(0)
481 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(((adev
->vcn.inst[inst_idx].gpu_addr) >> 16) >> 16)),
0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr) >> 16) >> 16))), 0)); ((((adev
)->virt.caps & (1 << 2)) && adev->gfx
.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x043d
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x043d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr) >> 16) >> 16)); } } while
(0);
482 offset = size;
483 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 256 >>
3, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (256 >> 3), 0)); ((
((adev)->virt.caps & (1 << 2)) && adev->
gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 256 >> 3
; } } while (0)
484 VCN, 0, mmUVD_VCPU_CACHE_OFFSET0),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 256 >>
3, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (256 >> 3), 0)); ((
((adev)->virt.caps & (1 << 2)) && adev->
gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 256 >> 3
; } } while (0)
485 AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 256 >>
3, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (256 >> 3), 0)); ((
((adev)->virt.caps & (1 << 2)) && adev->
gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0140
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0140); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 256 >> 3
; } } while (0);
486 }
487
488 if (!indirect)
489 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), size, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (size), 0)); ((((adev)->virt.caps
& (1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0141); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0141); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0141); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = size; } } while
(0)
490 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), size, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (size), 0)); ((((adev)->virt.caps
& (1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0141); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0141); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0141); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = size; } } while
(0);
491 else
492 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0141); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0141); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0141); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
493 VCN, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0141); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0141); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0141); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
494
495 /* cache window 1: stack */
496 if (!indirect) {
497 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(adev
->vcn.inst[inst_idx].gpu_addr + offset)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)
), (((u32)(adev->vcn.inst[inst_idx].gpu_addr + offset))), 0
)); ((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0468
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr + offset)); } } while (0)
498 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(adev
->vcn.inst[inst_idx].gpu_addr + offset)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)
), (((u32)(adev->vcn.inst[inst_idx].gpu_addr + offset))), 0
)); ((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0468
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr + offset)); } } while (0)
499 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(adev
->vcn.inst[inst_idx].gpu_addr + offset)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)
), (((u32)(adev->vcn.inst[inst_idx].gpu_addr + offset))), 0
)); ((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0468
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr + offset)); } } while (0);
500 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(((adev
->vcn.inst[inst_idx].gpu_addr + offset) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr + offset) >> 16) >> 16))), 0)
); ((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0469
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr + offset) >> 16) >> 16
)); } } while (0)
501 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(((adev
->vcn.inst[inst_idx].gpu_addr + offset) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr + offset) >> 16) >> 16))), 0)
); ((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0469
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr + offset) >> 16) >> 16
)); } } while (0)
502 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(((adev
->vcn.inst[inst_idx].gpu_addr + offset) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].gpu_addr + offset) >> 16) >> 16))), 0)
); ((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0469
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr + offset) >> 16) >> 16
)); } } while (0);
503 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0142); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0142); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0142); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
504 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0142); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0142); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0142); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
505 } else {
506 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0468); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
507 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0468); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0468); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
508 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0469); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
509 VCN, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0469); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0469); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
510 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0142); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0142); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0142); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
511 VCN, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0142); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0142); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0142); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
512 }
513 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (128*1024),
0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((128*1024)), 0)); ((((adev
)->virt.caps & (1 << 2)) && adev->gfx
.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0143
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0143); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0143); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (128*1024); } }
while (0)
514 VCN, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (128*1024),
0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((128*1024)), 0)); ((((adev
)->virt.caps & (1 << 2)) && adev->gfx
.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0143
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0143); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0143); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (128*1024); } }
while (0);
515
516 /* cache window 2: context */
517 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(adev
->vcn.inst[inst_idx].gpu_addr + offset + (128*1024))), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst[inst_idx].
gpu_addr + offset + (128*1024)))), 0)); ((((adev)->virt.caps
& (1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x046c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr + offset + (128*1024))); } } while
(0)
518 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(adev
->vcn.inst[inst_idx].gpu_addr + offset + (128*1024))), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst[inst_idx].
gpu_addr + offset + (128*1024)))), 0)); ((((adev)->virt.caps
& (1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x046c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr + offset + (128*1024))); } } while
(0)
519 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(adev
->vcn.inst[inst_idx].gpu_addr + offset + (128*1024))), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (((u32)(adev->vcn.inst[inst_idx].
gpu_addr + offset + (128*1024)))), 0)); ((((adev)->virt.caps
& (1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x046c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].gpu_addr + offset + (128*1024))); } } while
(0);
520 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(((adev
->vcn.inst[inst_idx].gpu_addr + offset + (128*1024)) >>
16) >> 16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32
)(((adev->vcn.inst[inst_idx].gpu_addr + offset + (128*1024
)) >> 16) >> 16))), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x046d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr + offset + (128*1024)) >> 16
) >> 16)); } } while (0)
521 VCN, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(((adev
->vcn.inst[inst_idx].gpu_addr + offset + (128*1024)) >>
16) >> 16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32
)(((adev->vcn.inst[inst_idx].gpu_addr + offset + (128*1024
)) >> 16) >> 16))), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x046d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr + offset + (128*1024)) >> 16
) >> 16)); } } while (0)
522 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(((adev
->vcn.inst[inst_idx].gpu_addr + offset + (128*1024)) >>
16) >> 16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32
)(((adev->vcn.inst[inst_idx].gpu_addr + offset + (128*1024
)) >> 16) >> 16))), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x046d); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x046d); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].gpu_addr + offset + (128*1024)) >> 16
) >> 16)); } } while (0);
523 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0144); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0144); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0144); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
524 VCN, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0144); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0144); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0144); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
525 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (512*1024),
0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((512*1024)), 0)); ((((adev
)->virt.caps & (1 << 2)) && adev->gfx
.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0145
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0145); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0145); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (512*1024); } }
while (0)
526 VCN, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (512*1024),
0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), ((512*1024)), 0)); ((((adev
)->virt.caps & (1 << 2)) && adev->gfx
.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0145
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0145); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0145); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (512*1024); } }
while (0);
527
528 /* non-cache window */
529 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(adev
->vcn.inst[inst_idx].fw_shared.gpu_addr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)
), (((u32)(adev->vcn.inst[inst_idx].fw_shared.gpu_addr))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0438
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0438); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0438); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].fw_shared.gpu_addr)); } } while (0)
530 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(adev
->vcn.inst[inst_idx].fw_shared.gpu_addr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)
), (((u32)(adev->vcn.inst[inst_idx].fw_shared.gpu_addr))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0438
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0438); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0438); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].fw_shared.gpu_addr)); } } while (0)
531 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(adev
->vcn.inst[inst_idx].fw_shared.gpu_addr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)
), (((u32)(adev->vcn.inst[inst_idx].fw_shared.gpu_addr))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0438
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0438); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0438); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(adev->
vcn.inst[inst_idx].fw_shared.gpu_addr)); } } while (0);
532 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(((adev
->vcn.inst[inst_idx].fw_shared.gpu_addr) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].fw_shared.gpu_addr) >> 16) >> 16))), 0
)); ((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0439
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0439); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0439); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].fw_shared.gpu_addr) >> 16) >> 16
)); } } while (0)
533 VCN, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(((adev
->vcn.inst[inst_idx].fw_shared.gpu_addr) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].fw_shared.gpu_addr) >> 16) >> 16))), 0
)); ((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0439
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0439); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0439); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].fw_shared.gpu_addr) >> 16) >> 16
)); } } while (0)
534 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((u32)(((adev
->vcn.inst[inst_idx].fw_shared.gpu_addr) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((u32)(((adev->vcn.inst
[inst_idx].fw_shared.gpu_addr) >> 16) >> 16))), 0
)); ((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0439
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0439); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0439); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((u32)(((adev->
vcn.inst[inst_idx].fw_shared.gpu_addr) >> 16) >> 16
)); } } while (0);
535 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0152); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0152); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0152); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
536 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0152); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0152); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0152); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
537 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (((sizeof(struct
amdgpu_fw_shared)) + (4096 - 1)) & ~(4096 - 1)), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), ((((sizeof(struct amdgpu_fw_shared))
+ (4096 - 1)) & ~(4096 - 1))), 0)); ((((adev)->virt.caps
& (1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0153); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0153); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0153); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (((sizeof(struct
amdgpu_fw_shared)) + (4096 - 1)) & ~(4096 - 1)); } } while
(0)
538 VCN, 0, mmUVD_VCPU_NONCACHE_SIZE0),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (((sizeof(struct
amdgpu_fw_shared)) + (4096 - 1)) & ~(4096 - 1)), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), ((((sizeof(struct amdgpu_fw_shared))
+ (4096 - 1)) & ~(4096 - 1))), 0)); ((((adev)->virt.caps
& (1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0153); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0153); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0153); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (((sizeof(struct
amdgpu_fw_shared)) + (4096 - 1)) & ~(4096 - 1)); } } while
(0)
539 AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), (((sizeof(struct
amdgpu_fw_shared)) + (4096 - 1)) & ~(4096 - 1)), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), ((((sizeof(struct amdgpu_fw_shared))
+ (4096 - 1)) & ~(4096 - 1))), 0)); ((((adev)->virt.caps
& (1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0153); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0153); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0153); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = (((sizeof(struct
amdgpu_fw_shared)) + (4096 - 1)) & ~(4096 - 1)); } } while
(0);
540
541 /* VCN global tiling registers */
542 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), adev->gfx
.config.gb_addr_config, 0, VCN_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)), (adev
->gfx.config.gb_addr_config), 0)); ((((adev)->virt.caps
& (1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0049); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0049); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0049); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = adev->gfx.config
.gb_addr_config; } } while (0)
543 VCN, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), adev->gfx
.config.gb_addr_config, 0, VCN_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012)), (adev
->gfx.config.gb_addr_config), 0)); ((((adev)->virt.caps
& (1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0049); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0049); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0049); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = adev->gfx.config
.gb_addr_config; } } while (0);
544}
545
546/**
547 * vcn_v2_5_disable_clock_gating - disable VCN clock gating
548 *
549 * @adev: amdgpu_device pointer
550 *
551 * Disable clock gating for VCN block
552 */
553static void vcn_v2_5_disable_clock_gating(struct amdgpu_device *adev)
554{
555 uint32_t data;
556 int i;
557
558 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
559 if (adev->vcn.harvest_config & (1 << i))
560 continue;
561 /* UVD disable CGC */
562 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x008a, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x008a), 0));
563 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG(1ULL << 24))
564 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0;
565 else
566 data &= ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK0x00000001L;
567 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT0x2;
568 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT0x6;
569 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x008a), data, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x008a)), (data), 0));
570
571 data = RREG32_SOC15(VCN, i, mmUVD_CGC_GATE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x0088, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x0088), 0));
572 data &= ~(UVD_CGC_GATE__SYS_MASK0x00000001L
573 | UVD_CGC_GATE__UDEC_MASK0x00000002L
574 | UVD_CGC_GATE__MPEG2_MASK0x00000004L
575 | UVD_CGC_GATE__REGS_MASK0x00000008L
576 | UVD_CGC_GATE__RBC_MASK0x00000010L
577 | UVD_CGC_GATE__LMI_MC_MASK0x00000020L
578 | UVD_CGC_GATE__LMI_UMC_MASK0x00000040L
579 | UVD_CGC_GATE__IDCT_MASK0x00000080L
580 | UVD_CGC_GATE__MPRD_MASK0x00000100L
581 | UVD_CGC_GATE__MPC_MASK0x00000200L
582 | UVD_CGC_GATE__LBSI_MASK0x00000400L
583 | UVD_CGC_GATE__LRBBM_MASK0x00000800L
584 | UVD_CGC_GATE__UDEC_RE_MASK0x00001000L
585 | UVD_CGC_GATE__UDEC_CM_MASK0x00002000L
586 | UVD_CGC_GATE__UDEC_IT_MASK0x00004000L
587 | UVD_CGC_GATE__UDEC_DB_MASK0x00008000L
588 | UVD_CGC_GATE__UDEC_MP_MASK0x00010000L
589 | UVD_CGC_GATE__WCB_MASK0x00020000L
590 | UVD_CGC_GATE__VCPU_MASK0x00040000L
591 | UVD_CGC_GATE__MMSCH_MASK0x00100000L);
592
593 WREG32_SOC15(VCN, i, mmUVD_CGC_GATE, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0088), data, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x0088)), (data), 0));
594
595 SOC15_WAIT_ON_RREG(VCN, i, mmUVD_CGC_GATE, 0, 0xFFFFFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0088), 0); uint32_t
loop = adev->usec_timeout; ret = 0; while ((tmp_ & (0xFFFFFFFF
)) != (0)) { if (old_ != tmp_) { loop = adev->usec_timeout
; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev
, (adev->reg_offset[VCN_HWIP][i][1] + 0x0088), 0); loop--;
if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, i, "mmUVD_CGC_GATE", (unsigned)0, (unsigned)(tmp_ & (0xFFFFFFFF
))); ret = -60; break; } } } while (0); ret; });
596
597 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x008a, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x008a), 0));
598 data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK0x00000800L
599 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK0x00001000L
600 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK0x00002000L
601 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK0x00004000L
602 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK0x00008000L
603 | UVD_CGC_CTRL__SYS_MODE_MASK0x00010000L
604 | UVD_CGC_CTRL__UDEC_MODE_MASK0x00020000L
605 | UVD_CGC_CTRL__MPEG2_MODE_MASK0x00040000L
606 | UVD_CGC_CTRL__REGS_MODE_MASK0x00080000L
607 | UVD_CGC_CTRL__RBC_MODE_MASK0x00100000L
608 | UVD_CGC_CTRL__LMI_MC_MODE_MASK0x00200000L
609 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK0x00400000L
610 | UVD_CGC_CTRL__IDCT_MODE_MASK0x00800000L
611 | UVD_CGC_CTRL__MPRD_MODE_MASK0x01000000L
612 | UVD_CGC_CTRL__MPC_MODE_MASK0x02000000L
613 | UVD_CGC_CTRL__LBSI_MODE_MASK0x04000000L
614 | UVD_CGC_CTRL__LRBBM_MODE_MASK0x08000000L
615 | UVD_CGC_CTRL__WCB_MODE_MASK0x10000000L
616 | UVD_CGC_CTRL__VCPU_MODE_MASK0x20000000L
617 | UVD_CGC_CTRL__MMSCH_MODE_MASK0x80000000L);
618 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x008a), data, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x008a)), (data), 0));
619
620 /* turn on */
621 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x008c, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x008c), 0));
622 data |= (UVD_SUVD_CGC_GATE__SRE_MASK0x00000001L
623 | UVD_SUVD_CGC_GATE__SIT_MASK0x00000002L
624 | UVD_SUVD_CGC_GATE__SMP_MASK0x00000004L
625 | UVD_SUVD_CGC_GATE__SCM_MASK0x00000008L
626 | UVD_SUVD_CGC_GATE__SDB_MASK0x00000010L
627 | UVD_SUVD_CGC_GATE__SRE_H264_MASK0x00000020L
628 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK0x00000040L
629 | UVD_SUVD_CGC_GATE__SIT_H264_MASK0x00000080L
630 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK0x00000100L
631 | UVD_SUVD_CGC_GATE__SCM_H264_MASK0x00000200L
632 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK0x00000400L
633 | UVD_SUVD_CGC_GATE__SDB_H264_MASK0x00000800L
634 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK0x00001000L
635 | UVD_SUVD_CGC_GATE__SCLR_MASK0x00002000L
636 | UVD_SUVD_CGC_GATE__UVD_SC_MASK0x00004000L
637 | UVD_SUVD_CGC_GATE__ENT_MASK0x00008000L
638 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK0x00020000L
639 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK0x00040000L
640 | UVD_SUVD_CGC_GATE__SITE_MASK0x00080000L
641 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK0x00100000L
642 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK0x00200000L
643 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK0x00400000L
644 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK0x00800000L
645 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK0x01000000L);
646 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_GATE, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x008c), data, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x008c)), (data), 0));
647
648 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x008e, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x008e), 0));
649 data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK0x00000001L
650 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK0x00000002L
651 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK0x00000004L
652 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK0x00000008L
653 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK0x00000010L
654 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK0x00000020L
655 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK0x00000040L
656 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK0x00000080L
657 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK0x00000100L
658 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK0x00000200L);
659 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x008e), data, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x008e)), (data), 0));
660 }
661}
662
663static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
664 uint8_t sram_sel, int inst_idx, uint8_t indirect)
665{
666 uint32_t reg_data = 0;
667
668 /* enable sw clock gating control */
669 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG(1ULL << 24))
670 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0;
671 else
672 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0;
673 reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT0x2;
674 reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT0x6;
675 reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK0x00000800L |
676 UVD_CGC_CTRL__UDEC_CM_MODE_MASK0x00001000L |
677 UVD_CGC_CTRL__UDEC_IT_MODE_MASK0x00002000L |
678 UVD_CGC_CTRL__UDEC_DB_MODE_MASK0x00004000L |
679 UVD_CGC_CTRL__UDEC_MP_MODE_MASK0x00008000L |
680 UVD_CGC_CTRL__SYS_MODE_MASK0x00010000L |
681 UVD_CGC_CTRL__UDEC_MODE_MASK0x00020000L |
682 UVD_CGC_CTRL__MPEG2_MODE_MASK0x00040000L |
683 UVD_CGC_CTRL__REGS_MODE_MASK0x00080000L |
684 UVD_CGC_CTRL__RBC_MODE_MASK0x00100000L |
685 UVD_CGC_CTRL__LMI_MC_MODE_MASK0x00200000L |
686 UVD_CGC_CTRL__LMI_UMC_MODE_MASK0x00400000L |
687 UVD_CGC_CTRL__IDCT_MODE_MASK0x00800000L |
688 UVD_CGC_CTRL__MPRD_MODE_MASK0x01000000L |
689 UVD_CGC_CTRL__MPC_MODE_MASK0x02000000L |
690 UVD_CGC_CTRL__LBSI_MODE_MASK0x04000000L |
691 UVD_CGC_CTRL__LRBBM_MODE_MASK0x08000000L |
692 UVD_CGC_CTRL__WCB_MODE_MASK0x10000000L |
693 UVD_CGC_CTRL__VCPU_MODE_MASK0x20000000L |
694 UVD_CGC_CTRL__MMSCH_MODE_MASK0x80000000L);
695 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), reg_data, 0
, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[
VCN_HWIP][inst_idx][1] + 0x0012)), (reg_data), 0)); ((((adev)
->virt.caps & (1 << 2)) && adev->gfx.
rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | sram_sel << 0x1 | (
{ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x008a); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | sram_sel
<< 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008a); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008a); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = reg_data; } } while
(0)
696 VCN, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), reg_data, 0
, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset[
VCN_HWIP][inst_idx][1] + 0x0012)), (reg_data), 0)); ((((adev)
->virt.caps & (1 << 2)) && adev->gfx.
rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | sram_sel << 0x1 | (
{ uint32_t internal_reg_offset, addr; _Bool video_range, video1_range
, aon_range, aon1_range; addr = (adev->reg_offset[VCN_HWIP
][0][1] + 0x008a); addr <<= 2; video_range = ((((0xFFFFF
& addr) >= (0x1fa00)) && ((0xFFFFF & addr
) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF &
addr) >= (0x48200)) && ((0xFFFFF & addr) <
((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF & addr)
>= (0x1f800)) && ((0xFFFFF & addr) < ((0x1f800
+ 0x600))))); aon1_range = ((((0xFFFFF & addr) >= (0x48000
)) && ((0xFFFFF & addr) < ((0x48000 + 0x600)))
)); if (video_range) internal_reg_offset = ((0xFFFFF & addr
) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | sram_sel
<< 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008a); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008a); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = reg_data; } } while
(0);
697
698 /* turn off clock gating */
699 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0088); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | sram_sel
<< 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0088); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0088); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
700 VCN, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0088); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | sram_sel
<< 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0088); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0088); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
701
702 /* turn on SUVD clock gating */
703 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 1, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (1), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x008c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | sram_sel
<< 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 1; } } while (
0)
704 VCN, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 1, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (1), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x008c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | sram_sel
<< 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 1; } } while (
0);
705
706 /* turn on sw mode in UVD_SUVD_CGC_CTRL */
707 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x008e); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | sram_sel
<< 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008e); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008e); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
708 VCN, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | sram_sel << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x008e); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | sram_sel
<< 0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008e); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x008e); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
709}
710
711/**
712 * vcn_v2_5_enable_clock_gating - enable VCN clock gating
713 *
714 * @adev: amdgpu_device pointer
715 *
716 * Enable clock gating for VCN block
717 */
718static void vcn_v2_5_enable_clock_gating(struct amdgpu_device *adev)
719{
720 uint32_t data = 0;
721 int i;
722
723 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
724 if (adev->vcn.harvest_config & (1 << i))
725 continue;
726 /* enable UVD CGC */
727 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x008a, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x008a), 0));
728 if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG(1ULL << 24))
729 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0;
730 else
731 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT0x0;
732 data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT0x2;
733 data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT0x6;
734 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x008a), data, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x008a)), (data), 0));
735
736 data = RREG32_SOC15(VCN, i, mmUVD_CGC_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x008a, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x008a), 0));
737 data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK0x00000800L
738 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK0x00001000L
739 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK0x00002000L
740 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK0x00004000L
741 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK0x00008000L
742 | UVD_CGC_CTRL__SYS_MODE_MASK0x00010000L
743 | UVD_CGC_CTRL__UDEC_MODE_MASK0x00020000L
744 | UVD_CGC_CTRL__MPEG2_MODE_MASK0x00040000L
745 | UVD_CGC_CTRL__REGS_MODE_MASK0x00080000L
746 | UVD_CGC_CTRL__RBC_MODE_MASK0x00100000L
747 | UVD_CGC_CTRL__LMI_MC_MODE_MASK0x00200000L
748 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK0x00400000L
749 | UVD_CGC_CTRL__IDCT_MODE_MASK0x00800000L
750 | UVD_CGC_CTRL__MPRD_MODE_MASK0x01000000L
751 | UVD_CGC_CTRL__MPC_MODE_MASK0x02000000L
752 | UVD_CGC_CTRL__LBSI_MODE_MASK0x04000000L
753 | UVD_CGC_CTRL__LRBBM_MODE_MASK0x08000000L
754 | UVD_CGC_CTRL__WCB_MODE_MASK0x10000000L
755 | UVD_CGC_CTRL__VCPU_MODE_MASK0x20000000L);
756 WREG32_SOC15(VCN, i, mmUVD_CGC_CTRL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x008a), data, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x008a)), (data), 0));
757
758 data = RREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x008e, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x008e), 0));
759 data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK0x00000001L
760 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK0x00000002L
761 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK0x00000004L
762 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK0x00000008L
763 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK0x00000010L
764 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK0x00000020L
765 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK0x00000040L
766 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK0x00000080L
767 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK0x00000100L
768 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK0x00000200L);
769 WREG32_SOC15(VCN, i, mmUVD_SUVD_CGC_CTRL, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x008e), data, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x008e)), (data), 0));
770 }
771}
772
773static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, bool_Bool indirect)
774{
775 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
776 struct amdgpu_ring *ring;
777 uint32_t rb_bufsz, tmp;
778
779 /* disable register anti-hang mechanism */
780 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 1,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x00000003L
); tmp_ |= ((1) & ~(~0x00000003L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0)
781 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x00000003L
); tmp_ |= ((1) & ~(~0x00000003L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0);
782 /* enable dynamic power gating mode */
783 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0));
784 tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK0x00000004L;
785 tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK0x00000100L;
786 WREG32_SOC15(VCN, inst_idx, mmUVD_POWER_STATUS, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), tmp, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp)
, 0));
787
788 if (indirect)
789 adev->vcn.inst[inst_idx].dpg_sram_curr_addr = (uint32_t *)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr;
790
791 /* enable clock gating */
792 vcn_v2_5_clock_gating_dpg_mode(adev, 0, inst_idx, indirect);
793
794 /* enable VCPU clock */
795 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT0x14);
796 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK0x00000200L;
797 tmp |= UVD_VCPU_CNTL__BLK_RST_MASK0x10000000L;
798 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), tmp, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (tmp), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0156); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0156); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0156); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while
(0)
799 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), tmp, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (tmp), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0156); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0156); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0156); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while
(0);
800
801 /* disable master interupt */
802 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00a1); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
803 VCN, 0, mmUVD_MASTINT_EN), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00a1); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
804
805 /* setup mmUVD_LMI_CTRL */
806 tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK0x00000100L |
807 UVD_LMI_CTRL__REQ_MODE_MASK0x00000200L |
808 UVD_LMI_CTRL__CRC_RESET_MASK0x00004000L |
809 UVD_LMI_CTRL__MASK_MC_URGENT_MASK0x00001000L |
810 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK0x00002000L |
811 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK0x00200000L |
812 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT0x0) |
813 0x00100000L);
814 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), tmp, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (tmp), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x04a8); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x04a8); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x04a8); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while
(0)
815 VCN, 0, mmUVD_LMI_CTRL), tmp, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), tmp, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (tmp), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x04a8); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x04a8); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x04a8); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while
(0);
816
817 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0x2 <<
0x3, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x2 << 0x3), 0)); (
(((adev)->virt.caps & (1 << 2)) && adev->
gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02cc
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02cc); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02cc); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x2 << 0x3
; } } while (0)
818 VCN, 0, mmUVD_MPC_CNTL),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0x2 <<
0x3, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x2 << 0x3), 0)); (
(((adev)->virt.caps & (1 << 2)) && adev->
gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02cc
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02cc); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02cc); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x2 << 0x3
; } } while (0)
819 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0x2 <<
0x3, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x2 << 0x3), 0)); (
(((adev)->virt.caps & (1 << 2)) && adev->
gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02cc
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02cc); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02cc); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x2 << 0x3
; } } while (0);
820
821 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02ce
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
822 VCN, 0, mmUVD_MPC_SET_MUXA0),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02ce
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
823 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02ce
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
824 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02ce
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
825 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02ce
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
826 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02ce
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02ce); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0);
827
828 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d0
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
829 VCN, 0, mmUVD_MPC_SET_MUXB0),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d0
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
830 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d0
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
831 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d0
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
832 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d0
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0)
833 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (((0x1 << 0x6) | (0x2
<< 0xc) | (0x3 << 0x12) | (0x4 << 0x18))),
0)); ((((adev)->virt.caps & (1 << 2)) &&
adev->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d0
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d0); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x1 <<
0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (0x4 <<
0x18)); } } while (0);
834
835 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1 <<
0x3) | (0x2 << 0x6))), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d2); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while (
0)
836 VCN, 0, mmUVD_MPC_SET_MUX),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1 <<
0x3) | (0x2 << 0x6))), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d2); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while (
0)
837 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1 <<
0x3) | (0x2 << 0x6))), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d2); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while (
0)
838 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1 <<
0x3) | (0x2 << 0x6))), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d2); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while (
0)
839 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (((0x0 << 0x0) | (0x1 <<
0x3) | (0x2 << 0x6))), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x02d2); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x02d2); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = ((0x0 <<
0x0) | (0x1 << 0x3) | (0x2 << 0x6)); } } while (
0);
840
841 vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
842
843 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0x10, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0x10), 0)); ((((adev)->virt.caps
& (1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x026c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x026c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x026c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x10; } } while
(0)
844 VCN, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0x10, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0x10), 0)); ((((adev)->virt.caps
& (1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x026c); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x026c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x026c); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x10; } } while
(0);
845 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0x3, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0x3), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x026b); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x026b); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x026b); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x3; } } while
(0)
846 VCN, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0x3, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0x3), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x026b); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x026b); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x026b); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x3; } } while
(0);
847
848 /* enable LMI MC and UMC channels */
849 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x04a6); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x04a6); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x04a6); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
850 VCN, 0, mmUVD_LMI_CTRL2), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x04a6); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x04a6); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x04a6); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
851
852 /* unblock VCPU register access */
853 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00c6); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00c6); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00c6); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0)
854 VCN, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (0), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00c6); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00c6); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00c6); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0; } } while (
0);
855
856 tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT0x14);
857 tmp |= UVD_VCPU_CNTL__CLK_EN_MASK0x00000200L;
858 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), tmp, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (tmp), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0156); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0156); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0156); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while
(0)
859 VCN, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), tmp, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
inst_idx][1] + 0x0012)), (tmp), 0)); ((((adev)->virt.caps &
(1 << 2)) && adev->gfx.rlc.funcs &&
adev->gfx.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0011),
(0x1 << 0x0 | 0 << 0x1 | ({ uint32_t internal_reg_offset
, addr; _Bool video_range, video1_range, aon_range, aon1_range
; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x0156); addr
<<= 2; video_range = ((((0xFFFFF & addr) >= (0x1fa00
)) && ((0xFFFFF & addr) < ((0x1fa00 + 0x2600))
))); video1_range = ((((0xFFFFF & addr) >= (0x48200)) &&
((0xFFFFF & addr) < ((0x48200 + 0x2600))))); aon_range
= ((((0xFFFFF & addr) >= (0x1f800)) && ((0xFFFFF
& addr) < ((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF
& addr) >= (0x48000)) && ((0xFFFFF & addr
) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0156); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x0156); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = tmp; } } while
(0);
860
861 /* enable master interrupt */
862 WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0x00000002L
, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x00000002L), 0)); ((((adev
)->virt.caps & (1 << 2)) && adev->gfx
.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00a1
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x00000002L; }
} while (0)
863 VCN, 0, mmUVD_MASTINT_EN),do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0x00000002L
, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x00000002L), 0)); ((((adev
)->virt.caps & (1 << 2)) && adev->gfx
.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00a1
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x00000002L; }
} while (0)
864 UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect)do { if (!indirect) { ((((adev)->virt.caps & (1 <<
2)) && adev->gfx.rlc.funcs && adev->gfx
.rlc.rlcg_reg_access_supported) ? amdgpu_sriov_wreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0012), 0x00000002L
, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0012)), (0x00000002L), 0)); ((((adev
)->virt.caps & (1 << 2)) && adev->gfx
.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0011), (0x1 << 0x0 | 0 << 0x1 | ({ uint32_t
internal_reg_offset, addr; _Bool video_range, video1_range, aon_range
, aon1_range; addr = (adev->reg_offset[VCN_HWIP][0][1] + 0x00a1
); addr <<= 2; video_range = ((((0xFFFFF & addr) >=
(0x1fa00)) && ((0xFFFFF & addr) < ((0x1fa00 +
0x2600))))); video1_range = ((((0xFFFFF & addr) >= (0x48200
)) && ((0xFFFFF & addr) < ((0x48200 + 0x2600))
))); aon_range = ((((0xFFFFF & addr) >= (0x1f800)) &&
((0xFFFFF & addr) < ((0x1f800 + 0x600))))); aon1_range
= ((((0xFFFFF & addr) >= (0x48000)) && ((0xFFFFF
& addr) < ((0x48000 + 0x600))))); if (video_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1fa00) + (0x0)); else if (aon_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x1f800) + (
0x30000)); else if (video1_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x48200) + (0x0)); else if (aon1_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x48000) + (0x30000)); else internal_reg_offset
= (0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0011)), ((0x1 << 0x0 | 0 <<
0x1 | ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }) <<
0x10)), 0)); } else { *adev->vcn.inst[inst_idx].dpg_sram_curr_addr
++ = ({ uint32_t internal_reg_offset, addr; _Bool video_range
, video1_range, aon_range, aon1_range; addr = (adev->reg_offset
[VCN_HWIP][0][1] + 0x00a1); addr <<= 2; video_range = (
(((0xFFFFF & addr) >= (0x1fa00)) && ((0xFFFFF &
addr) < ((0x1fa00 + 0x2600))))); video1_range = ((((0xFFFFF
& addr) >= (0x48200)) && ((0xFFFFF & addr
) < ((0x48200 + 0x2600))))); aon_range = ((((0xFFFFF &
addr) >= (0x1f800)) && ((0xFFFFF & addr) <
((0x1f800 + 0x600))))); aon1_range = ((((0xFFFFF & addr)
>= (0x48000)) && ((0xFFFFF & addr) < ((0x48000
+ 0x600))))); if (video_range) internal_reg_offset = ((0xFFFFF
& addr) - (0x1fa00) + (0x0)); else if (aon_range) internal_reg_offset
= ((0xFFFFF & addr) - (0x1f800) + (0x30000)); else if (video1_range
) internal_reg_offset = ((0xFFFFF & addr) - (0x48200) + (
0x0)); else if (aon1_range) internal_reg_offset = ((0xFFFFF &
addr) - (0x48000) + (0x30000)); else internal_reg_offset = (
0xFFFFF & addr); internal_reg_offset >>= 2; }); *adev
->vcn.inst[inst_idx].dpg_sram_curr_addr++ = 0x00000002L; }
} while (0);
865
866 if (indirect)
867 psp_update_vcn_sram(adev, inst_idx, adev->vcn.inst[inst_idx].dpg_sram_gpu_addr,
868 (uint32_t)((uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_curr_addr -
869 (uintptr_t)adev->vcn.inst[inst_idx].dpg_sram_cpu_addr));
870
871 ring = &adev->vcn.inst[inst_idx].ring_dec;
872 /* force RBC into idle state */
873 rb_bufsz = order_base_2(ring->ring_size)drm_order(ring->ring_size);
874 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000001FL) | (0x0000001FL & ((rb_bufsz) <<
0x0)));
875 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1)(((tmp) & ~0x00001F00L) | (0x00001F00L & ((1) <<
0x8)));
876 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1)(((tmp) & ~0x00010000L) | (0x00010000L & ((1) <<
0x10)));
877 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((1) <<
0x18)));
878 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((1) <<
0x1c)));
879 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02de), tmp, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02de)), (tmp)
, 0));
880
881 /* Stall DPG before WPTR/RPTR reset */
882 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)
), (tmp_), 0); } while (0)
883 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)
), (tmp_), 0); } while (0)
884 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)
), (tmp_), 0); } while (0);
885 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
886
887 /* set the write pointer delay */
888 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR_CNTL, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e6), 0, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02e6)), (0), 0
));
889
890 /* set the wb address */
891 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR_ADDR,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02df), (((u32)(((ring->gpu_addr) >> 16) >>
16)) >> 2), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02df)), ((((u32
)(((ring->gpu_addr) >> 16) >> 16)) >> 2)
), 0))
892 (upper_32_bits(ring->gpu_addr) >> 2))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02df), (((u32)(((ring->gpu_addr) >> 16) >>
16)) >> 2), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02df)), ((((u32
)(((ring->gpu_addr) >> 16) >> 16)) >> 2)
), 0));
893
894 /* program the RB_BASE for ring buffer */
895 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0432), ((u32)(ring->gpu_addr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0432)
), (((u32)(ring->gpu_addr))), 0))
896 lower_32_bits(ring->gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0432), ((u32)(ring->gpu_addr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0432)
), (((u32)(ring->gpu_addr))), 0));
897 WREG32_SOC15(VCN, inst_idx, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0433), ((u32)(((ring->gpu_addr) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0433)), (((u32)(((ring->gpu_addr
) >> 16) >> 16))), 0))
898 upper_32_bits(ring->gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0433), ((u32)(((ring->gpu_addr) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0433)), (((u32)(((ring->gpu_addr
) >> 16) >> 16))), 0));
899
900 /* Initialize the ring buffer's read and write pointers */
901 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e0), 0, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02e0)), (0), 0
));
902
903 WREG32_SOC15(VCN, inst_idx, mmUVD_SCRATCH2, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0016), 0, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((
adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0016)), (0), 0
));
904
905 ring->wptr = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_RPTR)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e0, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][inst_idx][1] + 0x02e0), 0));
906 WREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e1), ((u32)(ring->wptr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02e1)
), (((u32)(ring->wptr))), 0))
907 lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e1), ((u32)(ring->wptr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02e1)
), (((u32)(ring->wptr))), 0));
908
909 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
910 /* Unstall DPG */
911 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0) & ~(~0x80000000L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0)
912 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0) & ~(~0x80000000L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0);
913
914 return 0;
915}
916
917static int vcn_v2_5_start(struct amdgpu_device *adev)
918{
919 struct amdgpu_ring *ring;
920 uint32_t rb_bufsz, tmp;
921 int i, j, k, r;
922
923 if (adev->pm.dpm_enabled)
924 amdgpu_dpm_enable_uvd(adev, true1);
925
926 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
927 if (adev->vcn.harvest_config & (1 << i))
928 continue;
929 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15)) {
930 r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
931 continue;
932 }
933
934 /* disable register anti-hang mechanism */
935 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0004)), 0); tmp_ &= (~0x00000003L); tmp_
|= ((0) & ~(~0x00000003L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0004)), (tmp_), 0); } while
(0)
936 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0004)), 0); tmp_ &= (~0x00000003L); tmp_
|= ((0) & ~(~0x00000003L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0004)), (tmp_), 0); } while
(0);
937
938 /* set uvd status busy */
939 tmp = RREG32_SOC15(VCN, i, mmUVD_STATUS)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x0080, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x0080), 0)) | UVD_STATUS__UVD_BUSY;
940 WREG32_SOC15(VCN, i, mmUVD_STATUS, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0080), tmp, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (tmp), 0));
941 }
942
943 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15))
944 return 0;
945
946 /*SW clock gating */
947 vcn_v2_5_disable_clock_gating(adev);
948
949 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
950 if (adev->vcn.harvest_config & (1 << i))
951 continue;
952 /* enable VCPU clock */
953 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x00000200L); tmp_
|= ((0x00000200L) & ~(~0x00000200L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0)
954 UVD_VCPU_CNTL__CLK_EN_MASK, ~UVD_VCPU_CNTL__CLK_EN_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x00000200L); tmp_
|= ((0x00000200L) & ~(~0x00000200L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0);
955
956 /* disable master interrupt */
957 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_
|= ((0) & ~(~0x00000002L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_), 0); } while
(0)
958 ~UVD_MASTINT_EN__VCPU_EN_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_
|= ((0) & ~(~0x00000002L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_), 0); } while
(0);
959
960 /* setup mmUVD_LMI_CTRL */
961 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x04a8, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x04a8), 0));
962 tmp &= ~0xff;
963 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL, tmp | 0x8|((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x04a8), tmp | 0x8| 0x00000100L | 0x00001000L | 0x00002000L
| 0x00200000L, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x04a8)), (tmp | 0x8| 0x00000100L
| 0x00001000L | 0x00002000L | 0x00200000L), 0))
964 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x04a8), tmp | 0x8| 0x00000100L | 0x00001000L | 0x00002000L
| 0x00200000L, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x04a8)), (tmp | 0x8| 0x00000100L
| 0x00001000L | 0x00002000L | 0x00200000L), 0))
965 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x04a8), tmp | 0x8| 0x00000100L | 0x00001000L | 0x00002000L
| 0x00200000L, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x04a8)), (tmp | 0x8| 0x00000100L
| 0x00001000L | 0x00002000L | 0x00200000L), 0))
966 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x04a8), tmp | 0x8| 0x00000100L | 0x00001000L | 0x00002000L
| 0x00200000L, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x04a8)), (tmp | 0x8| 0x00000100L
| 0x00001000L | 0x00002000L | 0x00200000L), 0))
967 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x04a8), tmp | 0x8| 0x00000100L | 0x00001000L | 0x00002000L
| 0x00200000L, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x04a8)), (tmp | 0x8| 0x00000100L
| 0x00001000L | 0x00002000L | 0x00200000L), 0));
968
969 /* setup mmUVD_MPC_CNTL */
970 tmp = RREG32_SOC15(VCN, i, mmUVD_MPC_CNTL)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x02cc, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x02cc), 0));
971 tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK0x00000038L;
972 tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT0x3;
973 WREG32_SOC15(VCN, i, mmUVD_MPC_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02cc), tmp, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x02cc)), (tmp), 0));
974
975 /* setup UVD_MPC_SET_MUXA0 */
976 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXA0,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02ce), ((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x02ce)), (((0x1
<< 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (
0x4 << 0x18))), 0))
977 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02ce), ((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x02ce)), (((0x1
<< 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (
0x4 << 0x18))), 0))
978 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02ce), ((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x02ce)), (((0x1
<< 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (
0x4 << 0x18))), 0))
979 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02ce), ((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x02ce)), (((0x1
<< 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (
0x4 << 0x18))), 0))
980 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02ce), ((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x02ce)), (((0x1
<< 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (
0x4 << 0x18))), 0));
981
982 /* setup UVD_MPC_SET_MUXB0 */
983 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUXB0,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02d0), ((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x02d0)), (((0x1
<< 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (
0x4 << 0x18))), 0))
984 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02d0), ((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x02d0)), (((0x1
<< 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (
0x4 << 0x18))), 0))
985 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02d0), ((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x02d0)), (((0x1
<< 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (
0x4 << 0x18))), 0))
986 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02d0), ((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x02d0)), (((0x1
<< 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (
0x4 << 0x18))), 0))
987 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02d0), ((0x1 << 0x6) | (0x2 << 0xc) | (0x3
<< 0x12) | (0x4 << 0x18)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x02d0)), (((0x1
<< 0x6) | (0x2 << 0xc) | (0x3 << 0x12) | (
0x4 << 0x18))), 0));
988
989 /* setup mmUVD_MPC_SET_MUX */
990 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02d2), ((0x0 << 0x0) | (0x1 << 0x3) | (0x2
<< 0x6)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x02d2)), (((0x0 << 0x0
) | (0x1 << 0x3) | (0x2 << 0x6))), 0))
991 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02d2), ((0x0 << 0x0) | (0x1 << 0x3) | (0x2
<< 0x6)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x02d2)), (((0x0 << 0x0
) | (0x1 << 0x3) | (0x2 << 0x6))), 0))
992 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02d2), ((0x0 << 0x0) | (0x1 << 0x3) | (0x2
<< 0x6)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x02d2)), (((0x0 << 0x0
) | (0x1 << 0x3) | (0x2 << 0x6))), 0))
993 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02d2), ((0x0 << 0x0) | (0x1 << 0x3) | (0x2
<< 0x6)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x02d2)), (((0x0 << 0x0
) | (0x1 << 0x3) | (0x2 << 0x6))), 0));
994 }
995
996 vcn_v2_5_mc_resume(adev);
997
998 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
999 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[i].fw_shared.cpu_addr;
1000 if (adev->vcn.harvest_config & (1 << i))
1001 continue;
1002 /* VCN global tiling registers */
1003 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0049), adev->gfx.config.gb_addr_config, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
i][1] + 0x0049)), (adev->gfx.config.gb_addr_config), 0))
1004 adev->gfx.config.gb_addr_config)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0049), adev->gfx.config.gb_addr_config, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
i][1] + 0x0049)), (adev->gfx.config.gb_addr_config), 0));
1005 WREG32_SOC15(VCN, i, mmUVD_GFX8_ADDR_CONFIG,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0049), adev->gfx.config.gb_addr_config, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
i][1] + 0x0049)), (adev->gfx.config.gb_addr_config), 0))
1006 adev->gfx.config.gb_addr_config)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0049), adev->gfx.config.gb_addr_config, 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
i][1] + 0x0049)), (adev->gfx.config.gb_addr_config), 0));
1007
1008 /* enable LMI MC and UMC channels */
1009 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_LMI_CTRL2), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x04a6)), 0); tmp_ &= (~0x00000100L); tmp_
|= ((0) & ~(~0x00000100L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x04a6)), (tmp_), 0); } while
(0)
1010 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x04a6)), 0); tmp_ &= (~0x00000100L); tmp_
|= ((0) & ~(~0x00000100L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x04a6)), (tmp_), 0); } while
(0);
1011
1012 /* unblock VCPU register access */
1013 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_
|= ((0) & ~(~0x00000008L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_), 0); } while
(0)
1014 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_
|= ((0) & ~(~0x00000008L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_), 0); } while
(0);
1015
1016 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0) & ~(~0x10000000L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0); } while
(0)
1017 ~UVD_VCPU_CNTL__BLK_RST_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0) & ~(~0x10000000L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0); } while
(0);
1018
1019 for (k = 0; k < 10; ++k) {
1020 uint32_t status;
1021
1022 for (j = 0; j < 100; ++j) {
1023 status = RREG32_SOC15(VCN, i, mmUVD_STATUS)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x0080, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x0080), 0));
1024 if (status & 2)
1025 break;
1026 if (amdgpu_emu_mode == 1)
1027 drm_msleep(500)mdelay(500);
1028 else
1029 mdelay(10);
1030 }
1031 r = 0;
1032 if (status & 2)
1033 break;
1034
1035 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n")__drm_err("VCN decode not responding, trying to reset the VCPU!!!\n"
);
1036 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0)
1037 UVD_VCPU_CNTL__BLK_RST_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0)
1038 ~UVD_VCPU_CNTL__BLK_RST_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0);
1039 mdelay(10);
1040 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0) & ~(~0x10000000L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0); } while
(0)
1041 ~UVD_VCPU_CNTL__BLK_RST_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0) & ~(~0x10000000L)); amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0); } while
(0);
1042
1043 mdelay(10);
1044 r = -1;
1045 }
1046
1047 if (r) {
1048 DRM_ERROR("VCN decode not responding, giving up!!!\n")__drm_err("VCN decode not responding, giving up!!!\n");
1049 return r;
1050 }
1051
1052 /* enable master interrupt */
1053 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_MASTINT_EN),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_
|= ((0x00000002L) & ~(~0x00000002L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_
), 0); } while (0)
1054 UVD_MASTINT_EN__VCPU_EN_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_
|= ((0x00000002L) & ~(~0x00000002L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_
), 0); } while (0)
1055 ~UVD_MASTINT_EN__VCPU_EN_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00a1)), 0); tmp_ &= (~0x00000002L); tmp_
|= ((0x00000002L) & ~(~0x00000002L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00a1)), (tmp_
), 0); } while (0);
1056
1057 /* clear the busy bit of VCN_STATUS */
1058 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0080)), 0); tmp_ &= (~(2 << 0x1
)); tmp_ |= ((0) & ~(~(2 << 0x1))); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (tmp_
), 0); } while (0)
1059 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT))do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0080)), 0); tmp_ &= (~(2 << 0x1
)); tmp_ |= ((0) & ~(~(2 << 0x1))); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (tmp_
), 0); } while (0);
1060
1061 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_VMID, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x04b0), 0, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x04b0)), (0), 0));
1062
1063 ring = &adev->vcn.inst[i].ring_dec;
1064 /* force RBC into idle state */
1065 rb_bufsz = order_base_2(ring->ring_size)drm_order(ring->ring_size);
1066 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000001FL) | (0x0000001FL & ((rb_bufsz) <<
0x0)));
1067 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1)(((tmp) & ~0x00001F00L) | (0x00001F00L & ((1) <<
0x8)));
1068 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1)(((tmp) & ~0x00010000L) | (0x00010000L & ((1) <<
0x10)));
1069 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((1) <<
0x18)));
1070 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((1) <<
0x1c)));
1071 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_CNTL, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02de), tmp, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x02de)), (tmp), 0));
1072
1073 fw_shared->multi_queue.decode_queue_mode |= FW_QUEUE_RING_RESET;
1074 /* program the RB_BASE for ring buffer */
1075 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0432), ((u32)(ring->gpu_addr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0432)), (((u32
)(ring->gpu_addr))), 0))
1076 lower_32_bits(ring->gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0432), ((u32)(ring->gpu_addr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0432)), (((u32
)(ring->gpu_addr))), 0));
1077 WREG32_SOC15(VCN, i, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0433), ((u32)(((ring->gpu_addr) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0433)), (((u32)(((ring->gpu_addr) >>
16) >> 16))), 0))
1078 upper_32_bits(ring->gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0433), ((u32)(((ring->gpu_addr) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0433)), (((u32)(((ring->gpu_addr) >>
16) >> 16))), 0));
1079
1080 /* Initialize the ring buffer's read and write pointers */
1081 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02e0), 0, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x02e0)), (0), 0));
1082
1083 ring->wptr = RREG32_SOC15(VCN, i, mmUVD_RBC_RB_RPTR)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x02e0, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x02e0), 0));
1084 WREG32_SOC15(VCN, i, mmUVD_RBC_RB_WPTR,((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02e1), ((u32)(ring->wptr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x02e1)), (((u32
)(ring->wptr))), 0))
1085 lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x02e1), ((u32)(ring->wptr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x02e1)), (((u32
)(ring->wptr))), 0));
1086 fw_shared->multi_queue.decode_queue_mode &= ~FW_QUEUE_RING_RESET;
1087
1088 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1089 ring = &adev->vcn.inst[i].ring_enc[0];
1090 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x00ad), ((u32)(ring->wptr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00ad)), (((u32
)(ring->wptr))), 0));
1091 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x00ae), ((u32)(ring->wptr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00ae)), (((u32
)(ring->wptr))), 0));
1092 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO, ring->gpu_addr)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x00aa), ring->gpu_addr, 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00aa)), (ring
->gpu_addr), 0));
1093 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x00ab), ((u32)(((ring->gpu_addr) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00ab)), (((u32)(((ring->gpu_addr) >>
16) >> 16))), 0));
1094 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE, ring->ring_size / 4)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x00ac), ring->ring_size / 4, 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00ac)), (ring
->ring_size / 4), 0));
1095 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1096
1097 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1098 ring = &adev->vcn.inst[i].ring_enc[1];
1099 WREG32_SOC15(VCN, i, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x00b2), ((u32)(ring->wptr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00b2)), (((u32
)(ring->wptr))), 0));
1100 WREG32_SOC15(VCN, i, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x00b3), ((u32)(ring->wptr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00b3)), (((u32
)(ring->wptr))), 0));
1101 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_LO2, ring->gpu_addr)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x00af), ring->gpu_addr, 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00af)), (ring
->gpu_addr), 0));
1102 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x00b0), ((u32)(((ring->gpu_addr) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00b0)), (((u32)(((ring->gpu_addr) >>
16) >> 16))), 0));
1103 WREG32_SOC15(VCN, i, mmUVD_RB_SIZE2, ring->ring_size / 4)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x00b1), ring->ring_size / 4, 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00b1)), (ring
->ring_size / 4), 0));
1104 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1105 }
1106
1107 return 0;
1108}
1109
1110static int vcn_v2_5_mmsch_start(struct amdgpu_device *adev,
1111 struct amdgpu_mm_table *table)
1112{
1113 uint32_t data = 0, loop = 0, size = 0;
1114 uint64_t addr = table->gpu_addr;
1115 struct mmsch_v1_1_init_header *header = NULL((void *)0);
1116
1117 header = (struct mmsch_v1_1_init_header *)table->cpu_addr;
1118 size = header->total_size;
1119
1120 /*
1121 * 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of
1122 * memory descriptor location
1123 */
1124 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][0]
[0] + 0x000c), ((u32)(addr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][0][0] + 0x000c)), (((u32
)(addr))), 0));
1125 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][0]
[0] + 0x000d), ((u32)(((addr) >> 16) >> 16)), 0, VCN_HWIP
) : amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][
0][0] + 0x000d)), (((u32)(((addr) >> 16) >> 16)))
, 0));
1126
1127 /* 2, update vmid of descriptor */
1128 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][0][
0] + 0x000b, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][0][0] + 0x000b), 0));
1129 data &= ~MMSCH_VF_VMID__VF_CTX_VMID_MASK0x0000001FL;
1130 /* use domain0 for MM scheduler */
1131 data |= (0 << MMSCH_VF_VMID__VF_CTX_VMID__SHIFT0x0);
1132 WREG32_SOC15(VCN, 0, mmMMSCH_VF_VMID, data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][0]
[0] + 0x000b), data, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][0][0] + 0x000b)), (data), 0));
1133
1134 /* 3, notify mmsch about the size of this descriptor */
1135 WREG32_SOC15(VCN, 0, mmMMSCH_VF_CTX_SIZE, size)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][0]
[0] + 0x000e), size, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][0][0] + 0x000e)), (size), 0));
1136
1137 /* 4, set resp to zero */
1138 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][0]
[0] + 0x0013), 0, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][0][0] + 0x0013)), (0), 0));
1139
1140 /*
1141 * 5, kick off the initialization and wait until
1142 * VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero
1143 */
1144 WREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_HOST, 0x10000001)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][0]
[0] + 0x0012), 0x10000001, 0, VCN_HWIP) : amdgpu_device_wreg(
adev, ((adev->reg_offset[VCN_HWIP][0][0] + 0x0012)), (0x10000001
), 0));
1145
1146 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][0][
0] + 0x0013, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][0][0] + 0x0013), 0));
1147 loop = 10;
1148 while ((data & 0x10000002) != 0x10000002) {
1149 udelay(100);
1150 data = RREG32_SOC15(VCN, 0, mmMMSCH_VF_MAILBOX_RESP)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][0][
0] + 0x0013, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][0][0] + 0x0013), 0));
1151 loop--;
1152 if (!loop)
1153 break;
1154 }
1155
1156 if (!loop) {
1157 dev_err(adev->dev,printf("drm:pid%d:%s *ERROR* " "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , data)
1158 "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n",printf("drm:pid%d:%s *ERROR* " "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , data)
1159 data)printf("drm:pid%d:%s *ERROR* " "failed to init MMSCH, mmMMSCH_VF_MAILBOX_RESP = %x\n"
, ({struct cpu_info *__ci; asm volatile("movq %%gs:%P1,%0" : "=r"
(__ci) :"n" (__builtin_offsetof(struct cpu_info, ci_self)));
__ci;})->ci_curproc->p_p->ps_pid, __func__ , data);
1160 return -EBUSY16;
1161 }
1162
1163 return 0;
1164}
1165
1166static int vcn_v2_5_sriov_start(struct amdgpu_device *adev)
1167{
1168 struct amdgpu_ring *ring;
1169 uint32_t offset, size, tmp, i, rb_bufsz;
1170 uint32_t table_size = 0;
1171 struct mmsch_v1_0_cmd_direct_write direct_wt = { { 0 } };
1172 struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { { 0 } };
1173 struct mmsch_v1_0_cmd_end end = { { 0 } };
1174 uint32_t *init_table = adev->virt.mm_table.cpu_addr;
1175 struct mmsch_v1_1_init_header *header = (struct mmsch_v1_1_init_header *)init_table;
1176
1177 direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
1178 direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
1179 end.cmd_header.command_type = MMSCH_COMMAND__END;
1180
1181 header->version = MMSCH_VERSION0x1;
1182 header->total_size = sizeof(struct mmsch_v1_1_init_header) >> 2;
1183 init_table += header->total_size;
1184
1185 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1186 header->eng[i].table_offset = header->total_size;
1187 header->eng[i].init_status = 0;
1188 header->eng[i].table_size = 0;
1189
1190 table_size = 0;
1191
1192 MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT({ mmsch_v1_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, init_table
, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (~UVD_STATUS__UVD_BUSY
), (UVD_STATUS__UVD_BUSY)); init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write
)/4; }
1193 SOC15_REG_OFFSET(VCN, i, mmUVD_STATUS),{ mmsch_v1_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, init_table
, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (~UVD_STATUS__UVD_BUSY
), (UVD_STATUS__UVD_BUSY)); init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write
)/4; }
1194 ~UVD_STATUS__UVD_BUSY, UVD_STATUS__UVD_BUSY){ mmsch_v1_0_insert_direct_rd_mod_wt(&direct_rd_mod_wt, init_table
, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0080)), (~UVD_STATUS__UVD_BUSY
), (UVD_STATUS__UVD_BUSY)); init_table += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_read_modify_write
)/4; };
1195
1196 size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4)(((adev->vcn.fw->size + 4) + (4096 - 1)) & ~(4096 -
1));
1197 /* mc resume*/
1198 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
1199 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1200 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1201 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1202 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_lo)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; };
1203 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1204 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1205 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1206 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (adev->firmware
.ucode[AMDGPU_UCODE_ID_VCN + i].tmr_mc_addr_hi)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; };
1207 offset = 0;
1208 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0140)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1209 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0), 0){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0140)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; };
1210 } else {
1211 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (((u32)(adev->
vcn.inst[i].gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1212 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (((u32)(adev->
vcn.inst[i].gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1213 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (((u32)(adev->
vcn.inst[i].gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1214 lower_32_bits(adev->vcn.inst[i].gpu_addr)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043c)), (((u32)(adev->
vcn.inst[i].gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; };
1215 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (((u32)(((adev->
vcn.inst[i].gpu_addr) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1216 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (((u32)(((adev->
vcn.inst[i].gpu_addr) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1217 mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (((u32)(((adev->
vcn.inst[i].gpu_addr) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1218 upper_32_bits(adev->vcn.inst[i].gpu_addr)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x043d)), (((u32)(((adev->
vcn.inst[i].gpu_addr) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1219 offset = size;
1220 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0140)), (256 >> 3))
; init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4;
table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1221 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET0),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0140)), (256 >> 3))
; init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4;
table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1222 AMDGPU_UVD_FIRMWARE_OFFSET >> 3){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0140)), (256 >> 3))
; init_table += sizeof(struct mmsch_v1_0_cmd_direct_write)/4;
table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1223 }
1224
1225 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0141)), (size)); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1226 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE0),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0141)), (size)); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1227 size){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0141)), (size)); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1228 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0468)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset)))); init_table += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; }
1229 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0468)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset)))); init_table += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; }
1230 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0468)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset)))); init_table += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; }
1231 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0468)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset)))); init_table += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; };
1232 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0469)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1233 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0469)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1234 mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0469)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1235 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0469)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset) >> 16) >> 16)))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1236 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0142)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1237 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET1),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0142)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1238 0){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0142)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; };
1239 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0143)), ((128*1024))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1240 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE1),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0143)), ((128*1024))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1241 AMDGPU_VCN_STACK_SIZE){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0143)), ((128*1024))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1242 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046c)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset + (128*1024))))); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1243 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046c)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset + (128*1024))))); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1244 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046c)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset + (128*1024))))); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1245 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset +{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046c)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset + (128*1024))))); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1246 AMDGPU_VCN_STACK_SIZE)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046c)), (((u32)(adev->
vcn.inst[i].gpu_addr + offset + (128*1024))))); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; };
1247 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046d)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset + (128*1024)) >> 16) >>
16)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1248 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046d)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset + (128*1024)) >> 16) >>
16)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1249 mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046d)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset + (128*1024)) >> 16) >>
16)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1250 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset +{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046d)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset + (128*1024)) >> 16) >>
16)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1251 AMDGPU_VCN_STACK_SIZE)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x046d)), (((u32)(((adev->
vcn.inst[i].gpu_addr + offset + (128*1024)) >> 16) >>
16)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; };
1252 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0144)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1253 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_OFFSET2),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0144)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; }
1254 0){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0144)), (0)); init_table +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof
(struct mmsch_v1_0_cmd_direct_write)/4; };
1255 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0145)), ((512*1024))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1256 SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CACHE_SIZE2),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0145)), ((512*1024))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1257 AMDGPU_VCN_CONTEXT_SIZE){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0145)), ((512*1024))); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1258
1259 ring = &adev->vcn.inst[i].ring_enc[0];
1260 ring->wptr = 0;
1261
1262 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00aa)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1263 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_LO),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00aa)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1264 lower_32_bits(ring->gpu_addr)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00aa)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; };
1265 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00ab)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; }
1266 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_BASE_HI),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00ab)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; }
1267 upper_32_bits(ring->gpu_addr)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00ab)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; };
1268 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00ac)), (ring->ring_size
/ 4)); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1269 SOC15_REG_OFFSET(VCN, i, mmUVD_RB_SIZE),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00ac)), (ring->ring_size
/ 4)); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1270 ring->ring_size / 4){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x00ac)), (ring->ring_size
/ 4)); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; };
1271
1272 ring = &adev->vcn.inst[i].ring_dec;
1273 ring->wptr = 0;
1274 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0432)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1275 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0432)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1276 mmUVD_LMI_RBC_RB_64BIT_BAR_LOW),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0432)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; }
1277 lower_32_bits(ring->gpu_addr)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0432)), (((u32)(ring->
gpu_addr)))); init_table += sizeof(struct mmsch_v1_0_cmd_direct_write
)/4; table_size += sizeof(struct mmsch_v1_0_cmd_direct_write)
/4; };
1278 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0433)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; }
1279 SOC15_REG_OFFSET(VCN, i,{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0433)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; }
1280 mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH),{ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0433)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; }
1281 upper_32_bits(ring->gpu_addr)){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0433)), (((u32)(((ring->
gpu_addr) >> 16) >> 16)))); init_table += sizeof(
struct mmsch_v1_0_cmd_direct_write)/4; table_size += sizeof(struct
mmsch_v1_0_cmd_direct_write)/4; };
1282
1283 /* force RBC into idle state */
1284 rb_bufsz = order_base_2(ring->ring_size)drm_order(ring->ring_size);
1285 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz)(((0) & ~0x0000001FL) | (0x0000001FL & ((rb_bufsz) <<
0x0)));
1286 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1)(((tmp) & ~0x00001F00L) | (0x00001F00L & ((1) <<
0x8)));
1287 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1)(((tmp) & ~0x00010000L) | (0x00010000L & ((1) <<
0x10)));
1288 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1)(((tmp) & ~0x01000000L) | (0x01000000L & ((1) <<
0x18)));
1289 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1)(((tmp) & ~0x10000000L) | (0x10000000L & ((1) <<
0x1c)));
1290 MMSCH_V1_0_INSERT_DIRECT_WT({ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x02de)), (tmp)); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; }
1291 SOC15_REG_OFFSET(VCN, i, mmUVD_RBC_RB_CNTL), tmp){ mmsch_v1_0_insert_direct_wt(&direct_wt, init_table, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x02de)), (tmp)); init_table
+= sizeof(struct mmsch_v1_0_cmd_direct_write)/4; table_size +=
sizeof(struct mmsch_v1_0_cmd_direct_write)/4; };
1292
1293 /* add end packet */
1294 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end))__builtin_memcpy(((void *)init_table), (&end), (sizeof(struct
mmsch_v1_0_cmd_end)));
1295 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1296 init_table += sizeof(struct mmsch_v1_0_cmd_end) / 4;
1297
1298 /* refine header */
1299 header->eng[i].table_size = table_size;
1300 header->total_size += table_size;
1301 }
1302
1303 return vcn_v2_5_mmsch_start(adev, &adev->virt.mm_table);
1304}
1305
1306static int vcn_v2_5_stop_dpg_mode(struct amdgpu_device *adev, int inst_idx)
1307{
1308 uint32_t tmp;
1309
1310 /* Wait for power status to be 1 */
1311 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (1)) { if (old_ != tmp_) { loop =
adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ =
amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; })
1312 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (1)) { if (old_ != tmp_) { loop =
adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ =
amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; });
1313
1314 /* wait for read ptr to be equal to write ptr */
1315 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00ae, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][inst_idx][1] + 0x00ae), 0));
1316 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00ad),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0xFFFFFFFF)) != (tmp)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00ad), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_RB_RPTR", (unsigned)tmp, (unsigned)(tmp_ &
(0xFFFFFFFF))); ret = -60; break; } } } while (0); ret; });
1317
1318 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00b3, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][inst_idx][1] + 0x00b3), 0));
1319 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00b2),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0xFFFFFFFF)) != (tmp)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00b2), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_RB_RPTR2", (unsigned)tmp, (unsigned)(tmp_ &
(0xFFFFFFFF))); ret = -60; break; } } } while (0); ret; });
1320
1321 tmp = RREG32_SOC15(VCN, inst_idx, mmUVD_RBC_RB_WPTR)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e1, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][inst_idx][1] + 0x02e1), 0)) & 0x7FFFFFFF;
1322 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x02e0),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0xFFFFFFFF)) != (tmp)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x02e0), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_RBC_RB_RPTR", (unsigned)tmp, (unsigned)(tmp_
& (0xFFFFFFFF))); ret = -60; break; } } } while (0); ret
; });
1323
1324 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (1)) { if (old_ != tmp_) { loop =
adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ =
amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; })
1325 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (1)) { if (old_ != tmp_) { loop =
adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_ =
amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; });
1326
1327 /* disable dynamic power gating mode */
1328 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x00000004L
); tmp_ |= ((0) & ~(~0x00000004L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0)
1329 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x00000004L
); tmp_ |= ((0) & ~(~0x00000004L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0);
1330
1331 return 0;
1332}
1333
1334static int vcn_v2_5_stop(struct amdgpu_device *adev)
1335{
1336 uint32_t tmp;
1337 int i, r = 0;
1338
1339 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1340 if (adev->vcn.harvest_config & (1 << i))
1341 continue;
1342 if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG(1 << 15)) {
1343 r = vcn_v2_5_stop_dpg_mode(adev, i);
Value stored to 'r' is never read
1344 continue;
1345 }
1346
1347 /* wait for vcn idle */
1348 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); uint32_t
loop = adev->usec_timeout; ret = 0; while ((tmp_ & (0x7
)) != (UVD_STATUS__IDLE)) { if (old_ != tmp_) { loop = adev->
usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); loop
--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, i, "mmUVD_STATUS", (unsigned)UVD_STATUS__IDLE, (unsigned)(tmp_
& (0x7))); ret = -60; break; } } } while (0); ret; });
1349 if (r)
1350 return r;
1351
1352 tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK0x00000008L |
1353 UVD_LMI_STATUS__READ_CLEAN_MASK0x00000001L |
1354 UVD_LMI_STATUS__WRITE_CLEAN_MASK0x00000002L |
1355 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK0x00000004L;
1356 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x04a9), 0); uint32_t
loop = adev->usec_timeout; ret = 0; while ((tmp_ & (tmp
)) != (tmp)) { if (old_ != tmp_) { loop = adev->usec_timeout
; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev
, (adev->reg_offset[VCN_HWIP][i][1] + 0x04a9), 0); loop--;
if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, i, "mmUVD_LMI_STATUS", (unsigned)tmp, (unsigned)(tmp_ &
(tmp))); ret = -60; break; } } } while (0); ret; });
1357 if (r)
1358 return r;
1359
1360 /* block LMI UMC channel */
1361 tmp = RREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x04a6, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x04a6), 0));
1362 tmp |= UVD_LMI_CTRL2__STALL_ARB_UMC_MASK0x00000100L;
1363 WREG32_SOC15(VCN, i, mmUVD_LMI_CTRL2, tmp)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x04a6), tmp, 0, VCN_HWIP) : amdgpu_device_wreg(adev, (
(adev->reg_offset[VCN_HWIP][i][1] + 0x04a6)), (tmp), 0));
1364
1365 tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK0x00000200L|
1366 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK0x00000040L;
1367 r = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_LMI_STATUS, tmp, tmp)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x04a9), 0); uint32_t
loop = adev->usec_timeout; ret = 0; while ((tmp_ & (tmp
)) != (tmp)) { if (old_ != tmp_) { loop = adev->usec_timeout
; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev
, (adev->reg_offset[VCN_HWIP][i][1] + 0x04a9), 0); loop--;
if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, i, "mmUVD_LMI_STATUS", (unsigned)tmp, (unsigned)(tmp_ &
(tmp))); ret = -60; break; } } } while (0); ret; });
1368 if (r)
1369 return r;
1370
1371 /* block VCPU register access */
1372 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_RB_ARB_CTRL),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_
|= ((0x00000008L) & ~(~0x00000008L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_
), 0); } while (0)
1373 UVD_RB_ARB_CTRL__VCPU_DIS_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_
|= ((0x00000008L) & ~(~0x00000008L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_
), 0); } while (0)
1374 ~UVD_RB_ARB_CTRL__VCPU_DIS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x00c6)), 0); tmp_ &= (~0x00000008L); tmp_
|= ((0x00000008L) & ~(~0x00000008L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x00c6)), (tmp_
), 0); } while (0);
1375
1376 /* reset VCPU */
1377 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0)
1378 UVD_VCPU_CNTL__BLK_RST_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0)
1379 ~UVD_VCPU_CNTL__BLK_RST_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~0x10000000L); tmp_
|= ((0x10000000L) & ~(~0x10000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_
), 0); } while (0);
1380
1381 /* disable VCPU clock */
1382 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_VCPU_CNTL), 0,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~(0x00000200L))
; tmp_ |= ((0) & ~(~(0x00000200L))); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0
); } while (0)
1383 ~(UVD_VCPU_CNTL__CLK_EN_MASK))do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0156)), 0); tmp_ &= (~(0x00000200L))
; tmp_ |= ((0) & ~(~(0x00000200L))); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0156)), (tmp_), 0
); } while (0);
1384
1385 /* clear status */
1386 WREG32_SOC15(VCN, i, mmUVD_STATUS, 0)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][i]
[1] + 0x0080), 0, 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev
->reg_offset[VCN_HWIP][i][1] + 0x0080)), (0), 0));
1387
1388 vcn_v2_5_enable_clock_gating(adev);
1389
1390 /* enable register anti-hang mechanism */
1391 WREG32_P(SOC15_REG_OFFSET(VCN, i, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0004)), 0); tmp_ &= (~0x00000003L); tmp_
|= ((0x00000003L) & ~(~0x00000003L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0004)), (tmp_
), 0); } while (0)
1392 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0004)), 0); tmp_ &= (~0x00000003L); tmp_
|= ((0x00000003L) & ~(~0x00000003L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0004)), (tmp_
), 0); } while (0)
1393 ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][i][1] + 0x0004)), 0); tmp_ &= (~0x00000003L); tmp_
|= ((0x00000003L) & ~(~0x00000003L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][i][1] + 0x0004)), (tmp_
), 0); } while (0);
1394 }
1395
1396 if (adev->pm.dpm_enabled)
1397 amdgpu_dpm_enable_uvd(adev, false0);
1398
1399 return 0;
1400}
1401
1402static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
1403 int inst_idx, struct dpg_pause_state *new_state)
1404{
1405 struct amdgpu_ring *ring;
1406 uint32_t reg_data = 0;
1407 int ret_code = 0;
1408
1409 /* pause/unpause if state is changed */
1410 if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1411 DRM_DEBUG("dpg pause state changed %d -> %d",___drm_dbg(((void *)0), DRM_UT_CORE, "dpg pause state changed %d -> %d"
, adev->vcn.inst[inst_idx].pause_state.fw_based, new_state
->fw_based)
1412 adev->vcn.inst[inst_idx].pause_state.fw_based, new_state->fw_based)___drm_dbg(((void *)0), DRM_UT_CORE, "dpg pause state changed %d -> %d"
, adev->vcn.inst[inst_idx].pause_state.fw_based, new_state
->fw_based);
1413 reg_data = RREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0014, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][inst_idx][1] + 0x0014), 0)) &
1414 (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK0x00000008L);
1415
1416 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1417 ret_code = SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (0x1)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)0x1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; })
1418 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (0x1)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)0x1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; });
1419
1420 if (!ret_code) {
1421 volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst[inst_idx].fw_shared.cpu_addr;
1422
1423 /* pause DPG */
1424 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK0x00000004L;
1425 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0014), reg_data, 0, VCN_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0014)), (reg_data
), 0));
1426
1427 /* wait for ACK */
1428 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_DPG_PAUSE,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0014),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000008L)) != (0x00000008L)) { if (old_ != tmp_
) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(
1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP
][inst_idx][1] + 0x0014), 0); loop--; if (!loop) { printk("\0014"
"[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_DPG_PAUSE", (unsigned)0x00000008L, (unsigned
)(tmp_ & (0x00000008L))); ret = -60; break; } } } while (
0); ret; })
1429 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0014),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000008L)) != (0x00000008L)) { if (old_ != tmp_
) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(
1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP
][inst_idx][1] + 0x0014), 0); loop--; if (!loop) { printk("\0014"
"[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_DPG_PAUSE", (unsigned)0x00000008L, (unsigned
)(tmp_ & (0x00000008L))); ret = -60; break; } } } while (
0); ret; })
1430 UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0014),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000008L)) != (0x00000008L)) { if (old_ != tmp_
) { loop = adev->usec_timeout; old_ = tmp_; } else udelay(
1); tmp_ = amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP
][inst_idx][1] + 0x0014), 0); loop--; if (!loop) { printk("\0014"
"[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_DPG_PAUSE", (unsigned)0x00000008L, (unsigned
)(tmp_ & (0x00000008L))); ret = -60; break; } } } while (
0); ret; });
1431
1432 /* Stall DPG before WPTR/RPTR reset */
1433 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)
), (tmp_), 0); } while (0)
1434 UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK,do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)
), (tmp_), 0); } while (0)
1435 ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0x80000000L) & ~(~0x80000000L)); amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)
), (tmp_), 0); } while (0);
1436
1437 /* Restore */
1438 fw_shared->multi_queue.encode_generalpurpose_queue_mode |= FW_QUEUE_RING_RESET;
1439 ring = &adev->vcn.inst[inst_idx].ring_enc[0];
1440 ring->wptr = 0;
1441 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO, ring->gpu_addr)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00aa), ring->gpu_addr, 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00aa)
), (ring->gpu_addr), 0));
1442 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00ab), ((u32)(((ring->gpu_addr) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x00ab)), (((u32)(((ring->gpu_addr
) >> 16) >> 16))), 0));
1443 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE, ring->ring_size / 4)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00ac), ring->ring_size / 4, 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00ac)
), (ring->ring_size / 4), 0));
1444 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00ad), ((u32)(ring->wptr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00ad)
), (((u32)(ring->wptr))), 0));
1445 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00ae), ((u32)(ring->wptr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00ae)
), (((u32)(ring->wptr))), 0));
1446 fw_shared->multi_queue.encode_generalpurpose_queue_mode &= ~FW_QUEUE_RING_RESET;
1447
1448 fw_shared->multi_queue.encode_lowlatency_queue_mode |= FW_QUEUE_RING_RESET;
1449 ring = &adev->vcn.inst[inst_idx].ring_enc[1];
1450 ring->wptr = 0;
1451 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_LO2, ring->gpu_addr)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00af), ring->gpu_addr, 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00af)
), (ring->gpu_addr), 0));
1452 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00b0), ((u32)(((ring->gpu_addr) >> 16) >>
16)), 0, VCN_HWIP) : amdgpu_device_wreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x00b0)), (((u32)(((ring->gpu_addr
) >> 16) >> 16))), 0));
1453 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_SIZE2, ring->ring_size / 4)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00b1), ring->ring_size / 4, 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00b1)
), (ring->ring_size / 4), 0));
1454 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00b2), ((u32)(ring->wptr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00b2)
), (((u32)(ring->wptr))), 0));
1455 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x00b3), ((u32)(ring->wptr)), 0, VCN_HWIP) : amdgpu_device_wreg
(adev, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x00b3)
), (((u32)(ring->wptr))), 0));
1456 fw_shared->multi_queue.encode_lowlatency_queue_mode &= ~FW_QUEUE_RING_RESET;
1457
1458 /* Unstall DPG */
1459 WREG32_P(SOC15_REG_OFFSET(VCN, inst_idx, mmUVD_POWER_STATUS),do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0) & ~(~0x80000000L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0)
1460 0, ~UVD_POWER_STATUS__STALL_DPG_POWER_UP_MASK)do { uint32_t tmp_ = amdgpu_device_rreg(adev, ((adev->reg_offset
[VCN_HWIP][inst_idx][1] + 0x0004)), 0); tmp_ &= (~0x80000000L
); tmp_ |= ((0) & ~(~0x80000000L)); amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004)), (tmp_
), 0); } while (0);
1461
1462 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ =
tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); loop--;
if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
, (unsigned)(tmp_ & (0x00000003L))); ret = -60; break; } }
} while (0); ret; })
1463 UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
)) { if (old_ != tmp_) { loop = adev->usec_timeout; old_ =
tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg(adev, (adev
->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004), 0); loop--;
if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON
, (unsigned)(tmp_ & (0x00000003L))); ret = -60; break; } }
} while (0); ret; });
1464 }
1465 } else {
1466 reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK0x00000004L;
1467 WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_PAUSE, reg_data)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0014), reg_data, 0, VCN_HWIP) : amdgpu_device_wreg(adev
, ((adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0014)), (reg_data
), 0));
1468 SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 0x1,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (0x1)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)0x1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; })
1469 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][inst_idx][1] + 0x0004),
0); uint32_t loop = adev->usec_timeout; ret = 0; while ((
tmp_ & (0x00000003L)) != (0x1)) { if (old_ != tmp_) { loop
= adev->usec_timeout; old_ = tmp_; } else udelay(1); tmp_
= amdgpu_device_rreg(adev, (adev->reg_offset[VCN_HWIP][inst_idx
][1] + 0x0004), 0); loop--; if (!loop) { printk("\0014" "[" "drm"
"] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, inst_idx, "mmUVD_POWER_STATUS", (unsigned)0x1, (unsigned)(tmp_
& (0x00000003L))); ret = -60; break; } } } while (0); ret
; });
1470 }
1471 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1472 }
1473
1474 return 0;
1475}
1476
1477/**
1478 * vcn_v2_5_dec_ring_get_rptr - get read pointer
1479 *
1480 * @ring: amdgpu_ring pointer
1481 *
1482 * Returns the current hardware read pointer
1483 */
1484static uint64_t vcn_v2_5_dec_ring_get_rptr(struct amdgpu_ring *ring)
1485{
1486 struct amdgpu_device *adev = ring->adev;
1487
1488 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_RPTR)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x02e0, 0, VCN_HWIP) : amdgpu_device_rreg(adev,
(adev->reg_offset[VCN_HWIP][ring->me][1] + 0x02e0), 0)
);
1489}
1490
1491/**
1492 * vcn_v2_5_dec_ring_get_wptr - get write pointer
1493 *
1494 * @ring: amdgpu_ring pointer
1495 *
1496 * Returns the current hardware write pointer
1497 */
1498static uint64_t vcn_v2_5_dec_ring_get_wptr(struct amdgpu_ring *ring)
1499{
1500 struct amdgpu_device *adev = ring->adev;
1501
1502 if (ring->use_doorbell)
1503 return *ring->wptr_cpu_addr;
1504 else
1505 return RREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x02e1, 0, VCN_HWIP) : amdgpu_device_rreg(adev,
(adev->reg_offset[VCN_HWIP][ring->me][1] + 0x02e1), 0)
);
1506}
1507
1508/**
1509 * vcn_v2_5_dec_ring_set_wptr - set write pointer
1510 *
1511 * @ring: amdgpu_ring pointer
1512 *
1513 * Commits the write pointer to the hardware
1514 */
1515static void vcn_v2_5_dec_ring_set_wptr(struct amdgpu_ring *ring)
1516{
1517 struct amdgpu_device *adev = ring->adev;
1518
1519 if (ring->use_doorbell) {
1520 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr)((u32)(ring->wptr));
1521 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr))amdgpu_mm_wdoorbell(adev, (ring->doorbell_index), (((u32)(
ring->wptr))));
1522 } else {
1523 WREG32_SOC15(VCN, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x02e1), ((u32)(ring->wptr)), 0, VCN_HWIP) :
amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x02e1)), (((u32)(ring->wptr))), 0));
1524 }
1525}
1526
1527static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
1528 .type = AMDGPU_RING_TYPE_VCN_DEC,
1529 .align_mask = 0xf,
1530 .secure_submission_supported = true1,
1531 .vmhub = AMDGPU_MMHUB_12,
1532 .get_rptr = vcn_v2_5_dec_ring_get_rptr,
1533 .get_wptr = vcn_v2_5_dec_ring_get_wptr,
1534 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1535 .emit_frame_size =
1536 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 6 +
1537 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 8 +
1538 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1539 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1540 6,
1541 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1542 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1543 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1544 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1545 .test_ring = vcn_v2_0_dec_ring_test_ring,
1546 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1547 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1548 .insert_start = vcn_v2_0_dec_ring_insert_start,
1549 .insert_end = vcn_v2_0_dec_ring_insert_end,
1550 .pad_ib = amdgpu_ring_generic_pad_ib,
1551 .begin_use = amdgpu_vcn_ring_begin_use,
1552 .end_use = amdgpu_vcn_ring_end_use,
1553 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1554 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1555 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1556};
1557
1558static const struct amdgpu_ring_funcs vcn_v2_6_dec_ring_vm_funcs = {
1559 .type = AMDGPU_RING_TYPE_VCN_DEC,
1560 .align_mask = 0xf,
1561 .secure_submission_supported = true1,
1562 .vmhub = AMDGPU_MMHUB_01,
1563 .get_rptr = vcn_v2_5_dec_ring_get_rptr,
1564 .get_wptr = vcn_v2_5_dec_ring_get_wptr,
1565 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1566 .emit_frame_size =
1567 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 6 +
1568 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 8 +
1569 8 + /* vcn_v2_0_dec_ring_emit_vm_flush */
1570 14 + 14 + /* vcn_v2_0_dec_ring_emit_fence x2 vm fence */
1571 6,
1572 .emit_ib_size = 8, /* vcn_v2_0_dec_ring_emit_ib */
1573 .emit_ib = vcn_v2_0_dec_ring_emit_ib,
1574 .emit_fence = vcn_v2_0_dec_ring_emit_fence,
1575 .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
1576 .test_ring = vcn_v2_0_dec_ring_test_ring,
1577 .test_ib = amdgpu_vcn_dec_ring_test_ib,
1578 .insert_nop = vcn_v2_0_dec_ring_insert_nop,
1579 .insert_start = vcn_v2_0_dec_ring_insert_start,
1580 .insert_end = vcn_v2_0_dec_ring_insert_end,
1581 .pad_ib = amdgpu_ring_generic_pad_ib,
1582 .begin_use = amdgpu_vcn_ring_begin_use,
1583 .end_use = amdgpu_vcn_ring_end_use,
1584 .emit_wreg = vcn_v2_0_dec_ring_emit_wreg,
1585 .emit_reg_wait = vcn_v2_0_dec_ring_emit_reg_wait,
1586 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1587};
1588
1589/**
1590 * vcn_v2_5_enc_ring_get_rptr - get enc read pointer
1591 *
1592 * @ring: amdgpu_ring pointer
1593 *
1594 * Returns the current hardware enc read pointer
1595 */
1596static uint64_t vcn_v2_5_enc_ring_get_rptr(struct amdgpu_ring *ring)
1597{
1598 struct amdgpu_device *adev = ring->adev;
1599
1600 if (ring == &adev->vcn.inst[ring->me].ring_enc[0])
1601 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x00ad, 0, VCN_HWIP) : amdgpu_device_rreg(adev,
(adev->reg_offset[VCN_HWIP][ring->me][1] + 0x00ad), 0)
);
1602 else
1603 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_RPTR2)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x00b2, 0, VCN_HWIP) : amdgpu_device_rreg(adev,
(adev->reg_offset[VCN_HWIP][ring->me][1] + 0x00b2), 0)
);
1604}
1605
1606/**
1607 * vcn_v2_5_enc_ring_get_wptr - get enc write pointer
1608 *
1609 * @ring: amdgpu_ring pointer
1610 *
1611 * Returns the current hardware enc write pointer
1612 */
1613static uint64_t vcn_v2_5_enc_ring_get_wptr(struct amdgpu_ring *ring)
1614{
1615 struct amdgpu_device *adev = ring->adev;
1616
1617 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1618 if (ring->use_doorbell)
1619 return *ring->wptr_cpu_addr;
1620 else
1621 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x00ae, 0, VCN_HWIP) : amdgpu_device_rreg(adev,
(adev->reg_offset[VCN_HWIP][ring->me][1] + 0x00ae), 0)
);
1622 } else {
1623 if (ring->use_doorbell)
1624 return *ring->wptr_cpu_addr;
1625 else
1626 return RREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x00b3, 0, VCN_HWIP) : amdgpu_device_rreg(adev,
(adev->reg_offset[VCN_HWIP][ring->me][1] + 0x00b3), 0)
);
1627 }
1628}
1629
1630/**
1631 * vcn_v2_5_enc_ring_set_wptr - set enc write pointer
1632 *
1633 * @ring: amdgpu_ring pointer
1634 *
1635 * Commits the enc write pointer to the hardware
1636 */
1637static void vcn_v2_5_enc_ring_set_wptr(struct amdgpu_ring *ring)
1638{
1639 struct amdgpu_device *adev = ring->adev;
1640
1641 if (ring == &adev->vcn.inst[ring->me].ring_enc[0]) {
1642 if (ring->use_doorbell) {
1643 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr)((u32)(ring->wptr));
1644 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr))amdgpu_mm_wdoorbell(adev, (ring->doorbell_index), (((u32)(
ring->wptr))));
1645 } else {
1646 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x00ae), ((u32)(ring->wptr)), 0, VCN_HWIP) :
amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x00ae)), (((u32)(ring->wptr))), 0));
1647 }
1648 } else {
1649 if (ring->use_doorbell) {
1650 *ring->wptr_cpu_addr = lower_32_bits(ring->wptr)((u32)(ring->wptr));
1651 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr))amdgpu_mm_wdoorbell(adev, (ring->doorbell_index), (((u32)(
ring->wptr))));
1652 } else {
1653 WREG32_SOC15(VCN, ring->me, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr))((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_wreg(adev, (adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x00b3), ((u32)(ring->wptr)), 0, VCN_HWIP) :
amdgpu_device_wreg(adev, ((adev->reg_offset[VCN_HWIP][ring
->me][1] + 0x00b3)), (((u32)(ring->wptr))), 0));
1654 }
1655 }
1656}
1657
1658static const struct amdgpu_ring_funcs vcn_v2_5_enc_ring_vm_funcs = {
1659 .type = AMDGPU_RING_TYPE_VCN_ENC,
1660 .align_mask = 0x3f,
1661 .nop = VCN_ENC_CMD_NO_OP0x00000000,
1662 .vmhub = AMDGPU_MMHUB_12,
1663 .get_rptr = vcn_v2_5_enc_ring_get_rptr,
1664 .get_wptr = vcn_v2_5_enc_ring_get_wptr,
1665 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
1666 .emit_frame_size =
1667 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 3 +
1668 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 4 +
1669 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1670 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1671 1, /* vcn_v2_0_enc_ring_insert_end */
1672 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1673 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1674 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1675 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1676 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1677 .test_ib = amdgpu_vcn_enc_ring_test_ib,
1678 .insert_nop = amdgpu_ring_insert_nop,
1679 .insert_end = vcn_v2_0_enc_ring_insert_end,
1680 .pad_ib = amdgpu_ring_generic_pad_ib,
1681 .begin_use = amdgpu_vcn_ring_begin_use,
1682 .end_use = amdgpu_vcn_ring_end_use,
1683 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1684 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1685 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1686};
1687
1688static const struct amdgpu_ring_funcs vcn_v2_6_enc_ring_vm_funcs = {
1689 .type = AMDGPU_RING_TYPE_VCN_ENC,
1690 .align_mask = 0x3f,
1691 .nop = VCN_ENC_CMD_NO_OP0x00000000,
1692 .vmhub = AMDGPU_MMHUB_01,
1693 .get_rptr = vcn_v2_5_enc_ring_get_rptr,
1694 .get_wptr = vcn_v2_5_enc_ring_get_wptr,
1695 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
1696 .emit_frame_size =
1697 SOC15_FLUSH_GPU_TLB_NUM_WREG6 * 3 +
1698 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT3 * 4 +
1699 4 + /* vcn_v2_0_enc_ring_emit_vm_flush */
1700 5 + 5 + /* vcn_v2_0_enc_ring_emit_fence x2 vm fence */
1701 1, /* vcn_v2_0_enc_ring_insert_end */
1702 .emit_ib_size = 5, /* vcn_v2_0_enc_ring_emit_ib */
1703 .emit_ib = vcn_v2_0_enc_ring_emit_ib,
1704 .emit_fence = vcn_v2_0_enc_ring_emit_fence,
1705 .emit_vm_flush = vcn_v2_0_enc_ring_emit_vm_flush,
1706 .test_ring = amdgpu_vcn_enc_ring_test_ring,
1707 .test_ib = amdgpu_vcn_enc_ring_test_ib,
1708 .insert_nop = amdgpu_ring_insert_nop,
1709 .insert_end = vcn_v2_0_enc_ring_insert_end,
1710 .pad_ib = amdgpu_ring_generic_pad_ib,
1711 .begin_use = amdgpu_vcn_ring_begin_use,
1712 .end_use = amdgpu_vcn_ring_end_use,
1713 .emit_wreg = vcn_v2_0_enc_ring_emit_wreg,
1714 .emit_reg_wait = vcn_v2_0_enc_ring_emit_reg_wait,
1715 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1716};
1717
1718static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev)
1719{
1720 int i;
1721
1722 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1723 if (adev->vcn.harvest_config & (1 << i))
1724 continue;
1725 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0)(((2) << 16) | ((5) << 8) | (0)))
1726 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_5_dec_ring_vm_funcs;
1727 else /* CHIP_ALDEBARAN */
1728 adev->vcn.inst[i].ring_dec.funcs = &vcn_v2_6_dec_ring_vm_funcs;
1729 adev->vcn.inst[i].ring_dec.me = i;
1730 DRM_INFO("VCN(%d) decode is enabled in VM mode\n", i)printk("\0016" "[" "drm" "] " "VCN(%d) decode is enabled in VM mode\n"
, i);
1731 }
1732}
1733
1734static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev)
1735{
1736 int i, j;
1737
1738 for (j = 0; j < adev->vcn.num_vcn_inst; ++j) {
1739 if (adev->vcn.harvest_config & (1 << j))
1740 continue;
1741 for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
1742 if (adev->ip_versions[UVD_HWIP][0] == IP_VERSION(2, 5, 0)(((2) << 16) | ((5) << 8) | (0)))
1743 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_5_enc_ring_vm_funcs;
1744 else /* CHIP_ALDEBARAN */
1745 adev->vcn.inst[j].ring_enc[i].funcs = &vcn_v2_6_enc_ring_vm_funcs;
1746 adev->vcn.inst[j].ring_enc[i].me = j;
1747 }
1748 DRM_INFO("VCN(%d) encode is enabled in VM mode\n", j)printk("\0016" "[" "drm" "] " "VCN(%d) encode is enabled in VM mode\n"
, j);
1749 }
1750}
1751
1752static bool_Bool vcn_v2_5_is_idle(void *handle)
1753{
1754 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1755 int i, ret = 1;
1756
1757 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1758 if (adev->vcn.harvest_config & (1 << i))
1759 continue;
1760 ret &= (RREG32_SOC15(VCN, i, mmUVD_STATUS)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][i][
1] + 0x0080, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][i][1] + 0x0080), 0)) == UVD_STATUS__IDLE);
1761 }
1762
1763 return ret;
1764}
1765
1766static int vcn_v2_5_wait_for_idle(void *handle)
1767{
1768 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1769 int i, ret = 0;
1770
1771 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1772 if (adev->vcn.harvest_config & (1 << i))
1773 continue;
1774 ret = SOC15_WAIT_ON_RREG(VCN, i, mmUVD_STATUS, UVD_STATUS__IDLE,({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); uint32_t
loop = adev->usec_timeout; ret = 0; while ((tmp_ & (UVD_STATUS__IDLE
)) != (UVD_STATUS__IDLE)) { if (old_ != tmp_) { loop = adev->
usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); loop
--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, i, "mmUVD_STATUS", (unsigned)UVD_STATUS__IDLE, (unsigned)(tmp_
& (UVD_STATUS__IDLE))); ret = -60; break; } } } while (0
); ret; })
1775 UVD_STATUS__IDLE)({ int ret = 0; do { uint32_t old_ = 0; uint32_t tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); uint32_t
loop = adev->usec_timeout; ret = 0; while ((tmp_ & (UVD_STATUS__IDLE
)) != (UVD_STATUS__IDLE)) { if (old_ != tmp_) { loop = adev->
usec_timeout; old_ = tmp_; } else udelay(1); tmp_ = amdgpu_device_rreg
(adev, (adev->reg_offset[VCN_HWIP][i][1] + 0x0080), 0); loop
--; if (!loop) { printk("\0014" "[" "drm" "] " "Register(%d) [%s] failed to reach value 0x%08x != 0x%08x\n"
, i, "mmUVD_STATUS", (unsigned)UVD_STATUS__IDLE, (unsigned)(tmp_
& (UVD_STATUS__IDLE))); ret = -60; break; } } } while (0
); ret; });
1776 if (ret)
1777 return ret;
1778 }
1779
1780 return ret;
1781}
1782
1783static int vcn_v2_5_set_clockgating_state(void *handle,
1784 enum amd_clockgating_state state)
1785{
1786 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1787 bool_Bool enable = (state == AMD_CG_STATE_GATE);
1788
1789 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
1790 return 0;
1791
1792 if (enable) {
1793 if (!vcn_v2_5_is_idle(handle))
1794 return -EBUSY16;
1795 vcn_v2_5_enable_clock_gating(adev);
1796 } else {
1797 vcn_v2_5_disable_clock_gating(adev);
1798 }
1799
1800 return 0;
1801}
1802
1803static int vcn_v2_5_set_powergating_state(void *handle,
1804 enum amd_powergating_state state)
1805{
1806 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1807 int ret;
1808
1809 if (amdgpu_sriov_vf(adev)((adev)->virt.caps & (1 << 2)))
1810 return 0;
1811
1812 if(state == adev->vcn.cur_state)
1813 return 0;
1814
1815 if (state == AMD_PG_STATE_GATE)
1816 ret = vcn_v2_5_stop(adev);
1817 else
1818 ret = vcn_v2_5_start(adev);
1819
1820 if(!ret)
1821 adev->vcn.cur_state = state;
1822
1823 return ret;
1824}
1825
1826static int vcn_v2_5_set_interrupt_state(struct amdgpu_device *adev,
1827 struct amdgpu_irq_src *source,
1828 unsigned type,
1829 enum amdgpu_interrupt_state state)
1830{
1831 return 0;
1832}
1833
1834static int vcn_v2_5_process_interrupt(struct amdgpu_device *adev,
1835 struct amdgpu_irq_src *source,
1836 struct amdgpu_iv_entry *entry)
1837{
1838 uint32_t ip_instance;
1839
1840 switch (entry->client_id) {
1841 case SOC15_IH_CLIENTID_VCN:
1842 ip_instance = 0;
1843 break;
1844 case SOC15_IH_CLIENTID_VCN1:
1845 ip_instance = 1;
1846 break;
1847 default:
1848 DRM_ERROR("Unhandled client id: %d\n", entry->client_id)__drm_err("Unhandled client id: %d\n", entry->client_id);
1849 return 0;
1850 }
1851
1852 DRM_DEBUG("IH: VCN TRAP\n")___drm_dbg(((void *)0), DRM_UT_CORE, "IH: VCN TRAP\n");
1853
1854 switch (entry->src_id) {
1855 case VCN_2_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT124:
1856 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_dec);
1857 break;
1858 case VCN_2_0__SRCID__UVD_ENC_GENERAL_PURPOSE119:
1859 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[0]);
1860 break;
1861 case VCN_2_0__SRCID__UVD_ENC_LOW_LATENCY120:
1862 amdgpu_fence_process(&adev->vcn.inst[ip_instance].ring_enc[1]);
1863 break;
1864 case VCN_2_6__SRCID_UVD_POISON160:
1865 amdgpu_vcn_process_poison_irq(adev, source, entry);
1866 break;
1867 default:
1868 DRM_ERROR("Unhandled interrupt: %d %d\n",__drm_err("Unhandled interrupt: %d %d\n", entry->src_id, entry
->src_data[0])
1869 entry->src_id, entry->src_data[0])__drm_err("Unhandled interrupt: %d %d\n", entry->src_id, entry
->src_data[0]);
1870 break;
1871 }
1872
1873 return 0;
1874}
1875
1876static const struct amdgpu_irq_src_funcs vcn_v2_5_irq_funcs = {
1877 .set = vcn_v2_5_set_interrupt_state,
1878 .process = vcn_v2_5_process_interrupt,
1879};
1880
1881static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev)
1882{
1883 int i;
1884
1885 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
1886 if (adev->vcn.harvest_config & (1 << i))
1887 continue;
1888 adev->vcn.inst[i].irq.num_types = adev->vcn.num_enc_rings + 1;
1889 adev->vcn.inst[i].irq.funcs = &vcn_v2_5_irq_funcs;
1890 }
1891}
1892
1893static const struct amd_ip_funcs vcn_v2_5_ip_funcs = {
1894 .name = "vcn_v2_5",
1895 .early_init = vcn_v2_5_early_init,
1896 .late_init = NULL((void *)0),
1897 .sw_init = vcn_v2_5_sw_init,
1898 .sw_fini = vcn_v2_5_sw_fini,
1899 .hw_init = vcn_v2_5_hw_init,
1900 .hw_fini = vcn_v2_5_hw_fini,
1901 .suspend = vcn_v2_5_suspend,
1902 .resume = vcn_v2_5_resume,
1903 .is_idle = vcn_v2_5_is_idle,
1904 .wait_for_idle = vcn_v2_5_wait_for_idle,
1905 .check_soft_reset = NULL((void *)0),
1906 .pre_soft_reset = NULL((void *)0),
1907 .soft_reset = NULL((void *)0),
1908 .post_soft_reset = NULL((void *)0),
1909 .set_clockgating_state = vcn_v2_5_set_clockgating_state,
1910 .set_powergating_state = vcn_v2_5_set_powergating_state,
1911};
1912
1913static const struct amd_ip_funcs vcn_v2_6_ip_funcs = {
1914 .name = "vcn_v2_6",
1915 .early_init = vcn_v2_5_early_init,
1916 .late_init = NULL((void *)0),
1917 .sw_init = vcn_v2_5_sw_init,
1918 .sw_fini = vcn_v2_5_sw_fini,
1919 .hw_init = vcn_v2_5_hw_init,
1920 .hw_fini = vcn_v2_5_hw_fini,
1921 .suspend = vcn_v2_5_suspend,
1922 .resume = vcn_v2_5_resume,
1923 .is_idle = vcn_v2_5_is_idle,
1924 .wait_for_idle = vcn_v2_5_wait_for_idle,
1925 .check_soft_reset = NULL((void *)0),
1926 .pre_soft_reset = NULL((void *)0),
1927 .soft_reset = NULL((void *)0),
1928 .post_soft_reset = NULL((void *)0),
1929 .set_clockgating_state = vcn_v2_5_set_clockgating_state,
1930 .set_powergating_state = vcn_v2_5_set_powergating_state,
1931};
1932
1933const struct amdgpu_ip_block_version vcn_v2_5_ip_block =
1934{
1935 .type = AMD_IP_BLOCK_TYPE_VCN,
1936 .major = 2,
1937 .minor = 5,
1938 .rev = 0,
1939 .funcs = &vcn_v2_5_ip_funcs,
1940};
1941
1942const struct amdgpu_ip_block_version vcn_v2_6_ip_block =
1943{
1944 .type = AMD_IP_BLOCK_TYPE_VCN,
1945 .major = 2,
1946 .minor = 6,
1947 .rev = 0,
1948 .funcs = &vcn_v2_6_ip_funcs,
1949};
1950
1951static uint32_t vcn_v2_6_query_poison_by_instance(struct amdgpu_device *adev,
1952 uint32_t instance, uint32_t sub_block)
1953{
1954 uint32_t poison_stat = 0, reg_value = 0;
1955
1956 switch (sub_block) {
1957 case AMDGPU_VCN_V2_6_VCPU_VCODEC:
1958 reg_value = RREG32_SOC15(VCN, instance, mmUVD_RAS_VCPU_VCODEC_STATUS)((((adev)->virt.caps & (1 << 2)) && adev
->gfx.rlc.funcs && adev->gfx.rlc.rlcg_reg_access_supported
) ? amdgpu_sriov_rreg(adev, adev->reg_offset[VCN_HWIP][instance
][1] + 0x0057, 0, VCN_HWIP) : amdgpu_device_rreg(adev, (adev->
reg_offset[VCN_HWIP][instance][1] + 0x0057), 0));
1959 poison_stat = REG_GET_FIELD(reg_value, UVD_RAS_VCPU_VCODEC_STATUS, POISONED_PF)(((reg_value) & 0x80000000L) >> 0x1f);
1960 break;
1961 default:
1962 break;
1963 }
1964
1965 if (poison_stat)
1966 dev_info(adev->dev, "Poison detected in VCN%d, sub_block%d\n",do { } while(0)
1967 instance, sub_block)do { } while(0);
1968
1969 return poison_stat;
1970}
1971
1972static bool_Bool vcn_v2_6_query_poison_status(struct amdgpu_device *adev)
1973{
1974 uint32_t inst, sub;
1975 uint32_t poison_stat = 0;
1976
1977 for (inst = 0; inst < adev->vcn.num_vcn_inst; inst++)
1978 for (sub = 0; sub < AMDGPU_VCN_V2_6_MAX_SUB_BLOCK; sub++)
1979 poison_stat +=
1980 vcn_v2_6_query_poison_by_instance(adev, inst, sub);
1981
1982 return !!poison_stat;
1983}
1984
1985const struct amdgpu_ras_block_hw_ops vcn_v2_6_ras_hw_ops = {
1986 .query_poison_status = vcn_v2_6_query_poison_status,
1987};
1988
1989static struct amdgpu_vcn_ras vcn_v2_6_ras = {
1990 .ras_block = {
1991 .hw_ops = &vcn_v2_6_ras_hw_ops,
1992 },
1993};
1994
1995static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev)
1996{
1997 switch (adev->ip_versions[VCN_HWIP][0]) {
1998 case IP_VERSION(2, 6, 0)(((2) << 16) | ((6) << 8) | (0)):
1999 adev->vcn.ras = &vcn_v2_6_ras;
2000 break;
2001 default:
2002 break;
2003 }
2004
2005 if (adev->vcn.ras) {
2006 amdgpu_ras_register_ras_block(adev, &adev->vcn.ras->ras_block);
2007
2008 strlcpy(adev->vcn.ras->ras_block.ras_comm.name, "vcn",
2009 sizeof(adev->vcn.ras->ras_block.ras_comm.name));
2010 adev->vcn.ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN;
2011 adev->vcn.ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON;
2012 adev->vcn.ras_if = &adev->vcn.ras->ras_block.ras_comm;
2013
2014 /* If don't define special ras_late_init function, use default ras_late_init */
2015 if (!adev->vcn.ras->ras_block.ras_late_init)
2016 adev->vcn.ras->ras_block.ras_late_init = amdgpu_ras_block_late_init;
2017 }
2018}